| blob | 30cc060d05bb15993703b8fedef01c12beaac7e0 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-SDAG,SI-SDAG %s
3 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI,GCN-GISEL,SI-GISEL %s
4 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-SDAG,VI-SDAG %s
5 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI,GCN-GISEL,VI-GISEL %s
6 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-SDAG,GFX900-SDAG %s
7 ; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900,GCN-GISEL,GFX900-GISEL %s
9 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
10 ; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM %s
12 define amdgpu_kernel void @s_exp2_f32(ptr addrspace(1) %out, float %in) {
13 ; SI-SDAG-LABEL: s_exp2_f32:
14 ; SI-SDAG: ; %bb.0:
15 ; SI-SDAG-NEXT: s_load_dword s2, s[4:5], 0xb
16 ; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
17 ; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
18 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
19 ; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
20 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
21 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
22 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
23 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42800000
24 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
25 ; SI-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
26 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
27 ; SI-SDAG-NEXT: s_mov_b32 s2, -1
28 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, v1, v0
29 ; SI-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
30 ; SI-SDAG-NEXT: s_endpgm
31 ;
32 ; SI-GISEL-LABEL: s_exp2_f32:
33 ; SI-GISEL: ; %bb.0:
34 ; SI-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb
35 ; SI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
36 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
37 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
38 ; SI-GISEL-NEXT: s_mov_b32 s3, 0xf000
39 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
40 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
41 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
42 ; SI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
43 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
44 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
45 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
46 ; SI-GISEL-NEXT: s_mov_b32 s2, -1
47 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
48 ; SI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
49 ; SI-GISEL-NEXT: s_endpgm
50 ;
51 ; VI-SDAG-LABEL: s_exp2_f32:
52 ; VI-SDAG: ; %bb.0:
53 ; VI-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
54 ; VI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
55 ; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
56 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
57 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
58 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
59 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
60 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42800000
61 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
62 ; VI-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
63 ; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
64 ; VI-SDAG-NEXT: v_mul_f32_e32 v2, v1, v0
65 ; VI-SDAG-NEXT: v_mov_b32_e32 v0, s0
66 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, s1
67 ; VI-SDAG-NEXT: flat_store_dword v[0:1], v2
68 ; VI-SDAG-NEXT: s_endpgm
69 ;
70 ; VI-GISEL-LABEL: s_exp2_f32:
71 ; VI-GISEL: ; %bb.0:
72 ; VI-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
73 ; VI-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
74 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
75 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
76 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
77 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
78 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
79 ; VI-GISEL-NEXT: v_add_f32_e32 v0, s2, v0
80 ; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
81 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
82 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
83 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, v0, v1
84 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
85 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
86 ; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
87 ; VI-GISEL-NEXT: s_endpgm
88 ;
89 ; GFX900-SDAG-LABEL: s_exp2_f32:
90 ; GFX900-SDAG: ; %bb.0:
91 ; GFX900-SDAG-NEXT: s_load_dword s2, s[4:5], 0x2c
92 ; GFX900-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
93 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
94 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
95 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0
96 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
97 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
98 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
99 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42800000
100 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
101 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
102 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
103 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v1, v0
104 ; GFX900-SDAG-NEXT: global_store_dword v2, v0, s[0:1]
105 ; GFX900-SDAG-NEXT: s_endpgm
106 ;
107 ; GFX900-GISEL-LABEL: s_exp2_f32:
108 ; GFX900-GISEL: ; %bb.0:
109 ; GFX900-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
110 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
111 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
112 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
113 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
114 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
115 ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s0, v0
116 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
117 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
118 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
119 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
120 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
121 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0
122 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
123 ; GFX900-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
124 ; GFX900-GISEL-NEXT: s_endpgm
125 ;
126 ; R600-LABEL: s_exp2_f32:
127 ; R600: ; %bb.0:
128 ; R600-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]
129 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
130 ; R600-NEXT: CF_END
131 ; R600-NEXT: PAD
132 ; R600-NEXT: ALU clause starting at 4:
133 ; R600-NEXT: SETGT * T0.W, literal.x, KC0[2].Z,
134 ; R600-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
135 ; R600-NEXT: CNDE * T1.W, PV.W, 0.0, literal.x,
136 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
137 ; R600-NEXT: ADD T1.W, KC0[2].Z, PV.W,
138 ; R600-NEXT: CNDE * T0.W, T0.W, 1.0, literal.x,
139 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
140 ; R600-NEXT: EXP_IEEE * T0.X, PV.W,
141 ; R600-NEXT: MUL_IEEE T0.X, PS, T0.W,
142 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
143 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
144 ;
145 ; CM-LABEL: s_exp2_f32:
146 ; CM: ; %bb.0:
147 ; CM-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
148 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X
149 ; CM-NEXT: CF_END
150 ; CM-NEXT: PAD
151 ; CM-NEXT: ALU clause starting at 4:
152 ; CM-NEXT: SETGT * T0.W, literal.x, KC0[2].Z,
153 ; CM-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
154 ; CM-NEXT: CNDE * T1.W, PV.W, 0.0, literal.x,
155 ; CM-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
156 ; CM-NEXT: CNDE T0.Z, T0.W, 1.0, literal.x,
157 ; CM-NEXT: ADD * T0.W, KC0[2].Z, PV.W,
158 ; CM-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
159 ; CM-NEXT: EXP_IEEE T0.X, T0.W,
160 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,
161 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
162 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
163 ; CM-NEXT: MUL_IEEE * T0.X, PV.X, T0.Z,
164 ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
165 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
166 %result = call float @llvm.exp2.f32(float %in)
167 store float %result, ptr addrspace(1) %out
168 ret void
169 }
171 ; FIXME: We should be able to merge these packets together on Cayman so we
172 ; have a maximum of 4 instructions.
173 define amdgpu_kernel void @s_exp2_v2f32(ptr addrspace(1) %out, <2 x float> %in) {
174 ; SI-SDAG-LABEL: s_exp2_v2f32:
175 ; SI-SDAG: ; %bb.0:
176 ; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
177 ; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
178 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
179 ; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
180 ; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
181 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
182 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
183 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
184 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
185 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
186 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
187 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
188 ; SI-SDAG-NEXT: v_add_f32_e32 v4, s3, v4
189 ; SI-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
190 ; SI-SDAG-NEXT: v_exp_f32_e32 v4, v4
191 ; SI-SDAG-NEXT: v_exp_f32_e32 v3, v1
192 ; SI-SDAG-NEXT: s_mov_b32 s6, -1
193 ; SI-SDAG-NEXT: s_mov_b32 s4, s0
194 ; SI-SDAG-NEXT: s_mov_b32 s5, s1
195 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, v4, v2
196 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, v3, v0
197 ; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
198 ; SI-SDAG-NEXT: s_endpgm
199 ;
200 ; SI-GISEL-LABEL: s_exp2_v2f32:
201 ; SI-GISEL: ; %bb.0:
202 ; SI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
203 ; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
204 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
205 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000
206 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
207 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
208 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
209 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
210 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
211 ; SI-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
212 ; SI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
213 ; SI-GISEL-NEXT: v_exp_f32_e32 v3, v3
214 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v0
215 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc
216 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1]
217 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0
218 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v2
219 ; SI-GISEL-NEXT: s_mov_b32 s6, -1
220 ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
221 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
222 ; SI-GISEL-NEXT: s_endpgm
223 ;
224 ; VI-SDAG-LABEL: s_exp2_v2f32:
225 ; VI-SDAG: ; %bb.0:
226 ; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
227 ; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
228 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
229 ; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
230 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
231 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
232 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v3, 1.0, v1, vcc
233 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
234 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
235 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
236 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
237 ; VI-SDAG-NEXT: v_add_f32_e32 v4, s3, v4
238 ; VI-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
239 ; VI-SDAG-NEXT: v_exp_f32_e32 v4, v4
240 ; VI-SDAG-NEXT: v_exp_f32_e32 v2, v1
241 ; VI-SDAG-NEXT: v_mul_f32_e32 v1, v4, v3
242 ; VI-SDAG-NEXT: v_mul_f32_e32 v0, v2, v0
243 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, s1
244 ; VI-SDAG-NEXT: v_mov_b32_e32 v2, s0
245 ; VI-SDAG-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
246 ; VI-SDAG-NEXT: s_endpgm
247 ;
248 ; VI-GISEL-LABEL: s_exp2_v2f32:
249 ; VI-GISEL: ; %bb.0:
250 ; VI-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24
251 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
252 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
253 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000
254 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
255 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
256 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s7, v0
257 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
258 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
259 ; VI-GISEL-NEXT: v_add_f32_e32 v3, s6, v3
260 ; VI-GISEL-NEXT: v_add_f32_e32 v0, s7, v0
261 ; VI-GISEL-NEXT: v_exp_f32_e32 v3, v3
262 ; VI-GISEL-NEXT: v_exp_f32_e32 v1, v0
263 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc
264 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1]
265 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0
266 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v2
267 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, s4
268 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s5
269 ; VI-GISEL-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
270 ; VI-GISEL-NEXT: s_endpgm
271 ;
272 ; GFX900-SDAG-LABEL: s_exp2_v2f32:
273 ; GFX900-SDAG: ; %bb.0:
274 ; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
275 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
276 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
277 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
278 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v5, 0
279 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
280 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
281 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v3, 1.0, v1, vcc
282 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
283 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
284 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
285 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
286 ; GFX900-SDAG-NEXT: v_add_f32_e32 v4, s3, v4
287 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, s2, v1
288 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v4, v4
289 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v1
290 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, v4, v3
291 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v2, v0
292 ; GFX900-SDAG-NEXT: global_store_dwordx2 v5, v[0:1], s[0:1]
293 ; GFX900-SDAG-NEXT: s_endpgm
294 ;
295 ; GFX900-GISEL-LABEL: s_exp2_v2f32:
296 ; GFX900-GISEL: ; %bb.0:
297 ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
298 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
299 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
300 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x1f800000
301 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
302 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v0
303 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v0
304 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v3, 0, v1, vcc
305 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
306 ; GFX900-GISEL-NEXT: v_add_f32_e32 v3, s10, v3
307 ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s11, v0
308 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v3
309 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v0
310 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 1.0, v2, vcc
311 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 1.0, v2, s[0:1]
312 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v3, v0
313 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v1, v2
314 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0
315 ; GFX900-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
316 ; GFX900-GISEL-NEXT: s_endpgm
317 ;
318 ; R600-LABEL: s_exp2_v2f32:
319 ; R600: ; %bb.0:
320 ; R600-NEXT: ALU 18, @4, KC0[CB0:0-32], KC1[]
321 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
322 ; R600-NEXT: CF_END
323 ; R600-NEXT: PAD
324 ; R600-NEXT: ALU clause starting at 4:
325 ; R600-NEXT: SETGT T0.W, literal.x, KC0[3].X,
326 ; R600-NEXT: SETGT * T1.W, literal.x, KC0[2].W,
327 ; R600-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
328 ; R600-NEXT: CNDE * T2.W, PV.W, 0.0, literal.x,
329 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
330 ; R600-NEXT: ADD T2.W, KC0[3].X, PV.W,
331 ; R600-NEXT: CNDE * T3.W, T1.W, 0.0, literal.x,
332 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
333 ; R600-NEXT: ADD T0.Z, KC0[2].W, PS,
334 ; R600-NEXT: CNDE T0.W, T0.W, 1.0, literal.x,
335 ; R600-NEXT: EXP_IEEE * T0.X, PV.W,
336 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
337 ; R600-NEXT: MUL_IEEE T0.Y, PS, PV.W,
338 ; R600-NEXT: CNDE T0.W, T1.W, 1.0, literal.x,
339 ; R600-NEXT: EXP_IEEE * T0.X, PV.Z,
340 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
341 ; R600-NEXT: MUL_IEEE T0.X, PS, PV.W,
342 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
343 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
344 ;
345 ; CM-LABEL: s_exp2_v2f32:
346 ; CM: ; %bb.0:
347 ; CM-NEXT: ALU 23, @4, KC0[CB0:0-32], KC1[]
348 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T0.X
349 ; CM-NEXT: CF_END
350 ; CM-NEXT: PAD
351 ; CM-NEXT: ALU clause starting at 4:
352 ; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].X,
353 ; CM-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
354 ; CM-NEXT: CNDE T0.Z, PV.W, 0.0, literal.x,
355 ; CM-NEXT: SETGT * T1.W, literal.y, KC0[2].W,
356 ; CM-NEXT: 1115684864(6.400000e+01), -1023672320(-1.260000e+02)
357 ; CM-NEXT: CNDE T0.Y, PV.W, 0.0, literal.x,
358 ; CM-NEXT: CNDE T1.Z, T0.W, 1.0, literal.y,
359 ; CM-NEXT: ADD * T0.W, KC0[3].X, PV.Z,
360 ; CM-NEXT: 1115684864(6.400000e+01), 528482304(5.421011e-20)
361 ; CM-NEXT: EXP_IEEE T0.X, T0.W,
362 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,
363 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
364 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
365 ; CM-NEXT: MUL_IEEE T1.Y, PV.X, T1.Z,
366 ; CM-NEXT: CNDE T0.Z, T1.W, 1.0, literal.x,
367 ; CM-NEXT: ADD * T0.W, KC0[2].W, T0.Y,
368 ; CM-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
369 ; CM-NEXT: EXP_IEEE T0.X, T0.W,
370 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,
371 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
372 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
373 ; CM-NEXT: MUL_IEEE * T1.X, PV.X, T0.Z,
374 ; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
375 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
376 %result = call <2 x float> @llvm.exp2.v2f32(<2 x float> %in)
377 store <2 x float> %result, ptr addrspace(1) %out
378 ret void
379 }
381 define amdgpu_kernel void @s_exp2_v3f32(ptr addrspace(1) %out, <3 x float> %in) {
382 ; SI-SDAG-LABEL: s_exp2_v3f32:
383 ; SI-SDAG: ; %bb.0:
384 ; SI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
385 ; SI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
386 ; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
387 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
388 ; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
389 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
390 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
391 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
392 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
393 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
394 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v1, vcc
395 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
396 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
397 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
398 ; SI-SDAG-NEXT: v_add_f32_e32 v4, s1, v4
399 ; SI-SDAG-NEXT: v_add_f32_e32 v0, s2, v0
400 ; SI-SDAG-NEXT: v_exp_f32_e32 v4, v4
401 ; SI-SDAG-NEXT: v_add_f32_e32 v6, s0, v6
402 ; SI-SDAG-NEXT: v_exp_f32_e32 v3, v0
403 ; SI-SDAG-NEXT: v_exp_f32_e32 v6, v6
404 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v7, 1.0, v1, vcc
405 ; SI-SDAG-NEXT: s_mov_b32 s7, 0xf000
406 ; SI-SDAG-NEXT: s_mov_b32 s6, -1
407 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, v4, v2
408 ; SI-SDAG-NEXT: v_mul_f32_e32 v2, v3, v7
409 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, v6, v5
410 ; SI-SDAG-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
411 ; SI-SDAG-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
412 ; SI-SDAG-NEXT: s_endpgm
413 ;
414 ; SI-GISEL-LABEL: s_exp2_v3f32:
415 ; SI-GISEL: ; %bb.0:
416 ; SI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xd
417 ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
418 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
419 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000
420 ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
421 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
422 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
423 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
424 ; SI-GISEL-NEXT: v_add_f32_e32 v0, s0, v0
425 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
426 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc
427 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
428 ; SI-GISEL-NEXT: s_mov_b32 s6, -1
429 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4
430 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
431 ; SI-GISEL-NEXT: v_add_f32_e32 v4, s1, v4
432 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1
433 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
434 ; SI-GISEL-NEXT: v_exp_f32_e32 v4, v4
435 ; SI-GISEL-NEXT: v_add_f32_e32 v1, s2, v1
436 ; SI-GISEL-NEXT: v_exp_f32_e32 v2, v1
437 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc
438 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1
439 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1]
440 ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
441 ; SI-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3
442 ; SI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
443 ; SI-GISEL-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
444 ; SI-GISEL-NEXT: s_endpgm
445 ;
446 ; VI-SDAG-LABEL: s_exp2_v3f32:
447 ; VI-SDAG: ; %bb.0:
448 ; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
449 ; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
450 ; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
451 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
452 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
453 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
454 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
455 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
456 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
457 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
458 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v1, vcc
459 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
460 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
461 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
462 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
463 ; VI-SDAG-NEXT: v_add_f32_e32 v4, s2, v4
464 ; VI-SDAG-NEXT: v_add_f32_e32 v1, s0, v1
465 ; VI-SDAG-NEXT: v_exp_f32_e32 v4, v4
466 ; VI-SDAG-NEXT: v_add_f32_e32 v6, s1, v6
467 ; VI-SDAG-NEXT: v_exp_f32_e32 v3, v1
468 ; VI-SDAG-NEXT: v_exp_f32_e32 v6, v6
469 ; VI-SDAG-NEXT: v_mul_f32_e32 v2, v4, v2
470 ; VI-SDAG-NEXT: v_mul_f32_e32 v0, v3, v0
471 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, s4
472 ; VI-SDAG-NEXT: v_mul_f32_e32 v1, v6, v5
473 ; VI-SDAG-NEXT: v_mov_b32_e32 v4, s5
474 ; VI-SDAG-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
475 ; VI-SDAG-NEXT: s_endpgm
476 ;
477 ; VI-GISEL-LABEL: s_exp2_v3f32:
478 ; VI-GISEL: ; %bb.0:
479 ; VI-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
480 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
481 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
482 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000
483 ; VI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
484 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
485 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
486 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
487 ; VI-GISEL-NEXT: v_add_f32_e32 v0, s0, v0
488 ; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
489 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc
490 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
491 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4
492 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
493 ; VI-GISEL-NEXT: v_add_f32_e32 v4, s1, v4
494 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1
495 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
496 ; VI-GISEL-NEXT: v_add_f32_e32 v1, s2, v1
497 ; VI-GISEL-NEXT: v_exp_f32_e32 v4, v4
498 ; VI-GISEL-NEXT: v_exp_f32_e32 v2, v1
499 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc
500 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1]
501 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1
502 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3
503 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, s4
504 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s5
505 ; VI-GISEL-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
506 ; VI-GISEL-NEXT: s_endpgm
507 ;
508 ; GFX900-SDAG-LABEL: s_exp2_v3f32:
509 ; GFX900-SDAG: ; %bb.0:
510 ; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
511 ; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
512 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
513 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
514 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
515 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
516 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
517 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
518 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
519 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
520 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v1, vcc
521 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
522 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
523 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
524 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
525 ; GFX900-SDAG-NEXT: v_add_f32_e32 v4, s2, v4
526 ; GFX900-SDAG-NEXT: v_add_f32_e32 v6, s1, v6
527 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, s0, v1
528 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v4, v4
529 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v6, v6
530 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v3, v1
531 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v7, 0
532 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, v4, v2
533 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, v6, v5
534 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v3, v0
535 ; GFX900-SDAG-NEXT: global_store_dwordx3 v7, v[0:2], s[6:7]
536 ; GFX900-SDAG-NEXT: s_endpgm
537 ;
538 ; GFX900-GISEL-LABEL: s_exp2_v3f32:
539 ; GFX900-GISEL: ; %bb.0:
540 ; GFX900-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
541 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
542 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
543 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
544 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x1f800000
545 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
546 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s0, v1
547 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v2, vcc
548 ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s0, v0
549 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
550 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 1.0, v3, vcc
551 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s1, v1
552 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v4
553 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v2, vcc
554 ; GFX900-GISEL-NEXT: v_add_f32_e32 v4, s1, v4
555 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s2, v1
556 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v2, s[0:1]
557 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s2, v1
558 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v4, v4
559 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v1
560 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v3, vcc
561 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v3, 1.0, v3, s[0:1]
562 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v4, v1
563 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, v2, v3
564 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0
565 ; GFX900-GISEL-NEXT: global_store_dwordx3 v3, v[0:2], s[6:7]
566 ; GFX900-GISEL-NEXT: s_endpgm
567 ;
568 ; R600-LABEL: s_exp2_v3f32:
569 ; R600: ; %bb.0:
570 ; R600-NEXT: ALU 29, @4, KC0[CB0:0-32], KC1[]
571 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0
572 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1
573 ; R600-NEXT: CF_END
574 ; R600-NEXT: ALU clause starting at 4:
575 ; R600-NEXT: SETGT T0.W, literal.x, KC0[3].Z,
576 ; R600-NEXT: SETGT * T1.W, literal.x, KC0[3].Y,
577 ; R600-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
578 ; R600-NEXT: CNDE * T2.W, PV.W, 0.0, literal.x,
579 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
580 ; R600-NEXT: ADD T2.W, KC0[3].Z, PV.W,
581 ; R600-NEXT: CNDE * T3.W, T1.W, 0.0, literal.x,
582 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
583 ; R600-NEXT: ADD T0.Y, KC0[3].Y, PS,
584 ; R600-NEXT: SETGT T0.Z, literal.x, KC0[3].W,
585 ; R600-NEXT: CNDE T0.W, T0.W, 1.0, literal.y,
586 ; R600-NEXT: EXP_IEEE * T0.X, PV.W,
587 ; R600-NEXT: -1023672320(-1.260000e+02), 528482304(5.421011e-20)
588 ; R600-NEXT: MUL_IEEE T1.Y, PS, PV.W,
589 ; R600-NEXT: CNDE T1.Z, PV.Z, 0.0, literal.x,
590 ; R600-NEXT: CNDE T0.W, T1.W, 1.0, literal.y,
591 ; R600-NEXT: EXP_IEEE * T0.X, PV.Y,
592 ; R600-NEXT: 1115684864(6.400000e+01), 528482304(5.421011e-20)
593 ; R600-NEXT: MUL_IEEE T1.X, PS, PV.W,
594 ; R600-NEXT: ADD T0.W, KC0[3].W, PV.Z,
595 ; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
596 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
597 ; R600-NEXT: CNDE T1.W, T0.Z, 1.0, literal.x,
598 ; R600-NEXT: EXP_IEEE * T0.Y, PV.W,
599 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
600 ; R600-NEXT: MUL_IEEE T2.X, PS, PV.W,
601 ; R600-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
602 ; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00)
603 ; R600-NEXT: LSHR * T3.X, PV.W, literal.x,
604 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
605 ;
606 ; CM-LABEL: s_exp2_v3f32:
607 ; CM: ; %bb.0:
608 ; CM-NEXT: ALU 35, @4, KC0[CB0:0-32], KC1[]
609 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X
610 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X
611 ; CM-NEXT: CF_END
612 ; CM-NEXT: ALU clause starting at 4:
613 ; CM-NEXT: SETGT * T0.W, literal.x, KC0[3].W,
614 ; CM-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
615 ; CM-NEXT: CNDE T0.Y, PV.W, 0.0, literal.x,
616 ; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].Z,
617 ; CM-NEXT: SETGT * T1.W, literal.y, KC0[3].Y,
618 ; CM-NEXT: 1115684864(6.400000e+01), -1023672320(-1.260000e+02)
619 ; CM-NEXT: CNDE T0.X, PV.W, 0.0, literal.x,
620 ; CM-NEXT: CNDE T1.Y, PV.Z, 0.0, literal.x,
621 ; CM-NEXT: CNDE T1.Z, T0.W, 1.0, literal.y,
622 ; CM-NEXT: ADD * T0.W, KC0[3].W, PV.Y,
623 ; CM-NEXT: 1115684864(6.400000e+01), 528482304(5.421011e-20)
624 ; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.W,
625 ; CM-NEXT: EXP_IEEE T0.Y, T0.W,
626 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
627 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
628 ; CM-NEXT: MUL_IEEE T1.X, PV.Y, T1.Z,
629 ; CM-NEXT: CNDE T0.Y, T0.Z, 1.0, literal.x,
630 ; CM-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.y,
631 ; CM-NEXT: ADD * T0.W, KC0[3].Z, T1.Y,
632 ; CM-NEXT: 528482304(5.421011e-20), 8(1.121039e-44)
633 ; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.W,
634 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,
635 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
636 ; CM-NEXT: EXP_IEEE * T0.W, T0.W,
637 ; CM-NEXT: LSHR T2.X, T0.Z, literal.x,
638 ; CM-NEXT: MUL_IEEE T0.Y, PV.W, T0.Y,
639 ; CM-NEXT: CNDE T0.Z, T1.W, 1.0, literal.y,
640 ; CM-NEXT: ADD * T0.W, KC0[3].Y, T0.X,
641 ; CM-NEXT: 2(2.802597e-45), 528482304(5.421011e-20)
642 ; CM-NEXT: EXP_IEEE T0.X, T0.W,
643 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T0.W,
644 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
645 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
646 ; CM-NEXT: MUL_IEEE * T0.X, PV.X, T0.Z,
647 ; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
648 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
649 %result = call <3 x float> @llvm.exp2.v3f32(<3 x float> %in)
650 store <3 x float> %result, ptr addrspace(1) %out
651 ret void
652 }
654 ; FIXME: We should be able to merge these packets together on Cayman so we
655 ; have a maximum of 4 instructions.
656 define amdgpu_kernel void @s_exp2_v4f32(ptr addrspace(1) %out, <4 x float> %in) {
657 ; SI-SDAG-LABEL: s_exp2_v4f32:
658 ; SI-SDAG: ; %bb.0:
659 ; SI-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
660 ; SI-SDAG-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0xd
661 ; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
662 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
663 ; SI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
664 ; SI-SDAG-NEXT: s_mov_b32 s3, 0xf000
665 ; SI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
666 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s7, v0
667 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
668 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
669 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s6, v0
670 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v1, vcc
671 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
672 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s5, v0
673 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v7, 1.0, v1, vcc
674 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v8, 0, v3, vcc
675 ; SI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
676 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
677 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
678 ; SI-SDAG-NEXT: v_add_f32_e32 v4, s7, v4
679 ; SI-SDAG-NEXT: v_add_f32_e32 v6, s6, v6
680 ; SI-SDAG-NEXT: v_add_f32_e32 v8, s5, v8
681 ; SI-SDAG-NEXT: v_add_f32_e32 v1, s4, v1
682 ; SI-SDAG-NEXT: v_exp_f32_e32 v4, v4
683 ; SI-SDAG-NEXT: v_exp_f32_e32 v6, v6
684 ; SI-SDAG-NEXT: v_exp_f32_e32 v8, v8
685 ; SI-SDAG-NEXT: v_exp_f32_e32 v9, v1
686 ; SI-SDAG-NEXT: s_mov_b32 s2, -1
687 ; SI-SDAG-NEXT: v_mul_f32_e32 v3, v4, v2
688 ; SI-SDAG-NEXT: v_mul_f32_e32 v2, v6, v5
689 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, v8, v7
690 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, v9, v0
691 ; SI-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
692 ; SI-SDAG-NEXT: s_endpgm
693 ;
694 ; SI-GISEL-LABEL: s_exp2_v4f32:
695 ; SI-GISEL: ; %bb.0:
696 ; SI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0xd
697 ; SI-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
698 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
699 ; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000
700 ; SI-GISEL-NEXT: v_mov_b32_e32 v4, 0x1f800000
701 ; SI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
702 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
703 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
704 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
705 ; SI-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
706 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
707 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
708 ; SI-GISEL-NEXT: v_add_f32_e32 v1, s9, v1
709 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
710 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
711 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5
712 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1]
713 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
714 ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
715 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5
716 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
717 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
718 ; SI-GISEL-NEXT: v_add_f32_e32 v5, s10, v5
719 ; SI-GISEL-NEXT: v_add_f32_e32 v2, s11, v2
720 ; SI-GISEL-NEXT: v_exp_f32_e32 v5, v5
721 ; SI-GISEL-NEXT: v_exp_f32_e32 v3, v2
722 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc
723 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1]
724 ; SI-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2
725 ; SI-GISEL-NEXT: v_mul_f32_e32 v3, v3, v4
726 ; SI-GISEL-NEXT: s_mov_b32 s6, -1
727 ; SI-GISEL-NEXT: s_mov_b32 s7, 0xf000
728 ; SI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
729 ; SI-GISEL-NEXT: s_endpgm
730 ;
731 ; VI-SDAG-LABEL: s_exp2_v4f32:
732 ; VI-SDAG: ; %bb.0:
733 ; VI-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
734 ; VI-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
735 ; VI-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
736 ; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
737 ; VI-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
738 ; VI-SDAG-NEXT: s_waitcnt lgkmcnt(0)
739 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
740 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
741 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v3, vcc
742 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
743 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v5, 1.0, v1, vcc
744 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v6, 0, v3, vcc
745 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
746 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v7, 1.0, v1, vcc
747 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v8, 0, v3, vcc
748 ; VI-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
749 ; VI-SDAG-NEXT: v_add_f32_e32 v4, s3, v4
750 ; VI-SDAG-NEXT: v_add_f32_e32 v6, s2, v6
751 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
752 ; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
753 ; VI-SDAG-NEXT: v_exp_f32_e32 v4, v4
754 ; VI-SDAG-NEXT: v_exp_f32_e32 v6, v6
755 ; VI-SDAG-NEXT: v_add_f32_e32 v8, s1, v8
756 ; VI-SDAG-NEXT: v_add_f32_e32 v1, s0, v1
757 ; VI-SDAG-NEXT: v_exp_f32_e32 v8, v8
758 ; VI-SDAG-NEXT: v_exp_f32_e32 v9, v1
759 ; VI-SDAG-NEXT: v_mul_f32_e32 v3, v4, v2
760 ; VI-SDAG-NEXT: v_mul_f32_e32 v2, v6, v5
761 ; VI-SDAG-NEXT: v_mov_b32_e32 v4, s4
762 ; VI-SDAG-NEXT: v_mul_f32_e32 v1, v8, v7
763 ; VI-SDAG-NEXT: v_mul_f32_e32 v0, v9, v0
764 ; VI-SDAG-NEXT: v_mov_b32_e32 v5, s5
765 ; VI-SDAG-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
766 ; VI-SDAG-NEXT: s_endpgm
767 ;
768 ; VI-GISEL-LABEL: s_exp2_v4f32:
769 ; VI-GISEL: ; %bb.0:
770 ; VI-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
771 ; VI-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
772 ; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
773 ; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000
774 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, 0x1f800000
775 ; VI-GISEL-NEXT: s_waitcnt lgkmcnt(0)
776 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
777 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
778 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
779 ; VI-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
780 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
781 ; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
782 ; VI-GISEL-NEXT: v_add_f32_e32 v1, s9, v1
783 ; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
784 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
785 ; VI-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5
786 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1]
787 ; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
788 ; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
789 ; VI-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5
790 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
791 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
792 ; VI-GISEL-NEXT: v_add_f32_e32 v5, s10, v5
793 ; VI-GISEL-NEXT: v_add_f32_e32 v2, s11, v2
794 ; VI-GISEL-NEXT: v_exp_f32_e32 v5, v5
795 ; VI-GISEL-NEXT: v_exp_f32_e32 v3, v2
796 ; VI-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc
797 ; VI-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1]
798 ; VI-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2
799 ; VI-GISEL-NEXT: v_mul_f32_e32 v3, v3, v4
800 ; VI-GISEL-NEXT: v_mov_b32_e32 v5, s3
801 ; VI-GISEL-NEXT: v_mov_b32_e32 v4, s2
802 ; VI-GISEL-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
803 ; VI-GISEL-NEXT: s_endpgm
804 ;
805 ; GFX900-SDAG-LABEL: s_exp2_v4f32:
806 ; GFX900-SDAG: ; %bb.0:
807 ; GFX900-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x34
808 ; GFX900-SDAG-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
809 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
810 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
811 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v3, 0x42800000
812 ; GFX900-SDAG-NEXT: s_waitcnt lgkmcnt(0)
813 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s3, v0
814 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
815 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
816 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s2, v0
817 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v6, 1.0, v1, vcc
818 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v7, 0, v3, vcc
819 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s1, v0
820 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v8, 1.0, v1, vcc
821 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v9, 0, v3, vcc
822 ; GFX900-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s0, v0
823 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
824 ; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
825 ; GFX900-SDAG-NEXT: v_add_f32_e32 v5, s3, v5
826 ; GFX900-SDAG-NEXT: v_add_f32_e32 v7, s2, v7
827 ; GFX900-SDAG-NEXT: v_add_f32_e32 v9, s1, v9
828 ; GFX900-SDAG-NEXT: v_add_f32_e32 v1, s0, v1
829 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v5, v5
830 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v7, v7
831 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v9, v9
832 ; GFX900-SDAG-NEXT: v_exp_f32_e32 v10, v1
833 ; GFX900-SDAG-NEXT: v_mov_b32_e32 v4, 0
834 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v3, v5, v2
835 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v2, v7, v6
836 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, v9, v8
837 ; GFX900-SDAG-NEXT: v_mul_f32_e32 v0, v10, v0
838 ; GFX900-SDAG-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
839 ; GFX900-SDAG-NEXT: s_endpgm
840 ;
841 ; GFX900-GISEL-LABEL: s_exp2_v4f32:
842 ; GFX900-GISEL: ; %bb.0:
843 ; GFX900-GISEL-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x34
844 ; GFX900-GISEL-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24
845 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2fc0000
846 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x42800000
847 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0x1f800000
848 ; GFX900-GISEL-NEXT: s_waitcnt lgkmcnt(0)
849 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s8, v2
850 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v3, vcc
851 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s9, v2
852 ; GFX900-GISEL-NEXT: v_add_f32_e32 v0, s8, v0
853 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, v3, s[0:1]
854 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
855 ; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s9, v1
856 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
857 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
858 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v0, v0, v5
859 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v5, 1.0, v4, s[0:1]
860 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s10, v2
861 ; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[0:1], s11, v2
862 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, v1, v5
863 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v5, 0, v3, vcc
864 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, v3, s[0:1]
865 ; GFX900-GISEL-NEXT: v_add_f32_e32 v5, s10, v5
866 ; GFX900-GISEL-NEXT: v_add_f32_e32 v2, s11, v2
867 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v5, v5
868 ; GFX900-GISEL-NEXT: v_exp_f32_e32 v3, v2
869 ; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v2, 1.0, v4, vcc
870 ; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v4, 1.0, v4, s[0:1]
871 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v2, v5, v2
872 ; GFX900-GISEL-NEXT: v_mul_f32_e32 v3, v3, v4
873 ; GFX900-GISEL-NEXT: v_mov_b32_e32 v4, 0
874 ; GFX900-GISEL-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]
875 ; GFX900-GISEL-NEXT: s_endpgm
876 ;
877 ; R600-LABEL: s_exp2_v4f32:
878 ; R600: ; %bb.0:
879 ; R600-NEXT: ALU 33, @4, KC0[CB0:0-32], KC1[]
880 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
881 ; R600-NEXT: CF_END
882 ; R600-NEXT: PAD
883 ; R600-NEXT: ALU clause starting at 4:
884 ; R600-NEXT: SETGT T0.W, literal.x, KC0[4].X,
885 ; R600-NEXT: SETGT * T1.W, literal.x, KC0[3].W,
886 ; R600-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
887 ; R600-NEXT: CNDE * T2.W, PV.W, 0.0, literal.x,
888 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
889 ; R600-NEXT: ADD T0.Z, KC0[4].X, PV.W,
890 ; R600-NEXT: SETGT T2.W, literal.x, KC0[3].Z,
891 ; R600-NEXT: CNDE * T3.W, T1.W, 0.0, literal.y,
892 ; R600-NEXT: -1023672320(-1.260000e+02), 1115684864(6.400000e+01)
893 ; R600-NEXT: ADD T0.X, KC0[3].W, PS,
894 ; R600-NEXT: CNDE T0.Y, T0.W, 1.0, literal.x,
895 ; R600-NEXT: SETGT T1.Z, literal.y, KC0[3].Y,
896 ; R600-NEXT: CNDE T0.W, PV.W, 0.0, literal.z,
897 ; R600-NEXT: EXP_IEEE * T0.Z, PV.Z,
898 ; R600-NEXT: 528482304(5.421011e-20), -1023672320(-1.260000e+02)
899 ; R600-NEXT: 1115684864(6.400000e+01), 0(0.000000e+00)
900 ; R600-NEXT: ADD T1.X, KC0[3].Z, PV.W,
901 ; R600-NEXT: CNDE T1.Y, T1.W, 1.0, literal.x,
902 ; R600-NEXT: CNDE T2.Z, PV.Z, 0.0, literal.y,
903 ; R600-NEXT: MUL_IEEE T0.W, PS, PV.Y,
904 ; R600-NEXT: EXP_IEEE * T0.X, PV.X,
905 ; R600-NEXT: 528482304(5.421011e-20), 1115684864(6.400000e+01)
906 ; R600-NEXT: ADD T2.Y, KC0[3].Y, PV.Z,
907 ; R600-NEXT: MUL_IEEE T0.Z, PS, PV.Y,
908 ; R600-NEXT: CNDE T1.W, T2.W, 1.0, literal.x,
909 ; R600-NEXT: EXP_IEEE * T0.X, PV.X,
910 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
911 ; R600-NEXT: MUL_IEEE T0.Y, PS, PV.W,
912 ; R600-NEXT: CNDE T1.W, T1.Z, 1.0, literal.x,
913 ; R600-NEXT: EXP_IEEE * T0.X, PV.Y,
914 ; R600-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
915 ; R600-NEXT: MUL_IEEE T0.X, PS, PV.W,
916 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
917 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
918 ;
919 ; CM-LABEL: s_exp2_v4f32:
920 ; CM: ; %bb.0:
921 ; CM-NEXT: ALU 43, @4, KC0[CB0:0-32], KC1[]
922 ; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X
923 ; CM-NEXT: CF_END
924 ; CM-NEXT: PAD
925 ; CM-NEXT: ALU clause starting at 4:
926 ; CM-NEXT: SETGT * T0.W, literal.x, KC0[4].X,
927 ; CM-NEXT: -1023672320(-1.260000e+02), 0(0.000000e+00)
928 ; CM-NEXT: CNDE T0.Y, PV.W, 0.0, literal.x,
929 ; CM-NEXT: SETGT T0.Z, literal.y, KC0[3].W,
930 ; CM-NEXT: SETGT * T1.W, literal.y, KC0[3].Z,
931 ; CM-NEXT: 1115684864(6.400000e+01), -1023672320(-1.260000e+02)
932 ; CM-NEXT: CNDE T0.X, PV.W, 0.0, literal.x,
933 ; CM-NEXT: CNDE T1.Y, T0.W, 1.0, literal.y,
934 ; CM-NEXT: CNDE T1.Z, PV.Z, 0.0, literal.x,
935 ; CM-NEXT: ADD * T0.W, KC0[4].X, PV.Y,
936 ; CM-NEXT: 1115684864(6.400000e+01), 528482304(5.421011e-20)
937 ; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.W,
938 ; CM-NEXT: EXP_IEEE T0.Y, T0.W,
939 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.W,
940 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.W,
941 ; CM-NEXT: CNDE T1.X, T0.Z, 1.0, literal.x,
942 ; CM-NEXT: SETGT T2.Y, literal.y, KC0[3].Y,
943 ; CM-NEXT: ADD T0.Z, KC0[3].W, T1.Z,
944 ; CM-NEXT: MUL_IEEE * T0.W, PV.Y, T1.Y,
945 ; CM-NEXT: 528482304(5.421011e-20), -1023672320(-1.260000e+02)
946 ; CM-NEXT: EXP_IEEE T0.X (MASKED), T0.Z,
947 ; CM-NEXT: EXP_IEEE T0.Y, T0.Z,
948 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T0.Z,
949 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T0.Z,
950 ; CM-NEXT: CNDE T2.X, T2.Y, 0.0, literal.x,
951 ; CM-NEXT: CNDE T1.Y, T1.W, 1.0, literal.y,
952 ; CM-NEXT: MUL_IEEE T0.Z, PV.Y, T1.X,
953 ; CM-NEXT: ADD * T1.W, KC0[3].Z, T0.X, BS:VEC_021/SCL_122
954 ; CM-NEXT: 1115684864(6.400000e+01), 528482304(5.421011e-20)
955 ; CM-NEXT: EXP_IEEE T0.X, T1.W,
956 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T1.W,
957 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W,
958 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W,
959 ; CM-NEXT: MUL_IEEE T0.Y, PV.X, T1.Y,
960 ; CM-NEXT: CNDE T1.Z, T2.Y, 1.0, literal.x,
961 ; CM-NEXT: ADD * T1.W, KC0[3].Y, T2.X,
962 ; CM-NEXT: 528482304(5.421011e-20), 0(0.000000e+00)
963 ; CM-NEXT: EXP_IEEE T0.X, T1.W,
964 ; CM-NEXT: EXP_IEEE T0.Y (MASKED), T1.W,
965 ; CM-NEXT: EXP_IEEE T0.Z (MASKED), T1.W,
966 ; CM-NEXT: EXP_IEEE * T0.W (MASKED), T1.W,
967 ; CM-NEXT: MUL_IEEE * T0.X, PV.X, T1.Z,
968 ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
969 ; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)
970 %result = call <4 x float> @llvm.exp2.v4f32(<4 x float> %in)
971 store <4 x float> %result, ptr addrspace(1) %out
972 ret void
973 }
975 define float @v_exp2_f32(float %in) {
976 ; GCN-SDAG-LABEL: v_exp2_f32:
977 ; GCN-SDAG: ; %bb.0:
978 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
979 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
980 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
981 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
982 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
983 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
984 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
985 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
986 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
987 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
988 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
989 ;
990 ; GCN-GISEL-LABEL: v_exp2_f32:
991 ; GCN-GISEL: ; %bb.0:
992 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
993 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
994 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
995 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
996 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
997 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
998 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
999 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1000 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1001 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1002 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1003 ;
1004 ; R600-LABEL: v_exp2_f32:
1005 ; R600: ; %bb.0:
1006 ; R600-NEXT: CF_END
1007 ; R600-NEXT: PAD
1008 ;
1009 ; CM-LABEL: v_exp2_f32:
1010 ; CM: ; %bb.0:
1011 ; CM-NEXT: CF_END
1012 ; CM-NEXT: PAD
1013 %result = call float @llvm.exp2.f32(float %in)
1014 ret float %result
1015 }
1017 define float @v_exp2_fabs_f32(float %in) {
1018 ; GCN-SDAG-LABEL: v_exp2_fabs_f32:
1019 ; GCN-SDAG: ; %bb.0:
1020 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1021 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1022 ; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
1023 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1024 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1025 ; GCN-SDAG-NEXT: v_add_f32_e64 v0, |v0|, v2
1026 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1027 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1028 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1029 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1030 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1031 ;
1032 ; GCN-GISEL-LABEL: v_exp2_fabs_f32:
1033 ; GCN-GISEL: ; %bb.0:
1034 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1035 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1036 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1037 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
1038 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1039 ; GCN-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1
1040 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1041 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1042 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1043 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1044 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1045 ;
1046 ; R600-LABEL: v_exp2_fabs_f32:
1047 ; R600: ; %bb.0:
1048 ; R600-NEXT: CF_END
1049 ; R600-NEXT: PAD
1050 ;
1051 ; CM-LABEL: v_exp2_fabs_f32:
1052 ; CM: ; %bb.0:
1053 ; CM-NEXT: CF_END
1054 ; CM-NEXT: PAD
1055 %fabs = call float @llvm.fabs.f32(float %in)
1056 %result = call float @llvm.exp2.f32(float %fabs)
1057 ret float %result
1058 }
1060 define float @v_exp2_fneg_fabs_f32(float %in) {
1061 ; GCN-SDAG-LABEL: v_exp2_fneg_fabs_f32:
1062 ; GCN-SDAG: ; %bb.0:
1063 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1064 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0x42fc0000
1065 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
1066 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1067 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1068 ; GCN-SDAG-NEXT: v_sub_f32_e64 v0, v2, |v0|
1069 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1070 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1071 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1072 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1073 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1074 ;
1075 ; GCN-GISEL-LABEL: v_exp2_fneg_fabs_f32:
1076 ; GCN-GISEL: ; %bb.0:
1077 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1078 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1079 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1080 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -|v0|, v1
1081 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1082 ; GCN-GISEL-NEXT: v_sub_f32_e64 v0, v1, |v0|
1083 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1084 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1085 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1086 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1087 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1088 ;
1089 ; R600-LABEL: v_exp2_fneg_fabs_f32:
1090 ; R600: ; %bb.0:
1091 ; R600-NEXT: CF_END
1092 ; R600-NEXT: PAD
1093 ;
1094 ; CM-LABEL: v_exp2_fneg_fabs_f32:
1095 ; CM: ; %bb.0:
1096 ; CM-NEXT: CF_END
1097 ; CM-NEXT: PAD
1098 %fabs = call float @llvm.fabs.f32(float %in)
1099 %fneg.fabs = fneg float %fabs
1100 %result = call float @llvm.exp2.f32(float %fneg.fabs)
1101 ret float %result
1102 }
1104 define float @v_exp2_fneg_f32(float %in) {
1105 ; GCN-SDAG-LABEL: v_exp2_fneg_f32:
1106 ; GCN-SDAG: ; %bb.0:
1107 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1108 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0x42fc0000
1109 ; GCN-SDAG-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
1110 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1111 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1112 ; GCN-SDAG-NEXT: v_sub_f32_e32 v0, v2, v0
1113 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1114 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1115 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1116 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1117 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1118 ;
1119 ; GCN-GISEL-LABEL: v_exp2_fneg_f32:
1120 ; GCN-GISEL: ; %bb.0:
1121 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1122 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1123 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1124 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, -v0, v1
1125 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1126 ; GCN-GISEL-NEXT: v_sub_f32_e32 v0, v1, v0
1127 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1128 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1129 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1130 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1131 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1132 ;
1133 ; R600-LABEL: v_exp2_fneg_f32:
1134 ; R600: ; %bb.0:
1135 ; R600-NEXT: CF_END
1136 ; R600-NEXT: PAD
1137 ;
1138 ; CM-LABEL: v_exp2_fneg_f32:
1139 ; CM: ; %bb.0:
1140 ; CM-NEXT: CF_END
1141 ; CM-NEXT: PAD
1142 %fneg = fneg float %in
1143 %result = call float @llvm.exp2.f32(float %fneg)
1144 ret float %result
1145 }
1147 define float @v_exp2_f32_fast(float %in) {
1148 ; GCN-SDAG-LABEL: v_exp2_f32_fast:
1149 ; GCN-SDAG: ; %bb.0:
1150 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1151 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1152 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1153 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1154 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1155 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1156 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1157 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1158 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1159 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1160 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1161 ;
1162 ; GCN-GISEL-LABEL: v_exp2_f32_fast:
1163 ; GCN-GISEL: ; %bb.0:
1164 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1165 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1166 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1167 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1168 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1169 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1170 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1171 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1172 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1173 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1174 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1175 ;
1176 ; R600-LABEL: v_exp2_f32_fast:
1177 ; R600: ; %bb.0:
1178 ; R600-NEXT: CF_END
1179 ; R600-NEXT: PAD
1180 ;
1181 ; CM-LABEL: v_exp2_f32_fast:
1182 ; CM: ; %bb.0:
1183 ; CM-NEXT: CF_END
1184 ; CM-NEXT: PAD
1185 %result = call fast float @llvm.exp2.f32(float %in)
1186 ret float %result
1187 }
1189 define float @v_exp2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
1190 ; GCN-SDAG-LABEL: v_exp2_f32_unsafe_math_attr:
1191 ; GCN-SDAG: ; %bb.0:
1192 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1193 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1194 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1195 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1196 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1197 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1198 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1199 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1200 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1201 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1202 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1203 ;
1204 ; GCN-GISEL-LABEL: v_exp2_f32_unsafe_math_attr:
1205 ; GCN-GISEL: ; %bb.0:
1206 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1207 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1208 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1209 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1210 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1211 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1212 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1213 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1214 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1215 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1216 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1217 ;
1218 ; R600-LABEL: v_exp2_f32_unsafe_math_attr:
1219 ; R600: ; %bb.0:
1220 ; R600-NEXT: CF_END
1221 ; R600-NEXT: PAD
1222 ;
1223 ; CM-LABEL: v_exp2_f32_unsafe_math_attr:
1224 ; CM: ; %bb.0:
1225 ; CM-NEXT: CF_END
1226 ; CM-NEXT: PAD
1227 %result = call float @llvm.exp2.f32(float %in)
1228 ret float %result
1229 }
1231 define float @v_exp2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
1232 ; GCN-SDAG-LABEL: v_exp2_f32_approx_fn_attr:
1233 ; GCN-SDAG: ; %bb.0:
1234 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1235 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1236 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1237 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1238 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1239 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1240 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1241 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1242 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1243 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1244 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1245 ;
1246 ; GCN-GISEL-LABEL: v_exp2_f32_approx_fn_attr:
1247 ; GCN-GISEL: ; %bb.0:
1248 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1249 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1250 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1251 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1252 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1253 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1254 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1255 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1256 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1257 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1258 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1259 ;
1260 ; R600-LABEL: v_exp2_f32_approx_fn_attr:
1261 ; R600: ; %bb.0:
1262 ; R600-NEXT: CF_END
1263 ; R600-NEXT: PAD
1264 ;
1265 ; CM-LABEL: v_exp2_f32_approx_fn_attr:
1266 ; CM: ; %bb.0:
1267 ; CM-NEXT: CF_END
1268 ; CM-NEXT: PAD
1269 %result = call float @llvm.exp2.f32(float %in)
1270 ret float %result
1271 }
1273 define float @v_exp2_f32_ninf(float %in) {
1274 ; GCN-SDAG-LABEL: v_exp2_f32_ninf:
1275 ; GCN-SDAG: ; %bb.0:
1276 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1277 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1278 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1279 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1280 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1281 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1282 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1283 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1284 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1285 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1286 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1287 ;
1288 ; GCN-GISEL-LABEL: v_exp2_f32_ninf:
1289 ; GCN-GISEL: ; %bb.0:
1290 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1291 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1292 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1293 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1294 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1295 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1296 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1297 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1298 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1299 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1300 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1301 ;
1302 ; R600-LABEL: v_exp2_f32_ninf:
1303 ; R600: ; %bb.0:
1304 ; R600-NEXT: CF_END
1305 ; R600-NEXT: PAD
1306 ;
1307 ; CM-LABEL: v_exp2_f32_ninf:
1308 ; CM: ; %bb.0:
1309 ; CM-NEXT: CF_END
1310 ; CM-NEXT: PAD
1311 %result = call ninf float @llvm.exp2.f32(float %in)
1312 ret float %result
1313 }
1315 define float @v_exp2_f32_afn(float %in) {
1316 ; GCN-SDAG-LABEL: v_exp2_f32_afn:
1317 ; GCN-SDAG: ; %bb.0:
1318 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1319 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1320 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1321 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1322 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1323 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1324 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1325 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1326 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1327 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1328 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1329 ;
1330 ; GCN-GISEL-LABEL: v_exp2_f32_afn:
1331 ; GCN-GISEL: ; %bb.0:
1332 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1333 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1334 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1335 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1336 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1337 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1338 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1339 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1340 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1341 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1342 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1343 ;
1344 ; R600-LABEL: v_exp2_f32_afn:
1345 ; R600: ; %bb.0:
1346 ; R600-NEXT: CF_END
1347 ; R600-NEXT: PAD
1348 ;
1349 ; CM-LABEL: v_exp2_f32_afn:
1350 ; CM: ; %bb.0:
1351 ; CM-NEXT: CF_END
1352 ; CM-NEXT: PAD
1353 %result = call afn float @llvm.exp2.f32(float %in)
1354 ret float %result
1355 }
1357 define float @v_exp2_f32_afn_daz(float %in) #0 {
1358 ; GCN-LABEL: v_exp2_f32_afn_daz:
1359 ; GCN: ; %bb.0:
1360 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1361 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1362 ; GCN-NEXT: s_setpc_b64 s[30:31]
1363 ;
1364 ; R600-LABEL: v_exp2_f32_afn_daz:
1365 ; R600: ; %bb.0:
1366 ; R600-NEXT: CF_END
1367 ; R600-NEXT: PAD
1368 ;
1369 ; CM-LABEL: v_exp2_f32_afn_daz:
1370 ; CM: ; %bb.0:
1371 ; CM-NEXT: CF_END
1372 ; CM-NEXT: PAD
1373 %result = call afn float @llvm.exp2.f32(float %in)
1374 ret float %result
1375 }
1377 define float @v_exp2_f32_afn_dynamic(float %in) #1 {
1378 ; GCN-SDAG-LABEL: v_exp2_f32_afn_dynamic:
1379 ; GCN-SDAG: ; %bb.0:
1380 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1381 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1382 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1383 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1384 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1385 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1386 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1387 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1388 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1389 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1390 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1391 ;
1392 ; GCN-GISEL-LABEL: v_exp2_f32_afn_dynamic:
1393 ; GCN-GISEL: ; %bb.0:
1394 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1395 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1396 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1397 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1398 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1399 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1400 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1401 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1402 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1403 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1404 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1405 ;
1406 ; R600-LABEL: v_exp2_f32_afn_dynamic:
1407 ; R600: ; %bb.0:
1408 ; R600-NEXT: CF_END
1409 ; R600-NEXT: PAD
1410 ;
1411 ; CM-LABEL: v_exp2_f32_afn_dynamic:
1412 ; CM: ; %bb.0:
1413 ; CM-NEXT: CF_END
1414 ; CM-NEXT: PAD
1415 %result = call afn float @llvm.exp2.f32(float %in)
1416 ret float %result
1417 }
1419 define float @v_fabs_exp2_f32_afn(float %in) {
1420 ; GCN-SDAG-LABEL: v_fabs_exp2_f32_afn:
1421 ; GCN-SDAG: ; %bb.0:
1422 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1423 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1424 ; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
1425 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1426 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1427 ; GCN-SDAG-NEXT: v_add_f32_e64 v0, |v0|, v2
1428 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1429 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1430 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1431 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1432 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1433 ;
1434 ; GCN-GISEL-LABEL: v_fabs_exp2_f32_afn:
1435 ; GCN-GISEL: ; %bb.0:
1436 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1437 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1438 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1439 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
1440 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1441 ; GCN-GISEL-NEXT: v_add_f32_e64 v0, |v0|, v1
1442 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1443 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1444 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1445 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1446 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1447 ;
1448 ; R600-LABEL: v_fabs_exp2_f32_afn:
1449 ; R600: ; %bb.0:
1450 ; R600-NEXT: CF_END
1451 ; R600-NEXT: PAD
1452 ;
1453 ; CM-LABEL: v_fabs_exp2_f32_afn:
1454 ; CM: ; %bb.0:
1455 ; CM-NEXT: CF_END
1456 ; CM-NEXT: PAD
1457 %fabs = call float @llvm.fabs.f32(float %in)
1458 %result = call afn float @llvm.exp2.f32(float %fabs)
1459 ret float %result
1460 }
1462 define float @v_exp2_f32_daz(float %in) #0 {
1463 ; GCN-LABEL: v_exp2_f32_daz:
1464 ; GCN: ; %bb.0:
1465 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1466 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1467 ; GCN-NEXT: s_setpc_b64 s[30:31]
1468 ;
1469 ; R600-LABEL: v_exp2_f32_daz:
1470 ; R600: ; %bb.0:
1471 ; R600-NEXT: CF_END
1472 ; R600-NEXT: PAD
1473 ;
1474 ; CM-LABEL: v_exp2_f32_daz:
1475 ; CM: ; %bb.0:
1476 ; CM-NEXT: CF_END
1477 ; CM-NEXT: PAD
1478 %result = call float @llvm.exp2.f32(float %in)
1479 ret float %result
1480 }
1482 define float @v_exp2_f32_nnan(float %in) {
1483 ; GCN-SDAG-LABEL: v_exp2_f32_nnan:
1484 ; GCN-SDAG: ; %bb.0:
1485 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1486 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1487 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1488 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1489 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1490 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1491 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1492 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1493 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1494 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1495 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1496 ;
1497 ; GCN-GISEL-LABEL: v_exp2_f32_nnan:
1498 ; GCN-GISEL: ; %bb.0:
1499 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1500 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1501 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1502 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1503 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1504 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1505 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1506 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1507 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1508 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1509 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1510 ;
1511 ; R600-LABEL: v_exp2_f32_nnan:
1512 ; R600: ; %bb.0:
1513 ; R600-NEXT: CF_END
1514 ; R600-NEXT: PAD
1515 ;
1516 ; CM-LABEL: v_exp2_f32_nnan:
1517 ; CM: ; %bb.0:
1518 ; CM-NEXT: CF_END
1519 ; CM-NEXT: PAD
1520 %result = call nnan float @llvm.exp2.f32(float %in)
1521 ret float %result
1522 }
1524 define float @v_exp2_f32_nnan_daz(float %in) #0 {
1525 ; GCN-LABEL: v_exp2_f32_nnan_daz:
1526 ; GCN: ; %bb.0:
1527 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1528 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1529 ; GCN-NEXT: s_setpc_b64 s[30:31]
1530 ;
1531 ; R600-LABEL: v_exp2_f32_nnan_daz:
1532 ; R600: ; %bb.0:
1533 ; R600-NEXT: CF_END
1534 ; R600-NEXT: PAD
1535 ;
1536 ; CM-LABEL: v_exp2_f32_nnan_daz:
1537 ; CM: ; %bb.0:
1538 ; CM-NEXT: CF_END
1539 ; CM-NEXT: PAD
1540 %result = call nnan float @llvm.exp2.f32(float %in)
1541 ret float %result
1542 }
1544 define float @v_exp2_f32_nnan_dynamic(float %in) #1 {
1545 ; GCN-SDAG-LABEL: v_exp2_f32_nnan_dynamic:
1546 ; GCN-SDAG: ; %bb.0:
1547 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1548 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1549 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1550 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1551 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1552 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1553 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1554 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1555 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1556 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1557 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1558 ;
1559 ; GCN-GISEL-LABEL: v_exp2_f32_nnan_dynamic:
1560 ; GCN-GISEL: ; %bb.0:
1561 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1562 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1563 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1564 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1565 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1566 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1567 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1568 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1569 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1570 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1571 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1572 ;
1573 ; R600-LABEL: v_exp2_f32_nnan_dynamic:
1574 ; R600: ; %bb.0:
1575 ; R600-NEXT: CF_END
1576 ; R600-NEXT: PAD
1577 ;
1578 ; CM-LABEL: v_exp2_f32_nnan_dynamic:
1579 ; CM: ; %bb.0:
1580 ; CM-NEXT: CF_END
1581 ; CM-NEXT: PAD
1582 %result = call nnan float @llvm.exp2.f32(float %in)
1583 ret float %result
1584 }
1586 define float @v_exp2_f32_ninf_daz(float %in) #0 {
1587 ; GCN-LABEL: v_exp2_f32_ninf_daz:
1588 ; GCN: ; %bb.0:
1589 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1590 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1591 ; GCN-NEXT: s_setpc_b64 s[30:31]
1592 ;
1593 ; R600-LABEL: v_exp2_f32_ninf_daz:
1594 ; R600: ; %bb.0:
1595 ; R600-NEXT: CF_END
1596 ; R600-NEXT: PAD
1597 ;
1598 ; CM-LABEL: v_exp2_f32_ninf_daz:
1599 ; CM: ; %bb.0:
1600 ; CM-NEXT: CF_END
1601 ; CM-NEXT: PAD
1602 %result = call ninf float @llvm.exp2.f32(float %in)
1603 ret float %result
1604 }
1606 define float @v_exp2_f32_ninf_dynamic(float %in) #1 {
1607 ; GCN-SDAG-LABEL: v_exp2_f32_ninf_dynamic:
1608 ; GCN-SDAG: ; %bb.0:
1609 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1610 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1611 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1612 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1613 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1614 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1615 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1616 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1617 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1618 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1619 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1620 ;
1621 ; GCN-GISEL-LABEL: v_exp2_f32_ninf_dynamic:
1622 ; GCN-GISEL: ; %bb.0:
1623 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1624 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1625 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1626 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1627 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1628 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1629 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1630 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1631 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1632 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1633 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1634 ;
1635 ; R600-LABEL: v_exp2_f32_ninf_dynamic:
1636 ; R600: ; %bb.0:
1637 ; R600-NEXT: CF_END
1638 ; R600-NEXT: PAD
1639 ;
1640 ; CM-LABEL: v_exp2_f32_ninf_dynamic:
1641 ; CM: ; %bb.0:
1642 ; CM-NEXT: CF_END
1643 ; CM-NEXT: PAD
1644 %result = call ninf float @llvm.exp2.f32(float %in)
1645 ret float %result
1646 }
1648 define float @v_exp2_f32_nnan_ninf(float %in) {
1649 ; GCN-SDAG-LABEL: v_exp2_f32_nnan_ninf:
1650 ; GCN-SDAG: ; %bb.0:
1651 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1652 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1653 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1654 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1655 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1656 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1657 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1658 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1659 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1660 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1661 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1662 ;
1663 ; GCN-GISEL-LABEL: v_exp2_f32_nnan_ninf:
1664 ; GCN-GISEL: ; %bb.0:
1665 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1666 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1667 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1668 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1669 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1670 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1671 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1672 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1673 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1674 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1675 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1676 ;
1677 ; R600-LABEL: v_exp2_f32_nnan_ninf:
1678 ; R600: ; %bb.0:
1679 ; R600-NEXT: CF_END
1680 ; R600-NEXT: PAD
1681 ;
1682 ; CM-LABEL: v_exp2_f32_nnan_ninf:
1683 ; CM: ; %bb.0:
1684 ; CM-NEXT: CF_END
1685 ; CM-NEXT: PAD
1686 %result = call nnan ninf float @llvm.exp2.f32(float %in)
1687 ret float %result
1688 }
1690 define float @v_exp2_f32_nnan_ninf_daz(float %in) #0 {
1691 ; GCN-LABEL: v_exp2_f32_nnan_ninf_daz:
1692 ; GCN: ; %bb.0:
1693 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1694 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1695 ; GCN-NEXT: s_setpc_b64 s[30:31]
1696 ;
1697 ; R600-LABEL: v_exp2_f32_nnan_ninf_daz:
1698 ; R600: ; %bb.0:
1699 ; R600-NEXT: CF_END
1700 ; R600-NEXT: PAD
1701 ;
1702 ; CM-LABEL: v_exp2_f32_nnan_ninf_daz:
1703 ; CM: ; %bb.0:
1704 ; CM-NEXT: CF_END
1705 ; CM-NEXT: PAD
1706 %result = call nnan ninf float @llvm.exp2.f32(float %in)
1707 ret float %result
1708 }
1710 define float @v_exp2_f32_nnan_ninf_dynamic(float %in) #1 {
1711 ; GCN-SDAG-LABEL: v_exp2_f32_nnan_ninf_dynamic:
1712 ; GCN-SDAG: ; %bb.0:
1713 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1714 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1715 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1716 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1717 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1718 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1719 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1720 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1721 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1722 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1723 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1724 ;
1725 ; GCN-GISEL-LABEL: v_exp2_f32_nnan_ninf_dynamic:
1726 ; GCN-GISEL: ; %bb.0:
1727 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1728 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1729 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1730 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1731 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1732 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1733 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1734 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1735 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1736 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1737 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1738 ;
1739 ; R600-LABEL: v_exp2_f32_nnan_ninf_dynamic:
1740 ; R600: ; %bb.0:
1741 ; R600-NEXT: CF_END
1742 ; R600-NEXT: PAD
1743 ;
1744 ; CM-LABEL: v_exp2_f32_nnan_ninf_dynamic:
1745 ; CM: ; %bb.0:
1746 ; CM-NEXT: CF_END
1747 ; CM-NEXT: PAD
1748 %result = call nnan ninf float @llvm.exp2.f32(float %in)
1749 ret float %result
1750 }
1752 define float @v_exp2_f32_fast_daz(float %in) #0 {
1753 ; GCN-LABEL: v_exp2_f32_fast_daz:
1754 ; GCN: ; %bb.0:
1755 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1756 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1757 ; GCN-NEXT: s_setpc_b64 s[30:31]
1758 ;
1759 ; R600-LABEL: v_exp2_f32_fast_daz:
1760 ; R600: ; %bb.0:
1761 ; R600-NEXT: CF_END
1762 ; R600-NEXT: PAD
1763 ;
1764 ; CM-LABEL: v_exp2_f32_fast_daz:
1765 ; CM: ; %bb.0:
1766 ; CM-NEXT: CF_END
1767 ; CM-NEXT: PAD
1768 %result = call fast float @llvm.exp2.f32(float %in)
1769 ret float %result
1770 }
1772 define float @v_exp2_f32_dynamic_mode(float %in) #1 {
1773 ; GCN-SDAG-LABEL: v_exp2_f32_dynamic_mode:
1774 ; GCN-SDAG: ; %bb.0:
1775 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1776 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1777 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1778 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
1779 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1780 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
1781 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
1782 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1783 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1784 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1785 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1786 ;
1787 ; GCN-GISEL-LABEL: v_exp2_f32_dynamic_mode:
1788 ; GCN-GISEL: ; %bb.0:
1789 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1790 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
1791 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
1792 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
1793 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
1794 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1795 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1796 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1797 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1798 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1799 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1800 ;
1801 ; R600-LABEL: v_exp2_f32_dynamic_mode:
1802 ; R600: ; %bb.0:
1803 ; R600-NEXT: CF_END
1804 ; R600-NEXT: PAD
1805 ;
1806 ; CM-LABEL: v_exp2_f32_dynamic_mode:
1807 ; CM: ; %bb.0:
1808 ; CM-NEXT: CF_END
1809 ; CM-NEXT: PAD
1810 %result = call float @llvm.exp2.f32(float %in)
1811 ret float %result
1812 }
1814 define float @v_exp2_f32_undef() {
1815 ; GCN-SDAG-LABEL: v_exp2_f32_undef:
1816 ; GCN-SDAG: ; %bb.0:
1817 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1818 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, 0x7fc00000
1819 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
1820 ;
1821 ; GCN-GISEL-LABEL: v_exp2_f32_undef:
1822 ; GCN-GISEL: ; %bb.0:
1823 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1824 ; GCN-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
1825 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
1826 ; GCN-GISEL-NEXT: v_add_f32_e32 v1, s4, v1
1827 ; GCN-GISEL-NEXT: v_add_f32_e64 v2, s4, 0
1828 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
1829 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
1830 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
1831 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
1832 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1833 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
1834 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
1835 ;
1836 ; R600-LABEL: v_exp2_f32_undef:
1837 ; R600: ; %bb.0:
1838 ; R600-NEXT: CF_END
1839 ; R600-NEXT: PAD
1840 ;
1841 ; CM-LABEL: v_exp2_f32_undef:
1842 ; CM: ; %bb.0:
1843 ; CM-NEXT: CF_END
1844 ; CM-NEXT: PAD
1845 %result = call float @llvm.exp2.f32(float undef)
1846 ret float %result
1847 }
1849 define float @v_exp2_f32_0() {
1850 ; GCN-LABEL: v_exp2_f32_0:
1851 ; GCN: ; %bb.0:
1852 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1853 ; GCN-NEXT: v_mov_b32_e32 v0, 1.0
1854 ; GCN-NEXT: s_setpc_b64 s[30:31]
1855 ;
1856 ; R600-LABEL: v_exp2_f32_0:
1857 ; R600: ; %bb.0:
1858 ; R600-NEXT: CF_END
1859 ; R600-NEXT: PAD
1860 ;
1861 ; CM-LABEL: v_exp2_f32_0:
1862 ; CM: ; %bb.0:
1863 ; CM-NEXT: CF_END
1864 ; CM-NEXT: PAD
1865 ; GFX89-SDAG-LABEL: v_exp2_f32_0:
1866 ; GFX89-SDAG: ; %bb.0:
1867 ; GFX89-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1868 ; GFX89-SDAG-NEXT: v_log_f32_e32 v0, 0
1869 ; GFX89-SDAG-NEXT: s_setpc_b64 s[30:31]
1870 ; GFX89-GISEL-LABEL: v_exp2_f32_0:
1871 ; GFX89-GISEL: ; %bb.0:
1872 ; GFX89-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1873 ; GFX89-GISEL-NEXT: v_mov_b32_e32 v0, 0xff800000
1874 ; GFX89-GISEL-NEXT: s_setpc_b64 s[30:31]
1875 %result = call float @llvm.exp2.f32(float 0.0)
1876 ret float %result
1877 }
1879 define float @v_exp2_f32_from_fpext_f16(i16 %src.i) {
1880 ; GCN-LABEL: v_exp2_f32_from_fpext_f16:
1881 ; GCN: ; %bb.0:
1882 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1883 ; GCN-NEXT: v_cvt_f32_f16_e32 v0, v0
1884 ; GCN-NEXT: v_exp_f32_e32 v0, v0
1885 ; GCN-NEXT: s_setpc_b64 s[30:31]
1886 ;
1887 ; R600-LABEL: v_exp2_f32_from_fpext_f16:
1888 ; R600: ; %bb.0:
1889 ; R600-NEXT: CF_END
1890 ; R600-NEXT: PAD
1891 ;
1892 ; CM-LABEL: v_exp2_f32_from_fpext_f16:
1893 ; CM: ; %bb.0:
1894 ; CM-NEXT: CF_END
1895 ; CM-NEXT: PAD
1896 %src = bitcast i16 %src.i to half
1897 %fpext = fpext half %src to float
1898 %result = call float @llvm.exp2.f32(float %fpext)
1899 ret float %result
1900 }
1902 define float @v_exp2_f32_from_fpext_math_f16(i16 %src0.i, i16 %src1.i) {
1903 ; SI-SDAG-LABEL: v_exp2_f32_from_fpext_math_f16:
1904 ; SI-SDAG: ; %bb.0:
1905 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1906 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
1907 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
1908 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
1909 ; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
1910 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42800000
1911 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1912 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1913 ; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
1914 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
1915 ; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
1916 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1917 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
1918 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
1919 ;
1920 ; SI-GISEL-LABEL: v_exp2_f32_from_fpext_math_f16:
1921 ; SI-GISEL: ; %bb.0:
1922 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1923 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
1924 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
1925 ; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
1926 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
1927 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
1928 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
1929 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
1930 ;
1931 ; VI-LABEL: v_exp2_f32_from_fpext_math_f16:
1932 ; VI: ; %bb.0:
1933 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1934 ; VI-NEXT: v_add_f16_e32 v0, v0, v1
1935 ; VI-NEXT: v_cvt_f32_f16_e32 v0, v0
1936 ; VI-NEXT: v_exp_f32_e32 v0, v0
1937 ; VI-NEXT: s_setpc_b64 s[30:31]
1938 ;
1939 ; GFX900-LABEL: v_exp2_f32_from_fpext_math_f16:
1940 ; GFX900: ; %bb.0:
1941 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1942 ; GFX900-NEXT: v_add_f16_e32 v0, v0, v1
1943 ; GFX900-NEXT: v_cvt_f32_f16_e32 v0, v0
1944 ; GFX900-NEXT: v_exp_f32_e32 v0, v0
1945 ; GFX900-NEXT: s_setpc_b64 s[30:31]
1946 ;
1947 ; R600-LABEL: v_exp2_f32_from_fpext_math_f16:
1948 ; R600: ; %bb.0:
1949 ; R600-NEXT: CF_END
1950 ; R600-NEXT: PAD
1951 ;
1952 ; CM-LABEL: v_exp2_f32_from_fpext_math_f16:
1953 ; CM: ; %bb.0:
1954 ; CM-NEXT: CF_END
1955 ; CM-NEXT: PAD
1956 ; GFX89-LABEL: v_exp2_f32_from_fpext_math_f16:
1957 ; GFX89: ; %bb.0:
1958 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1959 ; GFX89-NEXT: v_add_f16_e32 v0, v0, v1
1960 ; GFX89-NEXT: v_cvt_f32_f16_e32 v0, v0
1961 ; GFX89-NEXT: v_log_f32_e32 v0, v0
1962 ; GFX89-NEXT: s_setpc_b64 s[30:31]
1963 %src0 = bitcast i16 %src0.i to half
1964 %src1 = bitcast i16 %src1.i to half
1965 %fadd = fadd half %src0, %src1
1966 %fpext = fpext half %fadd to float
1967 %result = call float @llvm.exp2.f32(float %fpext)
1968 ret float %result
1969 }
1971 define float @v_exp2_f32_from_fpext_bf16(bfloat %src) {
1972 ; SI-LABEL: v_exp2_f32_from_fpext_bf16:
1973 ; SI: ; %bb.0:
1974 ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1975 ; SI-NEXT: s_mov_b32 s4, 0xc2fc0000
1976 ; SI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1977 ; SI-NEXT: v_mov_b32_e32 v2, 0x42800000
1978 ; SI-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
1979 ; SI-NEXT: v_add_f32_e32 v0, v0, v2
1980 ; SI-NEXT: v_exp_f32_e32 v0, v0
1981 ; SI-NEXT: v_mov_b32_e32 v1, 0x1f800000
1982 ; SI-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1983 ; SI-NEXT: v_mul_f32_e32 v0, v0, v1
1984 ; SI-NEXT: s_setpc_b64 s[30:31]
1985 ;
1986 ; VI-LABEL: v_exp2_f32_from_fpext_bf16:
1987 ; VI: ; %bb.0:
1988 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1989 ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
1990 ; VI-NEXT: s_mov_b32 s4, 0xc2fc0000
1991 ; VI-NEXT: v_mov_b32_e32 v1, 0x42800000
1992 ; VI-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
1993 ; VI-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
1994 ; VI-NEXT: v_add_f32_e32 v0, v0, v1
1995 ; VI-NEXT: v_exp_f32_e32 v0, v0
1996 ; VI-NEXT: v_mov_b32_e32 v1, 0x1f800000
1997 ; VI-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
1998 ; VI-NEXT: v_mul_f32_e32 v0, v0, v1
1999 ; VI-NEXT: s_setpc_b64 s[30:31]
2000 ;
2001 ; GFX900-LABEL: v_exp2_f32_from_fpext_bf16:
2002 ; GFX900: ; %bb.0:
2003 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2004 ; GFX900-NEXT: v_lshlrev_b32_e32 v0, 16, v0
2005 ; GFX900-NEXT: s_mov_b32 s4, 0xc2fc0000
2006 ; GFX900-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
2007 ; GFX900-NEXT: v_mov_b32_e32 v2, 0x42800000
2008 ; GFX900-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
2009 ; GFX900-NEXT: v_add_f32_e32 v0, v0, v2
2010 ; GFX900-NEXT: v_exp_f32_e32 v0, v0
2011 ; GFX900-NEXT: v_mov_b32_e32 v1, 0x1f800000
2012 ; GFX900-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
2013 ; GFX900-NEXT: v_mul_f32_e32 v0, v0, v1
2014 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2015 ;
2016 ; R600-LABEL: v_exp2_f32_from_fpext_bf16:
2017 ; R600: ; %bb.0:
2018 ; R600-NEXT: CF_END
2019 ; R600-NEXT: PAD
2020 ;
2021 ; CM-LABEL: v_exp2_f32_from_fpext_bf16:
2022 ; CM: ; %bb.0:
2023 ; CM-NEXT: CF_END
2024 ; CM-NEXT: PAD
2025 ; GFX89-SDAG-LABEL: v_exp2_f32_from_fpext_bf16:
2026 ; GFX89-SDAG: ; %bb.0:
2027 ; GFX89-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2028 ; GFX89-SDAG-NEXT: v_log_f32_e32 v0, v0
2029 ; GFX89-SDAG-NEXT: s_setpc_b64 s[30:31]
2030 ; GFX89-GISEL-LABEL: v_exp2_f32_from_fpext_bf16:
2031 ; GFX89-GISEL: ; %bb.0:
2032 ; GFX89-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2033 ; GFX89-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2034 ; GFX89-GISEL-NEXT: v_log_f32_e32 v0, v0
2035 ; GFX89-GISEL-NEXT: s_setpc_b64 s[30:31]
2036 %fpext = fpext bfloat %src to float
2037 %result = call float @llvm.exp2.f32(float %fpext)
2038 ret float %result
2039 }
2041 ; FIXME: Fold out fp16_to_fp (FP_TO_FP16) on no-f16 targets
2042 define half @v_exp2_f16(half %in) {
2043 ; SI-SDAG-LABEL: v_exp2_f16:
2044 ; SI-SDAG: ; %bb.0:
2045 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2046 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2047 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2048 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2049 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2050 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2051 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2052 ;
2053 ; SI-GISEL-LABEL: v_exp2_f16:
2054 ; SI-GISEL: ; %bb.0:
2055 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2056 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2057 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2058 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2059 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2060 ;
2061 ; VI-LABEL: v_exp2_f16:
2062 ; VI: ; %bb.0:
2063 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2064 ; VI-NEXT: v_exp_f16_e32 v0, v0
2065 ; VI-NEXT: s_setpc_b64 s[30:31]
2066 ;
2067 ; GFX900-LABEL: v_exp2_f16:
2068 ; GFX900: ; %bb.0:
2069 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2070 ; GFX900-NEXT: v_exp_f16_e32 v0, v0
2071 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2072 ;
2073 ; R600-LABEL: v_exp2_f16:
2074 ; R600: ; %bb.0:
2075 ; R600-NEXT: CF_END
2076 ; R600-NEXT: PAD
2077 ;
2078 ; CM-LABEL: v_exp2_f16:
2079 ; CM: ; %bb.0:
2080 ; CM-NEXT: CF_END
2081 ; CM-NEXT: PAD
2082 ; GFX89-LABEL: v_exp2_f16:
2083 ; GFX89: ; %bb.0:
2084 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2085 ; GFX89-NEXT: v_log_f16_e32 v0, v0
2086 ; GFX89-NEXT: s_setpc_b64 s[30:31]
2087 %result = call half @llvm.exp2.f16(half %in)
2088 ret half %result
2089 }
2091 define half @v_exp2_fabs_f16(half %in) {
2092 ; SI-SDAG-LABEL: v_exp2_fabs_f16:
2093 ; SI-SDAG: ; %bb.0:
2094 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2095 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2096 ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|
2097 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2098 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2099 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2100 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2101 ;
2102 ; SI-GISEL-LABEL: v_exp2_fabs_f16:
2103 ; SI-GISEL: ; %bb.0:
2104 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2105 ; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, |v0|
2106 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2107 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2108 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2109 ;
2110 ; VI-LABEL: v_exp2_fabs_f16:
2111 ; VI: ; %bb.0:
2112 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2113 ; VI-NEXT: v_exp_f16_e64 v0, |v0|
2114 ; VI-NEXT: s_setpc_b64 s[30:31]
2115 ;
2116 ; GFX900-LABEL: v_exp2_fabs_f16:
2117 ; GFX900: ; %bb.0:
2118 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2119 ; GFX900-NEXT: v_exp_f16_e64 v0, |v0|
2120 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2121 ;
2122 ; R600-LABEL: v_exp2_fabs_f16:
2123 ; R600: ; %bb.0:
2124 ; R600-NEXT: CF_END
2125 ; R600-NEXT: PAD
2126 ;
2127 ; CM-LABEL: v_exp2_fabs_f16:
2128 ; CM: ; %bb.0:
2129 ; CM-NEXT: CF_END
2130 ; CM-NEXT: PAD
2131 ; GFX89-LABEL: v_exp2_fabs_f16:
2132 ; GFX89: ; %bb.0:
2133 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2134 ; GFX89-NEXT: v_log_f16_e64 v0, |v0|
2135 ; GFX89-NEXT: s_setpc_b64 s[30:31]
2136 %fabs = call half @llvm.fabs.f16(half %in)
2137 %result = call half @llvm.exp2.f16(half %fabs)
2138 ret half %result
2139 }
2141 define half @v_exp2_fneg_fabs_f16(half %in) {
2142 ; SI-SDAG-LABEL: v_exp2_fneg_fabs_f16:
2143 ; SI-SDAG: ; %bb.0:
2144 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2145 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2146 ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
2147 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2148 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2149 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2150 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2151 ;
2152 ; SI-GISEL-LABEL: v_exp2_fneg_fabs_f16:
2153 ; SI-GISEL: ; %bb.0:
2154 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2155 ; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -|v0|
2156 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2157 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2158 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2159 ;
2160 ; VI-LABEL: v_exp2_fneg_fabs_f16:
2161 ; VI: ; %bb.0:
2162 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2163 ; VI-NEXT: v_exp_f16_e64 v0, -|v0|
2164 ; VI-NEXT: s_setpc_b64 s[30:31]
2165 ;
2166 ; GFX900-LABEL: v_exp2_fneg_fabs_f16:
2167 ; GFX900: ; %bb.0:
2168 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2169 ; GFX900-NEXT: v_exp_f16_e64 v0, -|v0|
2170 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2171 ;
2172 ; R600-LABEL: v_exp2_fneg_fabs_f16:
2173 ; R600: ; %bb.0:
2174 ; R600-NEXT: CF_END
2175 ; R600-NEXT: PAD
2176 ;
2177 ; CM-LABEL: v_exp2_fneg_fabs_f16:
2178 ; CM: ; %bb.0:
2179 ; CM-NEXT: CF_END
2180 ; CM-NEXT: PAD
2181 ; GFX89-LABEL: v_exp2_fneg_fabs_f16:
2182 ; GFX89: ; %bb.0:
2183 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2184 ; GFX89-NEXT: v_log_f16_e64 v0, -|v0|
2185 ; GFX89-NEXT: s_setpc_b64 s[30:31]
2186 %fabs = call half @llvm.fabs.f16(half %in)
2187 %fneg.fabs = fneg half %fabs
2188 %result = call half @llvm.exp2.f16(half %fneg.fabs)
2189 ret half %result
2190 }
2192 define half @v_exp2_fneg_f16(half %in) {
2193 ; SI-SDAG-LABEL: v_exp2_fneg_f16:
2194 ; SI-SDAG: ; %bb.0:
2195 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2196 ; SI-SDAG-NEXT: v_cvt_f16_f32_e64 v0, -v0
2197 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2198 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2199 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2200 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2201 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2202 ;
2203 ; SI-GISEL-LABEL: v_exp2_fneg_f16:
2204 ; SI-GISEL: ; %bb.0:
2205 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2206 ; SI-GISEL-NEXT: v_cvt_f32_f16_e64 v0, -v0
2207 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2208 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2209 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2210 ;
2211 ; VI-LABEL: v_exp2_fneg_f16:
2212 ; VI: ; %bb.0:
2213 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2214 ; VI-NEXT: v_exp_f16_e64 v0, -v0
2215 ; VI-NEXT: s_setpc_b64 s[30:31]
2216 ;
2217 ; GFX900-LABEL: v_exp2_fneg_f16:
2218 ; GFX900: ; %bb.0:
2219 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2220 ; GFX900-NEXT: v_exp_f16_e64 v0, -v0
2221 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2222 ;
2223 ; R600-LABEL: v_exp2_fneg_f16:
2224 ; R600: ; %bb.0:
2225 ; R600-NEXT: CF_END
2226 ; R600-NEXT: PAD
2227 ;
2228 ; CM-LABEL: v_exp2_fneg_f16:
2229 ; CM: ; %bb.0:
2230 ; CM-NEXT: CF_END
2231 ; CM-NEXT: PAD
2232 ; GFX89-LABEL: v_exp2_fneg_f16:
2233 ; GFX89: ; %bb.0:
2234 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2235 ; GFX89-NEXT: v_log_f16_e64 v0, -v0
2236 ; GFX89-NEXT: s_setpc_b64 s[30:31]
2237 %fneg = fneg half %in
2238 %result = call half @llvm.exp2.f16(half %fneg)
2239 ret half %result
2240 }
2242 define half @v_exp2_f16_fast(half %in) {
2243 ; SI-SDAG-LABEL: v_exp2_f16_fast:
2244 ; SI-SDAG: ; %bb.0:
2245 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2246 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2247 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2248 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2249 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2250 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2251 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2252 ;
2253 ; SI-GISEL-LABEL: v_exp2_f16_fast:
2254 ; SI-GISEL: ; %bb.0:
2255 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2256 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2257 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2258 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2259 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2260 ;
2261 ; VI-LABEL: v_exp2_f16_fast:
2262 ; VI: ; %bb.0:
2263 ; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2264 ; VI-NEXT: v_exp_f16_e32 v0, v0
2265 ; VI-NEXT: s_setpc_b64 s[30:31]
2266 ;
2267 ; GFX900-LABEL: v_exp2_f16_fast:
2268 ; GFX900: ; %bb.0:
2269 ; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2270 ; GFX900-NEXT: v_exp_f16_e32 v0, v0
2271 ; GFX900-NEXT: s_setpc_b64 s[30:31]
2272 ;
2273 ; R600-LABEL: v_exp2_f16_fast:
2274 ; R600: ; %bb.0:
2275 ; R600-NEXT: CF_END
2276 ; R600-NEXT: PAD
2277 ;
2278 ; CM-LABEL: v_exp2_f16_fast:
2279 ; CM: ; %bb.0:
2280 ; CM-NEXT: CF_END
2281 ; CM-NEXT: PAD
2282 ; GFX89-LABEL: v_exp2_f16_fast:
2283 ; GFX89: ; %bb.0:
2284 ; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2285 ; GFX89-NEXT: v_log_f16_e32 v0, v0
2286 ; GFX89-NEXT: s_setpc_b64 s[30:31]
2287 %result = call fast half @llvm.exp2.f16(half %in)
2288 ret half %result
2289 }
2291 define <2 x half> @v_exp2_v2f16(<2 x half> %in) {
2292 ; SI-SDAG-LABEL: v_exp2_v2f16:
2293 ; SI-SDAG: ; %bb.0:
2294 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2295 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2296 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2297 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2298 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2299 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2300 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2301 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2302 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2303 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2304 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2305 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2306 ;
2307 ; SI-GISEL-LABEL: v_exp2_v2f16:
2308 ; SI-GISEL: ; %bb.0:
2309 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2310 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2311 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2312 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2313 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2314 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2315 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2316 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2317 ;
2318 ; VI-SDAG-LABEL: v_exp2_v2f16:
2319 ; VI-SDAG: ; %bb.0:
2320 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2321 ; VI-SDAG-NEXT: v_exp_f16_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2322 ; VI-SDAG-NEXT: v_exp_f16_e32 v0, v0
2323 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2324 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2325 ;
2326 ; VI-GISEL-LABEL: v_exp2_v2f16:
2327 ; VI-GISEL: ; %bb.0:
2328 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2329 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v0
2330 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2331 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2332 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2333 ;
2334 ; GFX900-SDAG-LABEL: v_exp2_v2f16:
2335 ; GFX900-SDAG: ; %bb.0:
2336 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2337 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2338 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v0
2339 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
2340 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2341 ;
2342 ; GFX900-GISEL-LABEL: v_exp2_v2f16:
2343 ; GFX900-GISEL: ; %bb.0:
2344 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2345 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v0
2346 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2347 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
2348 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2349 ;
2350 ; R600-LABEL: v_exp2_v2f16:
2351 ; R600: ; %bb.0:
2352 ; R600-NEXT: CF_END
2353 ; R600-NEXT: PAD
2354 ;
2355 ; CM-LABEL: v_exp2_v2f16:
2356 ; CM: ; %bb.0:
2357 ; CM-NEXT: CF_END
2358 ; CM-NEXT: PAD
2359 %result = call <2 x half> @llvm.exp2.v2f16(<2 x half> %in)
2360 ret <2 x half> %result
2361 }
2363 define <2 x half> @v_exp2_fabs_v2f16(<2 x half> %in) {
2364 ; SI-SDAG-LABEL: v_exp2_fabs_v2f16:
2365 ; SI-SDAG: ; %bb.0:
2366 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2367 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2368 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2369 ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v0, |v0|
2370 ; SI-SDAG-NEXT: v_cvt_f32_f16_e64 v1, |v1|
2371 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2372 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2373 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2374 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2375 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2376 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2377 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2378 ;
2379 ; SI-GISEL-LABEL: v_exp2_fabs_v2f16:
2380 ; SI-GISEL: ; %bb.0:
2381 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2382 ; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2383 ; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2384 ; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2385 ; SI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
2386 ; SI-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2387 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2388 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2389 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2390 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2391 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2392 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2393 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2394 ;
2395 ; VI-SDAG-LABEL: v_exp2_fabs_v2f16:
2396 ; VI-SDAG: ; %bb.0:
2397 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2398 ; VI-SDAG-NEXT: v_exp_f16_sdwa v1, |v0| dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2399 ; VI-SDAG-NEXT: v_exp_f16_e64 v0, |v0|
2400 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2401 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2402 ;
2403 ; VI-GISEL-LABEL: v_exp2_fabs_v2f16:
2404 ; VI-GISEL: ; %bb.0:
2405 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2406 ; VI-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
2407 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v0
2408 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2409 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2410 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2411 ;
2412 ; GFX900-SDAG-LABEL: v_exp2_fabs_v2f16:
2413 ; GFX900-SDAG: ; %bb.0:
2414 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2415 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v1, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2416 ; GFX900-SDAG-NEXT: v_exp_f16_e64 v0, |v0|
2417 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
2418 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2419 ;
2420 ; GFX900-GISEL-LABEL: v_exp2_fabs_v2f16:
2421 ; GFX900-GISEL: ; %bb.0:
2422 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2423 ; GFX900-GISEL-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
2424 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v0
2425 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2426 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
2427 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2428 ;
2429 ; R600-LABEL: v_exp2_fabs_v2f16:
2430 ; R600: ; %bb.0:
2431 ; R600-NEXT: CF_END
2432 ; R600-NEXT: PAD
2433 ;
2434 ; CM-LABEL: v_exp2_fabs_v2f16:
2435 ; CM: ; %bb.0:
2436 ; CM-NEXT: CF_END
2437 ; CM-NEXT: PAD
2438 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
2439 %result = call <2 x half> @llvm.exp2.v2f16(<2 x half> %fabs)
2440 ret <2 x half> %result
2441 }
2443 define <2 x half> @v_exp2_fneg_fabs_v2f16(<2 x half> %in) {
2444 ; SI-SDAG-LABEL: v_exp2_fneg_fabs_v2f16:
2445 ; SI-SDAG: ; %bb.0:
2446 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2447 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2448 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2449 ; SI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2450 ; SI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2451 ; SI-SDAG-NEXT: v_or_b32_e32 v0, 0x80008000, v0
2452 ; SI-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2453 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2454 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2455 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2456 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2457 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2458 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2459 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2460 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2461 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2462 ;
2463 ; SI-GISEL-LABEL: v_exp2_fneg_fabs_v2f16:
2464 ; SI-GISEL: ; %bb.0:
2465 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2466 ; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2467 ; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2468 ; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2469 ; SI-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
2470 ; SI-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2471 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2472 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2473 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2474 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2475 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2476 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2477 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2478 ;
2479 ; VI-SDAG-LABEL: v_exp2_fneg_fabs_v2f16:
2480 ; VI-SDAG: ; %bb.0:
2481 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2482 ; VI-SDAG-NEXT: v_exp_f16_sdwa v1, -|v0| dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2483 ; VI-SDAG-NEXT: v_exp_f16_e64 v0, -|v0|
2484 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2485 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2486 ;
2487 ; VI-GISEL-LABEL: v_exp2_fneg_fabs_v2f16:
2488 ; VI-GISEL: ; %bb.0:
2489 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2490 ; VI-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
2491 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v0
2492 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2493 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2494 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2495 ;
2496 ; GFX900-SDAG-LABEL: v_exp2_fneg_fabs_v2f16:
2497 ; GFX900-SDAG: ; %bb.0:
2498 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2499 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v1, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2500 ; GFX900-SDAG-NEXT: v_exp_f16_e64 v0, -|v0|
2501 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
2502 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2503 ;
2504 ; GFX900-GISEL-LABEL: v_exp2_fneg_fabs_v2f16:
2505 ; GFX900-GISEL: ; %bb.0:
2506 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2507 ; GFX900-GISEL-NEXT: v_or_b32_e32 v0, 0x80008000, v0
2508 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v0
2509 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2510 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
2511 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2512 ;
2513 ; R600-LABEL: v_exp2_fneg_fabs_v2f16:
2514 ; R600: ; %bb.0:
2515 ; R600-NEXT: CF_END
2516 ; R600-NEXT: PAD
2517 ;
2518 ; CM-LABEL: v_exp2_fneg_fabs_v2f16:
2519 ; CM: ; %bb.0:
2520 ; CM-NEXT: CF_END
2521 ; CM-NEXT: PAD
2522 %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %in)
2523 %fneg.fabs = fneg <2 x half> %fabs
2524 %result = call <2 x half> @llvm.exp2.v2f16(<2 x half> %fneg.fabs)
2525 ret <2 x half> %result
2526 }
2528 define <2 x half> @v_exp2_fneg_v2f16(<2 x half> %in) {
2529 ; SI-SDAG-LABEL: v_exp2_fneg_v2f16:
2530 ; SI-SDAG: ; %bb.0:
2531 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2532 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2533 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2534 ; SI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2535 ; SI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2536 ; SI-SDAG-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
2537 ; SI-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2538 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2539 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2540 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2541 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2542 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2543 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2544 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2545 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2546 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2547 ;
2548 ; SI-GISEL-LABEL: v_exp2_fneg_v2f16:
2549 ; SI-GISEL: ; %bb.0:
2550 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2551 ; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2552 ; SI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
2553 ; SI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2554 ; SI-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
2555 ; SI-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
2556 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2557 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2558 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2559 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2560 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2561 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2562 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2563 ;
2564 ; VI-SDAG-LABEL: v_exp2_fneg_v2f16:
2565 ; VI-SDAG: ; %bb.0:
2566 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2567 ; VI-SDAG-NEXT: v_exp_f16_sdwa v1, -v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2568 ; VI-SDAG-NEXT: v_exp_f16_e64 v0, -v0
2569 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2570 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2571 ;
2572 ; VI-GISEL-LABEL: v_exp2_fneg_v2f16:
2573 ; VI-GISEL: ; %bb.0:
2574 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2575 ; VI-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
2576 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v0
2577 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2578 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2579 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2580 ;
2581 ; GFX900-SDAG-LABEL: v_exp2_fneg_v2f16:
2582 ; GFX900-SDAG: ; %bb.0:
2583 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2584 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v1, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2585 ; GFX900-SDAG-NEXT: v_exp_f16_e64 v0, -v0
2586 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
2587 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2588 ;
2589 ; GFX900-GISEL-LABEL: v_exp2_fneg_v2f16:
2590 ; GFX900-GISEL: ; %bb.0:
2591 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2592 ; GFX900-GISEL-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
2593 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v0
2594 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2595 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
2596 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2597 ;
2598 ; R600-LABEL: v_exp2_fneg_v2f16:
2599 ; R600: ; %bb.0:
2600 ; R600-NEXT: CF_END
2601 ; R600-NEXT: PAD
2602 ;
2603 ; CM-LABEL: v_exp2_fneg_v2f16:
2604 ; CM: ; %bb.0:
2605 ; CM-NEXT: CF_END
2606 ; CM-NEXT: PAD
2607 %fneg = fneg <2 x half> %in
2608 %result = call <2 x half> @llvm.exp2.v2f16(<2 x half> %fneg)
2609 ret <2 x half> %result
2610 }
2612 define <2 x half> @v_exp2_v2f16_fast(<2 x half> %in) {
2613 ; SI-SDAG-LABEL: v_exp2_v2f16_fast:
2614 ; SI-SDAG: ; %bb.0:
2615 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2616 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2617 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2618 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2619 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2620 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2621 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2622 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2623 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2624 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2625 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2626 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2627 ;
2628 ; SI-GISEL-LABEL: v_exp2_v2f16_fast:
2629 ; SI-GISEL: ; %bb.0:
2630 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2631 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2632 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2633 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2634 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2635 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2636 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2637 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2638 ;
2639 ; VI-SDAG-LABEL: v_exp2_v2f16_fast:
2640 ; VI-SDAG: ; %bb.0:
2641 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2642 ; VI-SDAG-NEXT: v_exp_f16_sdwa v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2643 ; VI-SDAG-NEXT: v_exp_f16_e32 v0, v0
2644 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
2645 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2646 ;
2647 ; VI-GISEL-LABEL: v_exp2_v2f16_fast:
2648 ; VI-GISEL: ; %bb.0:
2649 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2650 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v0
2651 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2652 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v1, v0
2653 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2654 ;
2655 ; GFX900-SDAG-LABEL: v_exp2_v2f16_fast:
2656 ; GFX900-SDAG: ; %bb.0:
2657 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2658 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2659 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v0
2660 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v1
2661 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2662 ;
2663 ; GFX900-GISEL-LABEL: v_exp2_v2f16_fast:
2664 ; GFX900-GISEL: ; %bb.0:
2665 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2666 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v0
2667 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2668 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v1
2669 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2670 ;
2671 ; R600-LABEL: v_exp2_v2f16_fast:
2672 ; R600: ; %bb.0:
2673 ; R600-NEXT: CF_END
2674 ; R600-NEXT: PAD
2675 ;
2676 ; CM-LABEL: v_exp2_v2f16_fast:
2677 ; CM: ; %bb.0:
2678 ; CM-NEXT: CF_END
2679 ; CM-NEXT: PAD
2680 %result = call fast <2 x half> @llvm.exp2.v2f16(<2 x half> %in)
2681 ret <2 x half> %result
2682 }
2684 define <3 x half> @v_exp_v3f16(<3 x half> %in) {
2685 ; SI-SDAG-LABEL: v_exp_v3f16:
2686 ; SI-SDAG: ; %bb.0:
2687 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2688 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2689 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2690 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
2691 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2692 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2693 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
2694 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2695 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2696 ; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2
2697 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2698 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2699 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
2700 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2701 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2702 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
2703 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2704 ;
2705 ; SI-GISEL-LABEL: v_exp_v3f16:
2706 ; SI-GISEL: ; %bb.0:
2707 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2708 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2709 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2710 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2
2711 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2712 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2713 ; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
2714 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2715 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2716 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2
2717 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2718 ;
2719 ; VI-SDAG-LABEL: v_exp_v3f16:
2720 ; VI-SDAG: ; %bb.0:
2721 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2722 ; VI-SDAG-NEXT: v_exp_f16_sdwa v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2723 ; VI-SDAG-NEXT: v_exp_f16_e32 v0, v0
2724 ; VI-SDAG-NEXT: v_exp_f16_e32 v1, v1
2725 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
2726 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2727 ;
2728 ; VI-GISEL-LABEL: v_exp_v3f16:
2729 ; VI-GISEL: ; %bb.0:
2730 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2731 ; VI-GISEL-NEXT: v_exp_f16_e32 v2, v0
2732 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2733 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v1
2734 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
2735 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2736 ;
2737 ; GFX900-SDAG-LABEL: v_exp_v3f16:
2738 ; GFX900-SDAG: ; %bb.0:
2739 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2740 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2741 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v0
2742 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v1, v1
2743 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v2
2744 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2745 ;
2746 ; GFX900-GISEL-LABEL: v_exp_v3f16:
2747 ; GFX900-GISEL: ; %bb.0:
2748 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2749 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v2, v0
2750 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2751 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v1
2752 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
2753 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2754 ;
2755 ; R600-LABEL: v_exp_v3f16:
2756 ; R600: ; %bb.0:
2757 ; R600-NEXT: CF_END
2758 ; R600-NEXT: PAD
2759 ;
2760 ; CM-LABEL: v_exp_v3f16:
2761 ; CM: ; %bb.0:
2762 ; CM-NEXT: CF_END
2763 ; CM-NEXT: PAD
2764 %result = call <3 x half> @llvm.exp2.v3f16(<3 x half> %in)
2765 ret <3 x half> %result
2766 }
2768 define <3 x half> @v_exp2_v3f16_afn(<3 x half> %in) {
2769 ; SI-SDAG-LABEL: v_exp2_v3f16_afn:
2770 ; SI-SDAG: ; %bb.0:
2771 ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2772 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2773 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2774 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
2775 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2776 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2777 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
2778 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
2779 ; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
2780 ; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2
2781 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0
2782 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1
2783 ; SI-SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2
2784 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
2785 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
2786 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v2, v2
2787 ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
2788 ;
2789 ; SI-GISEL-LABEL: v_exp2_v3f16_afn:
2790 ; SI-GISEL: ; %bb.0:
2791 ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2792 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
2793 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
2794 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v2, v2
2795 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
2796 ; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
2797 ; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
2798 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0
2799 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1
2800 ; SI-GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2
2801 ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
2802 ;
2803 ; VI-SDAG-LABEL: v_exp2_v3f16_afn:
2804 ; VI-SDAG: ; %bb.0:
2805 ; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2806 ; VI-SDAG-NEXT: v_exp_f16_sdwa v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2807 ; VI-SDAG-NEXT: v_exp_f16_e32 v0, v0
2808 ; VI-SDAG-NEXT: v_exp_f16_e32 v1, v1
2809 ; VI-SDAG-NEXT: v_or_b32_e32 v0, v0, v2
2810 ; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
2811 ;
2812 ; VI-GISEL-LABEL: v_exp2_v3f16_afn:
2813 ; VI-GISEL: ; %bb.0:
2814 ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2815 ; VI-GISEL-NEXT: v_exp_f16_e32 v2, v0
2816 ; VI-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
2817 ; VI-GISEL-NEXT: v_exp_f16_e32 v1, v1
2818 ; VI-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
2819 ; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
2820 ;
2821 ; GFX900-SDAG-LABEL: v_exp2_v3f16_afn:
2822 ; GFX900-SDAG: ; %bb.0:
2823 ; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2824 ; GFX900-SDAG-NEXT: v_exp_f16_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2825 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v0, v0
2826 ; GFX900-SDAG-NEXT: v_exp_f16_e32 v1, v1
2827 ; GFX900-SDAG-NEXT: v_pack_b32_f16 v0, v0, v2
2828 ; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
2829 ;
2830 ; GFX900-GISEL-LABEL: v_exp2_v3f16_afn:
2831 ; GFX900-GISEL: ; %bb.0:
2832 ; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2833 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v2, v0
2834 ; GFX900-GISEL-NEXT: v_exp_f16_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
2835 ; GFX900-GISEL-NEXT: v_exp_f16_e32 v1, v1
2836 ; GFX900-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
2837 ; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
2838 ;
2839 ; R600-LABEL: v_exp2_v3f16_afn:
2840 ; R600: ; %bb.0:
2841 ; R600-NEXT: CF_END
2842 ; R600-NEXT: PAD
2843 ;
2844 ; CM-LABEL: v_exp2_v3f16_afn:
2845 ; CM: ; %bb.0:
2846 ; CM-NEXT: CF_END
2847 ; CM-NEXT: PAD
2848 %result = call afn <3 x half> @llvm.exp2.v3f16(<3 x half> %in)
2849 ret <3 x half> %result
2850 }
2852 define float @v_exp2_f32_contract(float %in) {
2853 ; GCN-SDAG-LABEL: v_exp2_f32_contract:
2854 ; GCN-SDAG: ; %bb.0:
2855 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2856 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
2857 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
2858 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
2859 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
2860 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
2861 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
2862 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
2863 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
2864 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
2865 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
2866 ;
2867 ; GCN-GISEL-LABEL: v_exp2_f32_contract:
2868 ; GCN-GISEL: ; %bb.0:
2869 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2870 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
2871 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
2872 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
2873 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
2874 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
2875 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
2876 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
2877 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
2878 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
2879 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
2880 ;
2881 ; R600-LABEL: v_exp2_f32_contract:
2882 ; R600: ; %bb.0:
2883 ; R600-NEXT: CF_END
2884 ; R600-NEXT: PAD
2885 ;
2886 ; CM-LABEL: v_exp2_f32_contract:
2887 ; CM: ; %bb.0:
2888 ; CM-NEXT: CF_END
2889 ; CM-NEXT: PAD
2890 %result = call contract float @llvm.exp2.f32(float %in)
2891 ret float %result
2892 }
2894 define float @v_exp2_f32_contract_daz(float %in) #0 {
2895 ; GCN-LABEL: v_exp2_f32_contract_daz:
2896 ; GCN: ; %bb.0:
2897 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2898 ; GCN-NEXT: v_exp_f32_e32 v0, v0
2899 ; GCN-NEXT: s_setpc_b64 s[30:31]
2900 ;
2901 ; R600-LABEL: v_exp2_f32_contract_daz:
2902 ; R600: ; %bb.0:
2903 ; R600-NEXT: CF_END
2904 ; R600-NEXT: PAD
2905 ;
2906 ; CM-LABEL: v_exp2_f32_contract_daz:
2907 ; CM: ; %bb.0:
2908 ; CM-NEXT: CF_END
2909 ; CM-NEXT: PAD
2910 %result = call contract float @llvm.exp2.f32(float %in)
2911 ret float %result
2912 }
2914 define float @v_exp2_f32_contract_nnan_ninf(float %in) {
2915 ; GCN-SDAG-LABEL: v_exp2_f32_contract_nnan_ninf:
2916 ; GCN-SDAG: ; %bb.0:
2917 ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2918 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
2919 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
2920 ; GCN-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
2921 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
2922 ; GCN-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
2923 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
2924 ; GCN-SDAG-NEXT: v_mov_b32_e32 v1, 0x1f800000
2925 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
2926 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, v0, v1
2927 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
2928 ;
2929 ; GCN-GISEL-LABEL: v_exp2_f32_contract_nnan_ninf:
2930 ; GCN-GISEL: ; %bb.0:
2931 ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2932 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
2933 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
2934 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
2935 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
2936 ; GCN-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
2937 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
2938 ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0x1f800000
2939 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
2940 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
2941 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
2942 ;
2943 ; R600-LABEL: v_exp2_f32_contract_nnan_ninf:
2944 ; R600: ; %bb.0:
2945 ; R600-NEXT: CF_END
2946 ; R600-NEXT: PAD
2947 ;
2948 ; CM-LABEL: v_exp2_f32_contract_nnan_ninf:
2949 ; CM: ; %bb.0:
2950 ; CM-NEXT: CF_END
2951 ; CM-NEXT: PAD
2952 %result = call contract nnan ninf float @llvm.exp2.f32(float %in)
2953 ret float %result
2954 }
2956 declare float @llvm.fabs.f32(float) #2
2957 declare float @llvm.exp2.f32(float) #2
2958 declare <2 x float> @llvm.exp2.v2f32(<2 x float>) #2
2959 declare <3 x float> @llvm.exp2.v3f32(<3 x float>) #2
2960 declare <4 x float> @llvm.exp2.v4f32(<4 x float>) #2
2961 declare half @llvm.fabs.f16(half) #2
2962 declare half @llvm.exp2.f16(half) #2
2963 declare <2 x half> @llvm.exp2.v2f16(<2 x half>) #2
2964 declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #2
2965 declare <3 x half> @llvm.exp2.v3f16(<3 x half>) #2
2967 attributes #0 = { "denormal-fp-math-f32"="ieee,preserve-sign" }
2968 attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" }
2969 attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }