llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s
   3 ---
   4 name: test_subregs_composition_vreg_1024
   5 tracksRegLiveness: true
   6 body:             |
   7   bb.0:
   8     ; CHECK-LABEL: name: test_subregs_composition_vreg_1024
   9     ; CHECK: undef [[V_MOV_B32_e32_:%[0-9]+]].sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec
  10     ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]].sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec
  11     ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub0_sub1
  12     ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]].sub1_sub2
  13     ; CHECK-NEXT: undef [[V_MOV_B32_e32_1:%[0-9]+]].sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
  14     ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]].sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
  15     ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub0_sub1_sub2
  16     ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]].sub1_sub2_sub3
  17     ; CHECK-NEXT: undef [[V_MOV_B32_e32_2:%[0-9]+]].sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec
  18     ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]].sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec
  19     ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub0_sub1_sub2_sub3
  20     ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]].sub1_sub2_sub3_sub4
  21     ; CHECK-NEXT: undef [[V_MOV_B32_e32_3:%[0-9]+]].sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec
  22     ; CHECK-NEXT: [[V_MOV_B32_e32_3:%[0-9]+]].sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec
  23     ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub0_sub1_sub2_sub3_sub4
  24     ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_3]].sub1_sub2_sub3_sub4_sub5
  25     ; CHECK-NEXT: undef [[V_MOV_B32_e32_4:%[0-9]+]].sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec
  26     ; CHECK-NEXT: [[V_MOV_B32_e32_4:%[0-9]+]].sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec
  27     ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_4]].sub0_sub1_sub2_sub3_sub4_sub5
  28     ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_4]].sub2_sub3_sub4_sub5_sub6_sub7
  29     undef %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
  30     %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
  31     S_NOP 0, implicit %0.sub1_sub2
  32     S_NOP 0, implicit %0.sub2_sub3
  33
  34     undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
  35     %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
  36     S_NOP 0, implicit %1.sub1_sub2_sub3
  37     S_NOP 0, implicit %1.sub2_sub3_sub4
  38
  39     undef %2.sub1:vreg_1024 = V_MOV_B32_e32 21, implicit $exec
  40     %2.sub2:vreg_1024 = V_MOV_B32_e32 22, implicit $exec
  41     S_NOP 0, implicit %2.sub1_sub2_sub3_sub4
  42     S_NOP 0, implicit %2.sub2_sub3_sub4_sub5
  43
  44     undef %3.sub1:vreg_1024 = V_MOV_B32_e32 31, implicit $exec
  45     %3.sub2:vreg_1024 = V_MOV_B32_e32 32, implicit $exec
  46     S_NOP 0, implicit %3.sub1_sub2_sub3_sub4_sub5
  47     S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub6
  48
  49     undef %4.sub1:vreg_1024 = V_MOV_B32_e32 41, implicit $exec
  50     %4.sub3:vreg_1024 = V_MOV_B32_e32 43, implicit $exec
  51     S_NOP 0, implicit %4.sub1_sub2_sub3_sub4_sub5_sub6
  52     S_NOP 0, implicit %4.sub3_sub4_sub5_sub6_sub7_sub8
  53 ...
  54 ---
  55 name: test_subregs_unknown_regclass_from_instructions
  56 tracksRegLiveness: true
  57 body:             |
  58   bb.0:
  59     ; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions
  60     ; CHECK: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 1
  61     ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = S_MOV_B32 2
  62     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY [[S_MOV_B32_]]
  63     undef %0.sub4:sgpr_1024 = S_MOV_B32 01
  64     %0.sub5:sgpr_1024 = S_MOV_B32 02
  65     %1:vreg_64 = COPY %0.sub4_sub5
  66 ...
  67 ---
  68 name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_64
  69 tracksRegLiveness: true
  70 registers:
  71   - { id: 0, class: sgpr_1024 }
  72 body:             |
  73   bb.0:
  74     ; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_64
  75     ; CHECK: dead [[COPY:%[0-9]+]]:vreg_64 = COPY undef %2:sgpr_64
  76     %1:vreg_64 = COPY undef %0.sub4_sub5
  77 ...
  78 ---
  79 name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec
  80 tracksRegLiveness: true
  81 body:             |
  82   bb.0:
  83     ; CHECK-LABEL: name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec
  84     ; CHECK: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sgpr_64 = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
  85     ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
  86     undef %0.sub2_sub3:sgpr_128 = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
  87     %2:vreg_64 = COPY %0.sub2_sub3:sgpr_128
  88 ...
  89 ---
  90 name: test_vgpr_selected_instead_of_sgpr_because_use_allows_both
  91 tracksRegLiveness: true
  92 body:             |
  93   bb.0:
  94     ; CHECK-LABEL: name: test_vgpr_selected_instead_of_sgpr_because_use_allows_both
  95     ; CHECK: [[COPY:%[0-9]+]]:sgpr_32 = COPY undef %1:sgpr_32
  96     ; CHECK-NEXT: dead [[V_LSHL_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_ADD_U32_e64 [[COPY]], 2, undef %3:vgpr_32, implicit $exec
  97     undef %1.sub1:sgpr_96 = COPY undef %0:sgpr_32
  98     %3:vgpr_32 = V_LSHL_ADD_U32_e64 %1.sub1:sgpr_96, 2, undef %2:vgpr_32, implicit $exec
  99 ...
 100