| blob | 4865290fd51d85b302bcc0587f08a4aa1b410eb7 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -verify-machineinstrs < %s | FileCheck %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -global-isel -verify-machineinstrs < %s | FileCheck %s
4 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck %s
5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel -verify-machineinstrs < %s | FileCheck %s
7 define amdgpu_vs float @sitofp_i32_to_f32(i32 inreg %val) {
8 ; CHECK-LABEL: sitofp_i32_to_f32:
9 ; CHECK: ; %bb.0:
10 ; CHECK-NEXT: s_cvt_f32_i32 s0, s0
11 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
12 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
13 ; CHECK-NEXT: ; return to shader part epilog
14 %res = sitofp i32 %val to float
15 ret float %res
16 }
18 define amdgpu_vs float @uitofp_u32_to_f32(i32 inreg %val) {
19 ; CHECK-LABEL: uitofp_u32_to_f32:
20 ; CHECK: ; %bb.0:
21 ; CHECK-NEXT: s_cvt_f32_u32 s0, s0
22 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
23 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
24 ; CHECK-NEXT: ; return to shader part epilog
25 %res = uitofp i32 %val to float
26 ret float %res
27 }
29 define amdgpu_vs i32 @fptosi_f32_to_i32(float inreg %val) {
30 ; CHECK-LABEL: fptosi_f32_to_i32:
31 ; CHECK: ; %bb.0:
32 ; CHECK-NEXT: s_cvt_i32_f32 s0, s0
33 ; CHECK-NEXT: ; return to shader part epilog
34 %res = fptosi float %val to i32
35 ret i32 %res
36 }
38 define amdgpu_vs i32 @fptoui_f32_to_u32(float inreg %val) {
39 ; CHECK-LABEL: fptoui_f32_to_u32:
40 ; CHECK: ; %bb.0:
41 ; CHECK-NEXT: s_cvt_u32_f32 s0, s0
42 ; CHECK-NEXT: ; return to shader part epilog
43 %res = fptoui float %val to i32
44 ret i32 %res
45 }
47 define amdgpu_vs float @fpext_f16_to_f32(half inreg %val) {
48 ; CHECK-LABEL: fpext_f16_to_f32:
49 ; CHECK: ; %bb.0:
50 ; CHECK-NEXT: s_cvt_f32_f16 s0, s0
51 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
52 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
53 ; CHECK-NEXT: ; return to shader part epilog
54 %res = fpext half %val to float
55 ret float %res
56 }
58 define amdgpu_vs float @fpext_hif16_to_32(<2 x half> inreg %val) {
59 ; CHECK-LABEL: fpext_hif16_to_32:
60 ; CHECK: ; %bb.0:
61 ; CHECK-NEXT: s_cvt_hi_f32_f16 s0, s0
62 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
63 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
64 ; CHECK-NEXT: ; return to shader part epilog
65 %hielt = extractelement <2 x half> %val, i32 1
66 %res = fpext half %hielt to float
67 ret float %res
68 }
70 define amdgpu_vs half @fptrunc_f32_to_f16(float inreg %val) {
71 ; CHECK-LABEL: fptrunc_f32_to_f16:
72 ; CHECK: ; %bb.0:
73 ; CHECK-NEXT: s_cvt_f16_f32 s0, s0
74 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
75 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
76 ; CHECK-NEXT: ; return to shader part epilog
77 %res = fptrunc float %val to half
78 ret half %res
79 }
81 define amdgpu_vs float @fceil_f32(float inreg %val) {
82 ; CHECK-LABEL: fceil_f32:
83 ; CHECK: ; %bb.0:
84 ; CHECK-NEXT: s_ceil_f32 s0, s0
85 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
86 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
87 ; CHECK-NEXT: ; return to shader part epilog
88 %res = call float @llvm.ceil.f32(float %val)
89 ret float %res
90 }
92 define amdgpu_vs float @ffloor_f32(float inreg %val) {
93 ; CHECK-LABEL: ffloor_f32:
94 ; CHECK: ; %bb.0:
95 ; CHECK-NEXT: s_floor_f32 s0, s0
96 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
97 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
98 ; CHECK-NEXT: ; return to shader part epilog
99 %res = call float @llvm.floor.f32(float %val)
100 ret float %res
101 }
103 define amdgpu_vs float @ftrunc_f32(float inreg %val) {
104 ; CHECK-LABEL: ftrunc_f32:
105 ; CHECK: ; %bb.0:
106 ; CHECK-NEXT: s_trunc_f32 s0, s0
107 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
108 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
109 ; CHECK-NEXT: ; return to shader part epilog
110 %res = call float @llvm.trunc.f32(float %val)
111 ret float %res
112 }
114 define amdgpu_vs float @frint_f32(float inreg %val) {
115 ; CHECK-LABEL: frint_f32:
116 ; CHECK: ; %bb.0:
117 ; CHECK-NEXT: s_rndne_f32 s0, s0
118 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
119 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
120 ; CHECK-NEXT: ; return to shader part epilog
121 %res = call float @llvm.rint.f32(float %val)
122 ret float %res
123 }
125 define amdgpu_vs half @fceil_f16(half inreg %val) {
126 ; CHECK-LABEL: fceil_f16:
127 ; CHECK: ; %bb.0:
128 ; CHECK-NEXT: s_ceil_f16 s0, s0
129 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
130 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
131 ; CHECK-NEXT: ; return to shader part epilog
132 %res = call half @llvm.ceil.f16(half %val)
133 ret half %res
134 }
136 define amdgpu_vs half @ffloor_f16(half inreg %val) {
137 ; CHECK-LABEL: ffloor_f16:
138 ; CHECK: ; %bb.0:
139 ; CHECK-NEXT: s_floor_f16 s0, s0
140 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
141 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
142 ; CHECK-NEXT: ; return to shader part epilog
143 %res = call half @llvm.floor.f16(half %val)
144 ret half %res
145 }
147 define amdgpu_vs half @ftrunc_f16(half inreg %val) {
148 ; CHECK-LABEL: ftrunc_f16:
149 ; CHECK: ; %bb.0:
150 ; CHECK-NEXT: s_trunc_f16 s0, s0
151 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
152 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
153 ; CHECK-NEXT: ; return to shader part epilog
154 %res = call half @llvm.trunc.f16(half %val)
155 ret half %res
156 }
158 define amdgpu_vs half @frint_f16(half inreg %val) {
159 ; CHECK-LABEL: frint_f16:
160 ; CHECK: ; %bb.0:
161 ; CHECK-NEXT: s_rndne_f16 s0, s0
162 ; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
163 ; CHECK-NEXT: v_mov_b32_e32 v0, s0
164 ; CHECK-NEXT: ; return to shader part epilog
165 %res = call half @llvm.rint.f16(half %val)
166 ret half %res
167 }
169 declare float @llvm.ceil.f32(float)
170 declare float @llvm.floor.f32(float)
171 declare float @llvm.trunc.f32(float)
172 declare float @llvm.rint.f32(float)
173 declare half @llvm.ceil.f16(half)
174 declare half @llvm.floor.f16(half)
175 declare half @llvm.trunc.f16(half)
176 declare half @llvm.rint.f16(half)