| blob | b4f977db804392e501cb463953af6949693004e0 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3 ; RUN: llc -mtriple=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
5 define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y) {
6 ; GCN-LABEL: s_test_urem_i64:
7 ; GCN: ; %bb.0:
8 ; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xd
9 ; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9
10 ; GCN-NEXT: s_mov_b32 s7, 0xf000
11 ; GCN-NEXT: s_mov_b32 s6, -1
12 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
13 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12
14 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13
15 ; GCN-NEXT: s_sub_u32 s0, 0, s12
16 ; GCN-NEXT: s_subb_u32 s1, 0, s13
17 ; GCN-NEXT: s_mov_b32 s4, s8
18 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
19 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
20 ; GCN-NEXT: s_mov_b32 s5, s9
21 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
22 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
23 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
24 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
25 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
26 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
27 ; GCN-NEXT: v_mul_lo_u32 v2, s0, v1
28 ; GCN-NEXT: v_mul_hi_u32 v3, s0, v0
29 ; GCN-NEXT: v_mul_lo_u32 v5, s1, v0
30 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v0
31 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
32 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
33 ; GCN-NEXT: v_mul_hi_u32 v3, v0, v4
34 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
35 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v2
36 ; GCN-NEXT: v_mul_hi_u32 v6, v1, v4
37 ; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
38 ; GCN-NEXT: v_mul_hi_u32 v8, v1, v2
39 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
40 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
41 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
42 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
43 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc
44 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc
45 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
46 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
47 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
48 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
49 ; GCN-NEXT: v_mul_lo_u32 v2, s0, v1
50 ; GCN-NEXT: v_mul_hi_u32 v3, s0, v0
51 ; GCN-NEXT: v_mul_lo_u32 v4, s1, v0
52 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
53 ; GCN-NEXT: v_mul_lo_u32 v3, s0, v0
54 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
55 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v2
56 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v3
57 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v2
58 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v3
59 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
60 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v2
61 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
62 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
63 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
64 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
65 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc
66 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
67 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
68 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
69 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
70 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
71 ; GCN-NEXT: v_mul_lo_u32 v2, s10, v1
72 ; GCN-NEXT: v_mul_hi_u32 v3, s10, v0
73 ; GCN-NEXT: v_mul_hi_u32 v4, s10, v1
74 ; GCN-NEXT: v_mul_hi_u32 v5, s11, v1
75 ; GCN-NEXT: v_mul_lo_u32 v1, s11, v1
76 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
77 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
78 ; GCN-NEXT: v_mul_lo_u32 v4, s11, v0
79 ; GCN-NEXT: v_mul_hi_u32 v0, s11, v0
80 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
81 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
82 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc
83 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
84 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
85 ; GCN-NEXT: v_mul_lo_u32 v1, s12, v1
86 ; GCN-NEXT: v_mul_hi_u32 v2, s12, v0
87 ; GCN-NEXT: v_mul_lo_u32 v3, s13, v0
88 ; GCN-NEXT: v_mul_lo_u32 v0, s12, v0
89 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2
90 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1
91 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1
92 ; GCN-NEXT: v_mov_b32_e32 v3, s13
93 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0
94 ; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
95 ; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0
96 ; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
97 ; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v5
98 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
99 ; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v4
100 ; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
101 ; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
102 ; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v5
103 ; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s12, v4
104 ; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
105 ; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
106 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
107 ; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1]
108 ; GCN-NEXT: v_mov_b32_e32 v4, s11
109 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc
110 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v1
111 ; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
112 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0
113 ; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
114 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
115 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1
116 ; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
117 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
118 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
119 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
120 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
121 ; GCN-NEXT: s_endpgm
122 ;
123 ; GCN-IR-LABEL: s_test_urem_i64:
124 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
125 ; GCN-IR-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0xd
126 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
127 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
128 ; GCN-IR-NEXT: s_mov_b32 s11, 0
129 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
130 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0
131 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[12:13], s[2:3], 0
132 ; GCN-IR-NEXT: s_flbit_i32_b64 s10, s[6:7]
133 ; GCN-IR-NEXT: s_flbit_i32_b64 s18, s[2:3]
134 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
135 ; GCN-IR-NEXT: s_sub_u32 s12, s10, s18
136 ; GCN-IR-NEXT: s_subb_u32 s13, 0, 0
137 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[14:15], s[12:13], 63
138 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[12:13], 63
139 ; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[14:15]
140 ; GCN-IR-NEXT: s_and_b64 s[8:9], s[14:15], exec
141 ; GCN-IR-NEXT: s_cselect_b32 s9, 0, s3
142 ; GCN-IR-NEXT: s_cselect_b32 s8, 0, s2
143 ; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
144 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[14:15]
145 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
146 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
147 ; GCN-IR-NEXT: s_add_u32 s14, s12, 1
148 ; GCN-IR-NEXT: s_addc_u32 s15, s13, 0
149 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[14:15], 0
150 ; GCN-IR-NEXT: s_sub_i32 s12, 63, s12
151 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[8:9]
152 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s12
153 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
154 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
155 ; GCN-IR-NEXT: s_lshr_b64 s[12:13], s[2:3], s14
156 ; GCN-IR-NEXT: s_add_u32 s16, s6, -1
157 ; GCN-IR-NEXT: s_addc_u32 s17, s7, -1
158 ; GCN-IR-NEXT: s_not_b64 s[4:5], s[10:11]
159 ; GCN-IR-NEXT: s_add_u32 s10, s4, s18
160 ; GCN-IR-NEXT: s_addc_u32 s11, s5, 0
161 ; GCN-IR-NEXT: s_mov_b64 s[14:15], 0
162 ; GCN-IR-NEXT: s_mov_b32 s5, 0
163 ; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
164 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
165 ; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
166 ; GCN-IR-NEXT: s_lshr_b32 s4, s9, 31
167 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
168 ; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5]
169 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9]
170 ; GCN-IR-NEXT: s_sub_u32 s4, s16, s12
171 ; GCN-IR-NEXT: s_subb_u32 s4, s17, s13
172 ; GCN-IR-NEXT: s_ashr_i32 s14, s4, 31
173 ; GCN-IR-NEXT: s_mov_b32 s15, s14
174 ; GCN-IR-NEXT: s_and_b32 s4, s14, 1
175 ; GCN-IR-NEXT: s_and_b64 s[14:15], s[14:15], s[6:7]
176 ; GCN-IR-NEXT: s_sub_u32 s12, s12, s14
177 ; GCN-IR-NEXT: s_subb_u32 s13, s13, s15
178 ; GCN-IR-NEXT: s_add_u32 s10, s10, 1
179 ; GCN-IR-NEXT: s_addc_u32 s11, s11, 0
180 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[18:19], s[10:11], 0
181 ; GCN-IR-NEXT: s_mov_b64 s[14:15], s[4:5]
182 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[18:19]
183 ; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
184 ; GCN-IR-NEXT: .LBB0_4: ; %Flow7
185 ; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
186 ; GCN-IR-NEXT: s_or_b64 s[8:9], s[4:5], s[8:9]
187 ; GCN-IR-NEXT: .LBB0_5: ; %udiv-end
188 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
189 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s6, v0
190 ; GCN-IR-NEXT: s_mov_b32 s12, s0
191 ; GCN-IR-NEXT: s_mul_i32 s0, s6, s9
192 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
193 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0
194 ; GCN-IR-NEXT: s_mul_i32 s0, s7, s8
195 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0
196 ; GCN-IR-NEXT: s_mul_i32 s0, s6, s8
197 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
198 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
199 ; GCN-IR-NEXT: s_mov_b32 s15, 0xf000
200 ; GCN-IR-NEXT: s_mov_b32 s14, -1
201 ; GCN-IR-NEXT: s_mov_b32 s13, s1
202 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
203 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[12:15], 0
204 ; GCN-IR-NEXT: s_endpgm
205 %result = urem i64 %x, %y
206 store i64 %result, ptr addrspace(1) %out
207 ret void
208 }
210 define i64 @v_test_urem_i64(i64 %x, i64 %y) {
211 ; GCN-LABEL: v_test_urem_i64:
212 ; GCN: ; %bb.0:
213 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
214 ; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
215 ; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3
216 ; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
217 ; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
218 ; GCN-NEXT: v_madmk_f32 v4, v5, 0x4f800000, v4
219 ; GCN-NEXT: v_rcp_f32_e32 v4, v4
220 ; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
221 ; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
222 ; GCN-NEXT: v_trunc_f32_e32 v5, v5
223 ; GCN-NEXT: v_madmk_f32 v4, v5, 0xcf800000, v4
224 ; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
225 ; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
226 ; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
227 ; GCN-NEXT: v_mul_hi_u32 v9, v6, v4
228 ; GCN-NEXT: v_mul_lo_u32 v10, v7, v4
229 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
230 ; GCN-NEXT: v_mul_lo_u32 v9, v6, v4
231 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
232 ; GCN-NEXT: v_mul_lo_u32 v10, v4, v8
233 ; GCN-NEXT: v_mul_hi_u32 v11, v4, v9
234 ; GCN-NEXT: v_mul_hi_u32 v12, v4, v8
235 ; GCN-NEXT: v_mul_hi_u32 v13, v5, v8
236 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v8
237 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
238 ; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
239 ; GCN-NEXT: v_mul_lo_u32 v12, v5, v9
240 ; GCN-NEXT: v_mul_hi_u32 v9, v5, v9
241 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v12
242 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc
243 ; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v13, vcc
244 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
245 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
246 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
247 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
248 ; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
249 ; GCN-NEXT: v_mul_hi_u32 v9, v6, v4
250 ; GCN-NEXT: v_mul_lo_u32 v7, v7, v4
251 ; GCN-NEXT: v_mul_lo_u32 v6, v6, v4
252 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
253 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
254 ; GCN-NEXT: v_mul_lo_u32 v10, v4, v7
255 ; GCN-NEXT: v_mul_hi_u32 v11, v4, v6
256 ; GCN-NEXT: v_mul_hi_u32 v12, v4, v7
257 ; GCN-NEXT: v_mul_hi_u32 v9, v5, v6
258 ; GCN-NEXT: v_mul_lo_u32 v6, v5, v6
259 ; GCN-NEXT: v_mul_hi_u32 v8, v5, v7
260 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
261 ; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
262 ; GCN-NEXT: v_mul_lo_u32 v7, v5, v7
263 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
264 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
265 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
266 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
267 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
268 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
269 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
270 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v5
271 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v4
272 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v5
273 ; GCN-NEXT: v_mul_hi_u32 v9, v1, v5
274 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v5
275 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
276 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
277 ; GCN-NEXT: v_mul_lo_u32 v8, v1, v4
278 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
279 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
280 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc
281 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v9, vcc
282 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
283 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
284 ; GCN-NEXT: v_mul_lo_u32 v5, v2, v5
285 ; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
286 ; GCN-NEXT: v_mul_lo_u32 v7, v3, v4
287 ; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
288 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
289 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
290 ; GCN-NEXT: v_sub_i32_e32 v6, vcc, v1, v5
291 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
292 ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v6, v3, vcc
293 ; GCN-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2
294 ; GCN-NEXT: v_subbrev_u32_e64 v7, s[6:7], 0, v4, s[4:5]
295 ; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v7, v3
296 ; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]
297 ; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v6, v2
298 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc
299 ; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7]
300 ; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v7, v3
301 ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v3, s[4:5]
302 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
303 ; GCN-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[6:7]
304 ; GCN-NEXT: v_sub_i32_e64 v9, s[4:5], v6, v2
305 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
306 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
307 ; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
308 ; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
309 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
310 ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v8
311 ; GCN-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
312 ; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v9, s[4:5]
313 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
314 ; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v4, s[4:5]
315 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
316 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
317 ; GCN-NEXT: s_setpc_b64 s[30:31]
318 ;
319 ; GCN-IR-LABEL: v_test_urem_i64:
320 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
321 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
322 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2
323 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
324 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3
325 ; GCN-IR-NEXT: v_min_u32_e32 v12, v4, v5
326 ; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0
327 ; GCN-IR-NEXT: v_add_i32_e64 v4, s[6:7], 32, v4
328 ; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
329 ; GCN-IR-NEXT: v_min_u32_e32 v13, v4, v5
330 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[6:7], v12, v13
331 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
332 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
333 ; GCN-IR-NEXT: v_subb_u32_e64 v5, s[6:7], 0, 0, s[6:7]
334 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[6:7], 63, v[4:5]
335 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
336 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
337 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
338 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
339 ; GCN-IR-NEXT: v_cndmask_b32_e64 v7, v1, 0, s[4:5]
340 ; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v0, 0, s[4:5]
341 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
342 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
343 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
344 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
345 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
346 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
347 ; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v4
348 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9]
349 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
350 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
351 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
352 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
353 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
354 ; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
355 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
356 ; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2
357 ; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc
358 ; GCN-IR-NEXT: v_not_b32_e32 v7, v12
359 ; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v8
360 ; GCN-IR-NEXT: v_not_b32_e32 v6, 0
361 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v7, v13
362 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
363 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v6, vcc
364 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
365 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
366 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
367 ; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
368 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
369 ; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1
370 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
371 ; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
372 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
373 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
374 ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
375 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
376 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6
377 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v8
378 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5
379 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12
380 ; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v3
381 ; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v2
382 ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
383 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[8:9]
384 ; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v12
385 ; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v13, s[4:5]
386 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7
387 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
388 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
389 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
390 ; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
391 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
392 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
393 ; GCN-IR-NEXT: .LBB1_5: ; %Flow4
394 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
395 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
396 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5
397 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v4
398 ; GCN-IR-NEXT: .LBB1_6: ; %Flow5
399 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
400 ; GCN-IR-NEXT: v_mul_lo_u32 v4, v2, v7
401 ; GCN-IR-NEXT: v_mul_hi_u32 v5, v2, v6
402 ; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v6
403 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, v6
404 ; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v5, v4
405 ; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, v4, v3
406 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
407 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
408 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
409 %result = urem i64 %x, %y
410 ret i64 %result
411 }
413 define amdgpu_kernel void @s_test_urem31_i64(ptr addrspace(1) %out, i64 %x, i64 %y) {
414 ; GCN-LABEL: s_test_urem31_i64:
415 ; GCN: ; %bb.0:
416 ; GCN-NEXT: s_load_dword s0, s[4:5], 0xe
417 ; GCN-NEXT: s_mov_b32 s7, 0xf000
418 ; GCN-NEXT: s_mov_b32 s6, -1
419 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
420 ; GCN-NEXT: s_lshr_b32 s8, s0, 1
421 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
422 ; GCN-NEXT: s_sub_i32 s0, 0, s8
423 ; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
424 ; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
425 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
426 ; GCN-NEXT: v_mul_lo_u32 v1, s0, v0
427 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
428 ; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
429 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
430 ; GCN-NEXT: s_lshr_b32 s2, s3, 1
431 ; GCN-NEXT: s_mov_b32 s4, s0
432 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
433 ; GCN-NEXT: v_mul_hi_u32 v0, s2, v0
434 ; GCN-NEXT: s_mov_b32 s5, s1
435 ; GCN-NEXT: v_mov_b32_e32 v1, 0
436 ; GCN-NEXT: v_readfirstlane_b32 s0, v0
437 ; GCN-NEXT: s_mul_i32 s0, s0, s8
438 ; GCN-NEXT: s_sub_i32 s0, s2, s0
439 ; GCN-NEXT: s_sub_i32 s1, s0, s8
440 ; GCN-NEXT: s_cmp_ge_u32 s0, s8
441 ; GCN-NEXT: s_cselect_b32 s0, s1, s0
442 ; GCN-NEXT: s_sub_i32 s1, s0, s8
443 ; GCN-NEXT: s_cmp_ge_u32 s0, s8
444 ; GCN-NEXT: s_cselect_b32 s0, s1, s0
445 ; GCN-NEXT: v_mov_b32_e32 v0, s0
446 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
447 ; GCN-NEXT: s_endpgm
448 ;
449 ; GCN-IR-LABEL: s_test_urem31_i64:
450 ; GCN-IR: ; %bb.0:
451 ; GCN-IR-NEXT: s_load_dword s0, s[4:5], 0xe
452 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
453 ; GCN-IR-NEXT: s_mov_b32 s6, -1
454 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
455 ; GCN-IR-NEXT: s_lshr_b32 s8, s0, 1
456 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8
457 ; GCN-IR-NEXT: s_sub_i32 s0, 0, s8
458 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
459 ; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
460 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
461 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s0, v0
462 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
463 ; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
464 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
465 ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 1
466 ; GCN-IR-NEXT: s_mov_b32 s4, s0
467 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
468 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0
469 ; GCN-IR-NEXT: s_mov_b32 s5, s1
470 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
471 ; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0
472 ; GCN-IR-NEXT: s_mul_i32 s0, s0, s8
473 ; GCN-IR-NEXT: s_sub_i32 s0, s2, s0
474 ; GCN-IR-NEXT: s_sub_i32 s1, s0, s8
475 ; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
476 ; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0
477 ; GCN-IR-NEXT: s_sub_i32 s1, s0, s8
478 ; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8
479 ; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0
480 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
481 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
482 ; GCN-IR-NEXT: s_endpgm
483 %1 = lshr i64 %x, 33
484 %2 = lshr i64 %y, 33
485 %result = urem i64 %1, %2
486 store i64 %result, ptr addrspace(1) %out
487 ret void
488 }
490 define amdgpu_kernel void @s_test_urem31_v2i64(ptr addrspace(1) %out, <2 x i64> %x, <2 x i64> %y) {
491 ; GCN-LABEL: s_test_urem31_v2i64:
492 ; GCN: ; %bb.0:
493 ; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
494 ; GCN-NEXT: s_mov_b32 s3, 0xf000
495 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
496 ; GCN-NEXT: s_lshr_b32 s0, s13, 1
497 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0
498 ; GCN-NEXT: s_sub_i32 s1, 0, s0
499 ; GCN-NEXT: s_lshr_b32 s6, s15, 1
500 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, s6
501 ; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
502 ; GCN-NEXT: s_lshr_b32 s7, s11, 1
503 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
504 ; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
505 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
506 ; GCN-NEXT: v_mul_lo_u32 v1, s1, v0
507 ; GCN-NEXT: s_lshr_b32 s1, s9, 1
508 ; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
509 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
510 ; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
511 ; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
512 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
513 ; GCN-NEXT: v_readfirstlane_b32 s2, v0
514 ; GCN-NEXT: s_mul_i32 s2, s2, s0
515 ; GCN-NEXT: s_sub_i32 s1, s1, s2
516 ; GCN-NEXT: s_sub_i32 s2, s1, s0
517 ; GCN-NEXT: s_cmp_ge_u32 s1, s0
518 ; GCN-NEXT: s_cselect_b32 s1, s2, s1
519 ; GCN-NEXT: s_sub_i32 s2, s1, s0
520 ; GCN-NEXT: s_cmp_ge_u32 s1, s0
521 ; GCN-NEXT: s_cselect_b32 s8, s2, s1
522 ; GCN-NEXT: s_sub_i32 s0, 0, s6
523 ; GCN-NEXT: v_mul_lo_u32 v0, s0, v1
524 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
525 ; GCN-NEXT: s_mov_b32 s2, -1
526 ; GCN-NEXT: v_mul_hi_u32 v0, v1, v0
527 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
528 ; GCN-NEXT: v_mul_hi_u32 v2, s7, v0
529 ; GCN-NEXT: v_mov_b32_e32 v1, 0
530 ; GCN-NEXT: v_mov_b32_e32 v0, s8
531 ; GCN-NEXT: v_mov_b32_e32 v3, v1
532 ; GCN-NEXT: v_readfirstlane_b32 s4, v2
533 ; GCN-NEXT: s_mul_i32 s4, s4, s6
534 ; GCN-NEXT: s_sub_i32 s4, s7, s4
535 ; GCN-NEXT: s_sub_i32 s5, s4, s6
536 ; GCN-NEXT: s_cmp_ge_u32 s4, s6
537 ; GCN-NEXT: s_cselect_b32 s4, s5, s4
538 ; GCN-NEXT: s_sub_i32 s5, s4, s6
539 ; GCN-NEXT: s_cmp_ge_u32 s4, s6
540 ; GCN-NEXT: s_cselect_b32 s4, s5, s4
541 ; GCN-NEXT: v_mov_b32_e32 v2, s4
542 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
543 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
544 ; GCN-NEXT: s_endpgm
545 ;
546 ; GCN-IR-LABEL: s_test_urem31_v2i64:
547 ; GCN-IR: ; %bb.0:
548 ; GCN-IR-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
549 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
550 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
551 ; GCN-IR-NEXT: s_lshr_b32 s0, s13, 1
552 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0
553 ; GCN-IR-NEXT: s_sub_i32 s1, 0, s0
554 ; GCN-IR-NEXT: s_lshr_b32 s6, s15, 1
555 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s6
556 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
557 ; GCN-IR-NEXT: s_lshr_b32 s7, s11, 1
558 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v2
559 ; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
560 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
561 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s1, v0
562 ; GCN-IR-NEXT: s_lshr_b32 s1, s9, 1
563 ; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
564 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
565 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s1, v0
566 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
567 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1
568 ; GCN-IR-NEXT: v_readfirstlane_b32 s2, v0
569 ; GCN-IR-NEXT: s_mul_i32 s2, s2, s0
570 ; GCN-IR-NEXT: s_sub_i32 s1, s1, s2
571 ; GCN-IR-NEXT: s_sub_i32 s2, s1, s0
572 ; GCN-IR-NEXT: s_cmp_ge_u32 s1, s0
573 ; GCN-IR-NEXT: s_cselect_b32 s1, s2, s1
574 ; GCN-IR-NEXT: s_sub_i32 s2, s1, s0
575 ; GCN-IR-NEXT: s_cmp_ge_u32 s1, s0
576 ; GCN-IR-NEXT: s_cselect_b32 s8, s2, s1
577 ; GCN-IR-NEXT: s_sub_i32 s0, 0, s6
578 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s0, v1
579 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
580 ; GCN-IR-NEXT: s_mov_b32 s2, -1
581 ; GCN-IR-NEXT: v_mul_hi_u32 v0, v1, v0
582 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v1, v0
583 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s7, v0
584 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
585 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
586 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
587 ; GCN-IR-NEXT: v_readfirstlane_b32 s4, v2
588 ; GCN-IR-NEXT: s_mul_i32 s4, s4, s6
589 ; GCN-IR-NEXT: s_sub_i32 s4, s7, s4
590 ; GCN-IR-NEXT: s_sub_i32 s5, s4, s6
591 ; GCN-IR-NEXT: s_cmp_ge_u32 s4, s6
592 ; GCN-IR-NEXT: s_cselect_b32 s4, s5, s4
593 ; GCN-IR-NEXT: s_sub_i32 s5, s4, s6
594 ; GCN-IR-NEXT: s_cmp_ge_u32 s4, s6
595 ; GCN-IR-NEXT: s_cselect_b32 s4, s5, s4
596 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s4
597 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
598 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
599 ; GCN-IR-NEXT: s_endpgm
600 %1 = lshr <2 x i64> %x, <i64 33, i64 33>
601 %2 = lshr <2 x i64> %y, <i64 33, i64 33>
602 %result = urem <2 x i64> %1, %2
603 store <2 x i64> %result, ptr addrspace(1) %out
604 ret void
605 }
607 define amdgpu_kernel void @s_test_urem24_i64(ptr addrspace(1) %out, i64 %x, i64 %y) {
608 ; GCN-LABEL: s_test_urem24_i64:
609 ; GCN: ; %bb.0:
610 ; GCN-NEXT: s_load_dword s6, s[4:5], 0xe
611 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
612 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
613 ; GCN-NEXT: s_mov_b32 s2, -1
614 ; GCN-NEXT: s_lshr_b32 s4, s6, 8
615 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
616 ; GCN-NEXT: s_lshr_b32 s5, s3, 8
617 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5
618 ; GCN-NEXT: s_mov_b32 s3, 0xf000
619 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
620 ; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
621 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
622 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
623 ; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
624 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
625 ; GCN-NEXT: v_mov_b32_e32 v1, 0
626 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
627 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
628 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
629 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
630 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
631 ; GCN-NEXT: s_endpgm
632 ;
633 ; GCN-IR-LABEL: s_test_urem24_i64:
634 ; GCN-IR: ; %bb.0:
635 ; GCN-IR-NEXT: s_load_dword s6, s[4:5], 0xe
636 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
637 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
638 ; GCN-IR-NEXT: s_mov_b32 s2, -1
639 ; GCN-IR-NEXT: s_lshr_b32 s4, s6, 8
640 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
641 ; GCN-IR-NEXT: s_lshr_b32 s5, s3, 8
642 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5
643 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
644 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
645 ; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
646 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
647 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
648 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
649 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
650 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
651 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
652 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
653 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0
654 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
655 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
656 ; GCN-IR-NEXT: s_endpgm
657 %1 = lshr i64 %x, 40
658 %2 = lshr i64 %y, 40
659 %result = urem i64 %1, %2
660 store i64 %result, ptr addrspace(1) %out
661 ret void
662 }
664 define amdgpu_kernel void @s_test_urem23_64_v2i64(ptr addrspace(1) %out, <2 x i64> %x, <2 x i64> %y) {
665 ; GCN-LABEL: s_test_urem23_64_v2i64:
666 ; GCN: ; %bb.0:
667 ; GCN-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
668 ; GCN-NEXT: s_mov_b32 s3, 0xf000
669 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
670 ; GCN-NEXT: s_lshr_b32 s0, s13, 1
671 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0
672 ; GCN-NEXT: s_sub_i32 s1, 0, s0
673 ; GCN-NEXT: s_lshr_b32 s6, s15, 9
674 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, s6
675 ; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0
676 ; GCN-NEXT: s_lshr_b32 s7, s11, 9
677 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2
678 ; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
679 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
680 ; GCN-NEXT: v_mul_lo_u32 v1, s1, v0
681 ; GCN-NEXT: s_lshr_b32 s1, s9, 1
682 ; GCN-NEXT: v_mul_hi_u32 v1, v0, v1
683 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
684 ; GCN-NEXT: v_mul_hi_u32 v0, s1, v0
685 ; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
686 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
687 ; GCN-NEXT: v_readfirstlane_b32 s2, v0
688 ; GCN-NEXT: s_mul_i32 s2, s2, s0
689 ; GCN-NEXT: s_sub_i32 s1, s1, s2
690 ; GCN-NEXT: s_sub_i32 s2, s1, s0
691 ; GCN-NEXT: s_cmp_ge_u32 s1, s0
692 ; GCN-NEXT: s_cselect_b32 s1, s2, s1
693 ; GCN-NEXT: s_sub_i32 s2, s1, s0
694 ; GCN-NEXT: s_cmp_ge_u32 s1, s0
695 ; GCN-NEXT: s_cselect_b32 s8, s2, s1
696 ; GCN-NEXT: s_sub_i32 s0, 0, s6
697 ; GCN-NEXT: v_mul_lo_u32 v0, s0, v1
698 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
699 ; GCN-NEXT: s_mov_b32 s2, -1
700 ; GCN-NEXT: v_mul_hi_u32 v0, v1, v0
701 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0
702 ; GCN-NEXT: v_mul_hi_u32 v2, s7, v0
703 ; GCN-NEXT: v_mov_b32_e32 v1, 0
704 ; GCN-NEXT: v_mov_b32_e32 v0, s8
705 ; GCN-NEXT: v_mov_b32_e32 v3, v1
706 ; GCN-NEXT: v_readfirstlane_b32 s4, v2
707 ; GCN-NEXT: s_mul_i32 s4, s4, s6
708 ; GCN-NEXT: s_sub_i32 s4, s7, s4
709 ; GCN-NEXT: s_sub_i32 s5, s4, s6
710 ; GCN-NEXT: s_cmp_ge_u32 s4, s6
711 ; GCN-NEXT: s_cselect_b32 s4, s5, s4
712 ; GCN-NEXT: s_sub_i32 s5, s4, s6
713 ; GCN-NEXT: s_cmp_ge_u32 s4, s6
714 ; GCN-NEXT: s_cselect_b32 s4, s5, s4
715 ; GCN-NEXT: v_mov_b32_e32 v2, s4
716 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
717 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
718 ; GCN-NEXT: s_endpgm
719 ;
720 ; GCN-IR-LABEL: s_test_urem23_64_v2i64:
721 ; GCN-IR: ; %bb.0:
722 ; GCN-IR-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
723 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
724 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
725 ; GCN-IR-NEXT: s_lshr_b32 s0, s13, 1
726 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0
727 ; GCN-IR-NEXT: s_sub_i32 s1, 0, s0
728 ; GCN-IR-NEXT: s_lshr_b32 s6, s15, 9
729 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s6
730 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0
731 ; GCN-IR-NEXT: s_lshr_b32 s7, s11, 9
732 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v2
733 ; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
734 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0
735 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s1, v0
736 ; GCN-IR-NEXT: s_lshr_b32 s1, s9, 1
737 ; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1
738 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1
739 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s1, v0
740 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2
741 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1
742 ; GCN-IR-NEXT: v_readfirstlane_b32 s2, v0
743 ; GCN-IR-NEXT: s_mul_i32 s2, s2, s0
744 ; GCN-IR-NEXT: s_sub_i32 s1, s1, s2
745 ; GCN-IR-NEXT: s_sub_i32 s2, s1, s0
746 ; GCN-IR-NEXT: s_cmp_ge_u32 s1, s0
747 ; GCN-IR-NEXT: s_cselect_b32 s1, s2, s1
748 ; GCN-IR-NEXT: s_sub_i32 s2, s1, s0
749 ; GCN-IR-NEXT: s_cmp_ge_u32 s1, s0
750 ; GCN-IR-NEXT: s_cselect_b32 s8, s2, s1
751 ; GCN-IR-NEXT: s_sub_i32 s0, 0, s6
752 ; GCN-IR-NEXT: v_mul_lo_u32 v0, s0, v1
753 ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
754 ; GCN-IR-NEXT: s_mov_b32 s2, -1
755 ; GCN-IR-NEXT: v_mul_hi_u32 v0, v1, v0
756 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v1, v0
757 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s7, v0
758 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
759 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
760 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1
761 ; GCN-IR-NEXT: v_readfirstlane_b32 s4, v2
762 ; GCN-IR-NEXT: s_mul_i32 s4, s4, s6
763 ; GCN-IR-NEXT: s_sub_i32 s4, s7, s4
764 ; GCN-IR-NEXT: s_sub_i32 s5, s4, s6
765 ; GCN-IR-NEXT: s_cmp_ge_u32 s4, s6
766 ; GCN-IR-NEXT: s_cselect_b32 s4, s5, s4
767 ; GCN-IR-NEXT: s_sub_i32 s5, s4, s6
768 ; GCN-IR-NEXT: s_cmp_ge_u32 s4, s6
769 ; GCN-IR-NEXT: s_cselect_b32 s4, s5, s4
770 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s4
771 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
772 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
773 ; GCN-IR-NEXT: s_endpgm
774 %1 = lshr <2 x i64> %x, <i64 33, i64 41>
775 %2 = lshr <2 x i64> %y, <i64 33, i64 41>
776 %result = urem <2 x i64> %1, %2
777 store <2 x i64> %result, ptr addrspace(1) %out
778 ret void
779 }
781 define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x) {
782 ; GCN-LABEL: s_test_urem_k_num_i64:
783 ; GCN: ; %bb.0:
784 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9
785 ; GCN-NEXT: s_mov_b32 s11, 0xf000
786 ; GCN-NEXT: s_mov_b32 s10, -1
787 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
788 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6
789 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7
790 ; GCN-NEXT: s_sub_u32 s0, 0, s6
791 ; GCN-NEXT: s_subb_u32 s1, 0, s7
792 ; GCN-NEXT: s_mov_b32 s8, s4
793 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0
794 ; GCN-NEXT: v_rcp_f32_e32 v0, v0
795 ; GCN-NEXT: s_mov_b32 s9, s5
796 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
797 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
798 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
799 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0
800 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
801 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
802 ; GCN-NEXT: v_mul_lo_u32 v2, s0, v1
803 ; GCN-NEXT: v_mul_hi_u32 v3, s0, v0
804 ; GCN-NEXT: v_mul_lo_u32 v5, s1, v0
805 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v0
806 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
807 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5
808 ; GCN-NEXT: v_mul_hi_u32 v3, v0, v4
809 ; GCN-NEXT: v_mul_lo_u32 v5, v0, v2
810 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v2
811 ; GCN-NEXT: v_mul_hi_u32 v6, v1, v4
812 ; GCN-NEXT: v_mul_lo_u32 v4, v1, v4
813 ; GCN-NEXT: v_mul_hi_u32 v8, v1, v2
814 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
815 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc
816 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
817 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
818 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc
819 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc
820 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
821 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
822 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
823 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
824 ; GCN-NEXT: v_mul_lo_u32 v2, s0, v1
825 ; GCN-NEXT: v_mul_hi_u32 v3, s0, v0
826 ; GCN-NEXT: v_mul_lo_u32 v4, s1, v0
827 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
828 ; GCN-NEXT: v_mul_lo_u32 v3, s0, v0
829 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
830 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v2
831 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v3
832 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v2
833 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v3
834 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
835 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v2
836 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
837 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
838 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
839 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3
840 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc
841 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
842 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
843 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
844 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
845 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
846 ; GCN-NEXT: v_mul_lo_u32 v2, v1, 24
847 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
848 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
849 ; GCN-NEXT: v_mov_b32_e32 v3, s7
850 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
851 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc
852 ; GCN-NEXT: v_mul_lo_u32 v1, s7, v0
853 ; GCN-NEXT: v_mul_hi_u32 v2, s6, v0
854 ; GCN-NEXT: v_mul_lo_u32 v0, s6, v0
855 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2
856 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v1
857 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
858 ; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
859 ; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s6, v0
860 ; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
861 ; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s7, v5
862 ; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3]
863 ; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s6, v4
864 ; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
865 ; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3]
866 ; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s7, v5
867 ; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s6, v4
868 ; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3]
869 ; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
870 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
871 ; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6
872 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
873 ; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1]
874 ; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
875 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
876 ; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1]
877 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
878 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s7, v1
879 ; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
880 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
881 ; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
882 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
883 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
884 ; GCN-NEXT: s_endpgm
885 ;
886 ; GCN-IR-LABEL: s_test_urem_k_num_i64:
887 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
888 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
889 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
890 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
891 ; GCN-IR-NEXT: s_flbit_i32_b64 s12, s[2:3]
892 ; GCN-IR-NEXT: s_add_u32 s8, s12, 0xffffffc5
893 ; GCN-IR-NEXT: s_addc_u32 s9, 0, -1
894 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[2:3], 0
895 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[10:11], s[8:9], 63
896 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[8:9], 63
897 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[6:7], s[10:11]
898 ; GCN-IR-NEXT: s_and_b64 s[6:7], s[10:11], exec
899 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, 24
900 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[14:15]
901 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[10:11]
902 ; GCN-IR-NEXT: s_mov_b32 s7, 0
903 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_5
904 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
905 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
906 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
907 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], 0
908 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
909 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7]
910 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], 24, s8
911 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_4
912 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
913 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], 24, s10
914 ; GCN-IR-NEXT: s_add_u32 s14, s2, -1
915 ; GCN-IR-NEXT: s_addc_u32 s15, s3, -1
916 ; GCN-IR-NEXT: s_sub_u32 s8, 58, s12
917 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
918 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
919 ; GCN-IR-NEXT: s_mov_b32 s5, 0
920 ; GCN-IR-NEXT: .LBB6_3: ; %udiv-do-while
921 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
922 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
923 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
924 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
925 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]
926 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7]
927 ; GCN-IR-NEXT: s_sub_u32 s4, s14, s10
928 ; GCN-IR-NEXT: s_subb_u32 s4, s15, s11
929 ; GCN-IR-NEXT: s_ashr_i32 s12, s4, 31
930 ; GCN-IR-NEXT: s_mov_b32 s13, s12
931 ; GCN-IR-NEXT: s_and_b32 s4, s12, 1
932 ; GCN-IR-NEXT: s_and_b64 s[12:13], s[12:13], s[2:3]
933 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s12
934 ; GCN-IR-NEXT: s_subb_u32 s11, s11, s13
935 ; GCN-IR-NEXT: s_add_u32 s8, s8, 1
936 ; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
937 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[16:17], s[8:9], 0
938 ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[4:5]
939 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
940 ; GCN-IR-NEXT: s_cbranch_vccz .LBB6_3
941 ; GCN-IR-NEXT: .LBB6_4: ; %Flow6
942 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
943 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7]
944 ; GCN-IR-NEXT: .LBB6_5: ; %udiv-end
945 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
946 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0
947 ; GCN-IR-NEXT: s_mov_b32 s8, s0
948 ; GCN-IR-NEXT: s_mul_i32 s0, s2, s7
949 ; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
950 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v0
951 ; GCN-IR-NEXT: s_mul_i32 s0, s3, s6
952 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0
953 ; GCN-IR-NEXT: s_mul_i32 s0, s2, s6
954 ; GCN-IR-NEXT: v_sub_i32_e64 v0, vcc, 24, s0
955 ; GCN-IR-NEXT: s_mov_b32 s10, -1
956 ; GCN-IR-NEXT: s_mov_b32 s9, s1
957 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
958 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
959 ; GCN-IR-NEXT: s_endpgm
960 %result = urem i64 24, %x
961 store i64 %result, ptr addrspace(1) %out
962 ret void
963 }
965 define amdgpu_kernel void @s_test_urem_k_den_i64(ptr addrspace(1) %out, i64 %x) {
966 ; GCN-LABEL: s_test_urem_k_den_i64:
967 ; GCN: ; %bb.0:
968 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
969 ; GCN-NEXT: v_mov_b32_e32 v2, 0xaaaaaaab
970 ; GCN-NEXT: v_mov_b32_e32 v0, 0xaaaaaaaa
971 ; GCN-NEXT: s_mov_b32 s7, 0xf000
972 ; GCN-NEXT: s_mov_b32 s6, -1
973 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
974 ; GCN-NEXT: v_mul_hi_u32 v3, s2, v2
975 ; GCN-NEXT: v_mul_hi_u32 v2, s3, v2
976 ; GCN-NEXT: v_mul_hi_u32 v1, s2, v0
977 ; GCN-NEXT: s_mul_i32 s5, s3, 0xaaaaaaab
978 ; GCN-NEXT: v_add_i32_e32 v3, vcc, s5, v3
979 ; GCN-NEXT: s_mov_b32 s4, s0
980 ; GCN-NEXT: s_mul_i32 s0, s2, 0xaaaaaaaa
981 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
982 ; GCN-NEXT: v_add_i32_e32 v3, vcc, s0, v3
983 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
984 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
985 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
986 ; GCN-NEXT: s_mul_i32 s0, s3, 0xaaaaaaaa
987 ; GCN-NEXT: v_addc_u32_e64 v2, s[8:9], 0, 0, vcc
988 ; GCN-NEXT: v_add_i32_e32 v1, vcc, s0, v1
989 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v0, v2, vcc
990 ; GCN-NEXT: v_alignbit_b32 v1, v0, v1, 4
991 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 4, v0
992 ; GCN-NEXT: v_mul_hi_u32 v2, v1, 24
993 ; GCN-NEXT: v_mul_lo_u32 v0, v0, 24
994 ; GCN-NEXT: v_mul_lo_u32 v1, v1, 24
995 ; GCN-NEXT: v_mov_b32_e32 v3, s3
996 ; GCN-NEXT: s_mov_b32 s5, s1
997 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v0, v2
998 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v1
999 ; GCN-NEXT: v_subb_u32_e32 v1, vcc, v3, v2, vcc
1000 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1001 ; GCN-NEXT: s_endpgm
1002 ;
1003 ; GCN-IR-LABEL: s_test_urem_k_den_i64:
1004 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1005 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1006 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1007 ; GCN-IR-NEXT: s_flbit_i32_b64 s12, s[2:3]
1008 ; GCN-IR-NEXT: s_sub_u32 s8, 59, s12
1009 ; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
1010 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], s[2:3], 0
1011 ; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[6:7], s[8:9], 63
1012 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[8:9], 63
1013 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
1014 ; GCN-IR-NEXT: s_and_b64 s[6:7], s[4:5], exec
1015 ; GCN-IR-NEXT: s_cselect_b32 s7, 0, s3
1016 ; GCN-IR-NEXT: s_cselect_b32 s6, 0, s2
1017 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], s[10:11]
1018 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[4:5]
1019 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
1020 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5
1021 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1022 ; GCN-IR-NEXT: s_add_u32 s10, s8, 1
1023 ; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
1024 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[6:7], s[10:11], 0
1025 ; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
1026 ; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[6:7]
1027 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s8
1028 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4
1029 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1030 ; GCN-IR-NEXT: s_lshr_b64 s[10:11], s[2:3], s10
1031 ; GCN-IR-NEXT: s_add_u32 s8, s12, 0xffffffc4
1032 ; GCN-IR-NEXT: s_addc_u32 s9, 0, -1
1033 ; GCN-IR-NEXT: s_mov_b64 s[12:13], 0
1034 ; GCN-IR-NEXT: s_mov_b32 s5, 0
1035 ; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while
1036 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1037 ; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
1038 ; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
1039 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
1040 ; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]
1041 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[12:13], s[6:7]
1042 ; GCN-IR-NEXT: s_sub_u32 s4, 23, s10
1043 ; GCN-IR-NEXT: s_subb_u32 s4, 0, s11
1044 ; GCN-IR-NEXT: s_ashr_i32 s12, s4, 31
1045 ; GCN-IR-NEXT: s_and_b32 s4, s12, 1
1046 ; GCN-IR-NEXT: s_and_b32 s12, s12, 24
1047 ; GCN-IR-NEXT: s_sub_u32 s10, s10, s12
1048 ; GCN-IR-NEXT: s_subb_u32 s11, s11, 0
1049 ; GCN-IR-NEXT: s_add_u32 s8, s8, 1
1050 ; GCN-IR-NEXT: s_addc_u32 s9, s9, 0
1051 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[14:15], s[8:9], 0
1052 ; GCN-IR-NEXT: s_mov_b64 s[12:13], s[4:5]
1053 ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[14:15]
1054 ; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3
1055 ; GCN-IR-NEXT: .LBB7_4: ; %Flow6
1056 ; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
1057 ; GCN-IR-NEXT: s_or_b64 s[6:7], s[4:5], s[6:7]
1058 ; GCN-IR-NEXT: .LBB7_5: ; %udiv-end
1059 ; GCN-IR-NEXT: v_mul_hi_u32 v0, s6, 24
1060 ; GCN-IR-NEXT: s_mov_b32 s8, s0
1061 ; GCN-IR-NEXT: s_mul_i32 s0, s7, 24
1062 ; GCN-IR-NEXT: v_mov_b32_e32 v2, s3
1063 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, s0, v0
1064 ; GCN-IR-NEXT: s_mul_i32 s0, s6, 24
1065 ; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
1066 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
1067 ; GCN-IR-NEXT: s_mov_b32 s11, 0xf000
1068 ; GCN-IR-NEXT: s_mov_b32 s10, -1
1069 ; GCN-IR-NEXT: s_mov_b32 s9, s1
1070 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc
1071 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
1072 ; GCN-IR-NEXT: s_endpgm
1073 %result = urem i64 %x, 24
1074 store i64 %result, ptr addrspace(1) %out
1075 ret void
1076 }
1078 ; FIXME: Constant bus violation
1079 ; define i64 @v_test_urem_k_num_i64(i64 %x) {
1080 ; %result = urem i64 24, %x
1081 ; ret i64 %result
1082 ; }
1084 define i64 @v_test_urem_pow2_k_num_i64(i64 %x) {
1085 ; GCN-LABEL: v_test_urem_pow2_k_num_i64:
1086 ; GCN: ; %bb.0:
1087 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1088 ; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0
1089 ; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1
1090 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
1091 ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc
1092 ; GCN-NEXT: v_madmk_f32 v2, v3, 0x4f800000, v2
1093 ; GCN-NEXT: v_rcp_f32_e32 v2, v2
1094 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
1095 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
1096 ; GCN-NEXT: v_trunc_f32_e32 v3, v3
1097 ; GCN-NEXT: v_madmk_f32 v2, v3, 0xcf800000, v2
1098 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
1099 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
1100 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
1101 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
1102 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v2
1103 ; GCN-NEXT: v_mul_lo_u32 v9, v4, v2
1104 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
1105 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
1106 ; GCN-NEXT: v_mul_hi_u32 v7, v2, v9
1107 ; GCN-NEXT: v_mul_lo_u32 v8, v2, v6
1108 ; GCN-NEXT: v_mul_hi_u32 v10, v2, v6
1109 ; GCN-NEXT: v_mul_hi_u32 v11, v3, v6
1110 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
1111 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8
1112 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v10, vcc
1113 ; GCN-NEXT: v_mul_lo_u32 v10, v3, v9
1114 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v9
1115 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
1116 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v9, vcc
1117 ; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v11, vcc
1118 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
1119 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
1120 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
1121 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
1122 ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
1123 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
1124 ; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
1125 ; GCN-NEXT: v_mul_lo_u32 v4, v4, v2
1126 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
1127 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
1128 ; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
1129 ; GCN-NEXT: v_mul_hi_u32 v9, v2, v4
1130 ; GCN-NEXT: v_mul_hi_u32 v10, v2, v5
1131 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v4
1132 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
1133 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v5
1134 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
1135 ; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
1136 ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
1137 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
1138 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
1139 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
1140 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
1141 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
1142 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
1143 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v3, v5, vcc
1144 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
1145 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v2
1146 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
1147 ; GCN-NEXT: v_mul_lo_u32 v2, v0, v2
1148 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
1149 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
1150 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0x8000, v2
1151 ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
1152 ; GCN-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v0
1153 ; GCN-NEXT: v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5]
1154 ; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v6, v1
1155 ; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
1156 ; GCN-NEXT: v_cmp_ge_u32_e64 s[6:7], v5, v0
1157 ; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[6:7]
1158 ; GCN-NEXT: v_cmp_eq_u32_e64 s[6:7], v6, v1
1159 ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, s[4:5]
1160 ; GCN-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[6:7]
1161 ; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v5, v0
1162 ; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
1163 ; GCN-NEXT: v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
1164 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
1165 ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
1166 ; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
1167 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0
1168 ; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
1169 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v3, v1
1170 ; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
1171 ; GCN-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[4:5]
1172 ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
1173 ; GCN-NEXT: v_cndmask_b32_e64 v1, v6, v4, s[4:5]
1174 ; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
1175 ; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
1176 ; GCN-NEXT: s_setpc_b64 s[30:31]
1177 ;
1178 ; GCN-IR-LABEL: v_test_urem_pow2_k_num_i64:
1179 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1180 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1181 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
1182 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
1183 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
1184 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
1185 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 0xffffffd0, v10
1186 ; GCN-IR-NEXT: v_addc_u32_e64 v3, s[6:7], 0, -1, vcc
1187 ; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
1188 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[2:3]
1189 ; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[6:7], 63, v[2:3]
1190 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0x8000
1191 ; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
1192 ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v4, 0, s[4:5]
1193 ; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
1194 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1195 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
1196 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1197 ; GCN-IR-NEXT: s_cbranch_execz .LBB8_6
1198 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1199 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
1200 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
1201 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
1202 ; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
1203 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
1204 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[4:5], v2
1205 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1206 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1207 ; GCN-IR-NEXT: s_and_saveexec_b64 s[8:9], vcc
1208 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
1209 ; GCN-IR-NEXT: s_cbranch_execz .LBB8_5
1210 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1211 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
1212 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
1213 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v6
1214 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v10
1215 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
1216 ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[4:5], 0, 0, vcc
1217 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1218 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
1219 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1220 ; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
1221 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1222 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
1223 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
1224 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
1225 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1226 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
1227 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
1228 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
1229 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
1230 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
1231 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
1232 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
1233 ; GCN-IR-NEXT: v_and_b32_e32 v11, v10, v1
1234 ; GCN-IR-NEXT: v_and_b32_e32 v10, v10, v0
1235 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
1236 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1237 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
1238 ; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v11, s[4:5]
1239 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
1240 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
1241 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
1242 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
1243 ; GCN-IR-NEXT: s_cbranch_execnz .LBB8_3
1244 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1245 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1246 ; GCN-IR-NEXT: .LBB8_5: ; %Flow4
1247 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1248 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1249 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
1250 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
1251 ; GCN-IR-NEXT: .LBB8_6: ; %Flow5
1252 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1253 ; GCN-IR-NEXT: v_mul_lo_u32 v2, v0, v5
1254 ; GCN-IR-NEXT: v_mul_hi_u32 v3, v0, v4
1255 ; GCN-IR-NEXT: v_mul_lo_u32 v1, v1, v4
1256 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, v4
1257 ; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v3, v2
1258 ; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, v2, v1
1259 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
1260 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
1261 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1262 %result = urem i64 32768, %x
1263 ret i64 %result
1264 }
1266 define i64 @v_test_urem_pow2_k_den_i64(i64 %x) {
1267 ; GCN-LABEL: v_test_urem_pow2_k_den_i64:
1268 ; GCN: ; %bb.0:
1269 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1270 ; GCN-NEXT: v_and_b32_e32 v0, 0x7fff, v0
1271 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1272 ; GCN-NEXT: s_setpc_b64 s[30:31]
1273 ;
1274 ; GCN-IR-LABEL: v_test_urem_pow2_k_den_i64:
1275 ; GCN-IR: ; %bb.0: ; %_udiv-special-cases
1276 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1277 ; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
1278 ; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
1279 ; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
1280 ; GCN-IR-NEXT: v_min_u32_e32 v10, v2, v3
1281 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 48, v10
1282 ; GCN-IR-NEXT: v_subb_u32_e64 v3, s[4:5], 0, 0, s[4:5]
1283 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
1284 ; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[2:3]
1285 ; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
1286 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[2:3]
1287 ; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
1288 ; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v1, 0, s[4:5]
1289 ; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v0, 0, s[4:5]
1290 ; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
1291 ; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
1292 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_6
1293 ; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
1294 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v2
1295 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v3, vcc
1296 ; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v2
1297 ; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[6:7]
1298 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
1299 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
1300 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1301 ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
1302 ; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
1303 ; GCN-IR-NEXT: s_cbranch_execz .LBB9_5
1304 ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
1305 ; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v6
1306 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v10
1307 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
1308 ; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
1309 ; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
1310 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
1311 ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
1312 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
1313 ; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
1314 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
1315 ; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
1316 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
1317 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
1318 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8
1319 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1320 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc
1321 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 1, v6
1322 ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
1323 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
1324 ; GCN-IR-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
1325 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
1326 ; GCN-IR-NEXT: v_and_b32_e32 v10, 0x8000, v10
1327 ; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[6:7]
1328 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
1329 ; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v10
1330 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
1331 ; GCN-IR-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
1332 ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
1333 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
1334 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
1335 ; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3
1336 ; GCN-IR-NEXT: ; %bb.4: ; %Flow
1337 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
1338 ; GCN-IR-NEXT: .LBB9_5: ; %Flow4
1339 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
1340 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
1341 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
1342 ; GCN-IR-NEXT: v_or_b32_e32 v4, v4, v2
1343 ; GCN-IR-NEXT: .LBB9_6: ; %Flow5
1344 ; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
1345 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[4:5], 15
1346 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
1347 ; GCN-IR-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc
1348 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1349 %result = urem i64 %x, 32768
1350 ret i64 %result
1351 }
1353 define amdgpu_kernel void @s_test_urem24_k_num_i64(ptr addrspace(1) %out, i64 %x) {
1354 ; GCN-LABEL: s_test_urem24_k_num_i64:
1355 ; GCN: ; %bb.0:
1356 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1357 ; GCN-NEXT: s_mov_b32 s5, 0x41c00000
1358 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1359 ; GCN-NEXT: s_mov_b32 s2, -1
1360 ; GCN-NEXT: s_lshr_b32 s4, s3, 8
1361 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
1362 ; GCN-NEXT: s_mov_b32 s3, 0xf000
1363 ; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
1364 ; GCN-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
1365 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
1366 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
1367 ; GCN-NEXT: v_mad_f32 v1, -v1, v0, s5
1368 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1369 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1370 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1371 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
1372 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
1373 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1374 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1375 ; GCN-NEXT: s_endpgm
1376 ;
1377 ; GCN-IR-LABEL: s_test_urem24_k_num_i64:
1378 ; GCN-IR: ; %bb.0:
1379 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1380 ; GCN-IR-NEXT: s_mov_b32 s5, 0x41c00000
1381 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1382 ; GCN-IR-NEXT: s_mov_b32 s2, -1
1383 ; GCN-IR-NEXT: s_lshr_b32 s4, s3, 8
1384 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
1385 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
1386 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
1387 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x41c00000, v1
1388 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1389 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
1390 ; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s5
1391 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
1392 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1393 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1394 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
1395 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
1396 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1397 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
1398 ; GCN-IR-NEXT: s_endpgm
1399 %x.shr = lshr i64 %x, 40
1400 %result = urem i64 24, %x.shr
1401 store i64 %result, ptr addrspace(1) %out
1402 ret void
1403 }
1405 define amdgpu_kernel void @s_test_urem24_k_den_i64(ptr addrspace(1) %out, i64 %x) {
1406 ; GCN-LABEL: s_test_urem24_k_den_i64:
1407 ; GCN: ; %bb.0:
1408 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1409 ; GCN-NEXT: s_movk_i32 s4, 0x5b7f
1410 ; GCN-NEXT: s_mov_b32 s7, 0xf000
1411 ; GCN-NEXT: s_mov_b32 s6, -1
1412 ; GCN-NEXT: s_waitcnt lgkmcnt(0)
1413 ; GCN-NEXT: s_lshr_b32 s2, s3, 8
1414 ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
1415 ; GCN-NEXT: s_mov_b32 s3, 0x46b6fe00
1416 ; GCN-NEXT: s_mov_b32 s5, s1
1417 ; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
1418 ; GCN-NEXT: v_trunc_f32_e32 v1, v1
1419 ; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
1420 ; GCN-NEXT: v_mad_f32 v0, -v1, s3, v0
1421 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s3
1422 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1423 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1424 ; GCN-NEXT: v_mul_lo_u32 v0, v0, s4
1425 ; GCN-NEXT: s_mov_b32 s4, s0
1426 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
1427 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1428 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1429 ; GCN-NEXT: s_endpgm
1430 ;
1431 ; GCN-IR-LABEL: s_test_urem24_k_den_i64:
1432 ; GCN-IR: ; %bb.0:
1433 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
1434 ; GCN-IR-NEXT: s_movk_i32 s4, 0x5b7f
1435 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
1436 ; GCN-IR-NEXT: s_mov_b32 s6, -1
1437 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
1438 ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
1439 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
1440 ; GCN-IR-NEXT: s_mov_b32 s3, 0x46b6fe00
1441 ; GCN-IR-NEXT: s_mov_b32 s5, s1
1442 ; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
1443 ; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
1444 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
1445 ; GCN-IR-NEXT: v_mad_f32 v0, -v1, s3, v0
1446 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s3
1447 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1448 ; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
1449 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4
1450 ; GCN-IR-NEXT: s_mov_b32 s4, s0
1451 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s2, v0
1452 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1453 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
1454 ; GCN-IR-NEXT: s_endpgm
1455 %x.shr = lshr i64 %x, 40
1456 %result = urem i64 %x.shr, 23423
1457 store i64 %result, ptr addrspace(1) %out
1458 ret void
1459 }
1461 define i64 @v_test_urem24_k_num_i64(i64 %x) {
1462 ; GCN-LABEL: v_test_urem24_k_num_i64:
1463 ; GCN: ; %bb.0:
1464 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1465 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1466 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
1467 ; GCN-NEXT: s_mov_b32 s4, 0x41c00000
1468 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
1469 ; GCN-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
1470 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
1471 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
1472 ; GCN-NEXT: v_mad_f32 v2, -v2, v1, s4
1473 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
1474 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
1475 ; GCN-NEXT: v_mul_lo_u32 v0, v1, v0
1476 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1477 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
1478 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1479 ; GCN-NEXT: s_setpc_b64 s[30:31]
1480 ;
1481 ; GCN-IR-LABEL: v_test_urem24_k_num_i64:
1482 ; GCN-IR: ; %bb.0:
1483 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1484 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1485 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
1486 ; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
1487 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
1488 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x41c00000, v2
1489 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
1490 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
1491 ; GCN-IR-NEXT: v_mad_f32 v2, -v2, v1, s4
1492 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
1493 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
1494 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0
1495 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1496 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 24, v0
1497 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1498 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1499 %x.shr = lshr i64 %x, 40
1500 %result = urem i64 24, %x.shr
1501 ret i64 %result
1502 }
1504 define i64 @v_test_urem24_pow2_k_num_i64(i64 %x) {
1505 ; GCN-LABEL: v_test_urem24_pow2_k_num_i64:
1506 ; GCN: ; %bb.0:
1507 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1508 ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1509 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
1510 ; GCN-NEXT: s_mov_b32 s4, 0x47000000
1511 ; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v1
1512 ; GCN-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
1513 ; GCN-NEXT: v_trunc_f32_e32 v2, v2
1514 ; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
1515 ; GCN-NEXT: v_mad_f32 v2, -v2, v1, s4
1516 ; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
1517 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
1518 ; GCN-NEXT: v_mul_lo_u32 v0, v1, v0
1519 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1520 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
1521 ; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1522 ; GCN-NEXT: s_setpc_b64 s[30:31]
1523 ;
1524 ; GCN-IR-LABEL: v_test_urem24_pow2_k_num_i64:
1525 ; GCN-IR: ; %bb.0:
1526 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1527 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1528 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
1529 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
1530 ; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v1
1531 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x47000000, v2
1532 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
1533 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
1534 ; GCN-IR-NEXT: v_mad_f32 v2, -v2, v1, s4
1535 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v1
1536 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
1537 ; GCN-IR-NEXT: v_mul_lo_u32 v0, v1, v0
1538 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1539 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 0x8000, v0
1540 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1541 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1542 %x.shr = lshr i64 %x, 40
1543 %result = urem i64 32768, %x.shr
1544 ret i64 %result
1545 }
1547 define i64 @v_test_urem24_pow2_k_den_i64(i64 %x) {
1548 ; GCN-LABEL: v_test_urem24_pow2_k_den_i64:
1549 ; GCN: ; %bb.0:
1550 ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1551 ; GCN-NEXT: v_bfe_u32 v0, v1, 8, 15
1552 ; GCN-NEXT: v_mov_b32_e32 v1, 0
1553 ; GCN-NEXT: s_setpc_b64 s[30:31]
1554 ;
1555 ; GCN-IR-LABEL: v_test_urem24_pow2_k_den_i64:
1556 ; GCN-IR: ; %bb.0:
1557 ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1558 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
1559 ; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v0
1560 ; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
1561 ; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x38000000, v1
1562 ; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
1563 ; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
1564 ; GCN-IR-NEXT: v_mad_f32 v1, -v2, s4, v1
1565 ; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, s4
1566 ; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc
1567 ; GCN-IR-NEXT: v_lshlrev_b32_e32 v1, 15, v1
1568 ; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
1569 ; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
1570 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
1571 ; GCN-IR-NEXT: s_setpc_b64 s[30:31]
1572 %x.shr = lshr i64 %x, 40
1573 %result = urem i64 %x.shr, 32768
1574 ret i64 %result
1575 }