| blob | ee16dad2d7d11c53a01ccdc799fa77d2ac7b363f |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs | FileCheck %s --check-prefix=SI
3 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=VI
4 ; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=GFX11
6 define amdgpu_kernel void @madak_f16(
7 ; SI-LABEL: madak_f16:
8 ; SI: ; %bb.0: ; %entry
9 ; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
10 ; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
11 ; SI-NEXT: s_mov_b32 s7, 0xf000
12 ; SI-NEXT: s_mov_b32 s6, -1
13 ; SI-NEXT: s_mov_b32 s14, s6
14 ; SI-NEXT: s_waitcnt lgkmcnt(0)
15 ; SI-NEXT: s_mov_b32 s12, s2
16 ; SI-NEXT: s_mov_b32 s13, s3
17 ; SI-NEXT: s_mov_b32 s15, s7
18 ; SI-NEXT: s_mov_b32 s10, s6
19 ; SI-NEXT: s_mov_b32 s11, s7
20 ; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
21 ; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
22 ; SI-NEXT: s_mov_b32 s4, s0
23 ; SI-NEXT: s_mov_b32 s5, s1
24 ; SI-NEXT: s_waitcnt vmcnt(1)
25 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
26 ; SI-NEXT: s_waitcnt vmcnt(0)
27 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
28 ; SI-NEXT: v_madak_f32 v0, v0, v1, 0x41200000
29 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
30 ; SI-NEXT: buffer_store_short v0, off, s[4:7], 0
31 ; SI-NEXT: s_endpgm
32 ;
33 ; VI-LABEL: madak_f16:
34 ; VI: ; %bb.0: ; %entry
35 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
36 ; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x34
37 ; VI-NEXT: s_mov_b32 s7, 0xf000
38 ; VI-NEXT: s_mov_b32 s6, -1
39 ; VI-NEXT: s_mov_b32 s14, s6
40 ; VI-NEXT: s_waitcnt lgkmcnt(0)
41 ; VI-NEXT: s_mov_b32 s12, s2
42 ; VI-NEXT: s_mov_b32 s13, s3
43 ; VI-NEXT: s_mov_b32 s15, s7
44 ; VI-NEXT: s_mov_b32 s10, s6
45 ; VI-NEXT: s_mov_b32 s11, s7
46 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0
47 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0
48 ; VI-NEXT: s_mov_b32 s4, s0
49 ; VI-NEXT: s_mov_b32 s5, s1
50 ; VI-NEXT: s_waitcnt vmcnt(0)
51 ; VI-NEXT: v_madak_f16 v0, v0, v1, 0x4900
52 ; VI-NEXT: buffer_store_short v0, off, s[4:7], 0
53 ; VI-NEXT: s_endpgm
54 ;
55 ; GFX11-LABEL: madak_f16:
56 ; GFX11: ; %bb.0: ; %entry
57 ; GFX11-NEXT: s_clause 0x1
58 ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
59 ; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
60 ; GFX11-NEXT: s_mov_b32 s10, -1
61 ; GFX11-NEXT: s_mov_b32 s11, 0x31016000
62 ; GFX11-NEXT: s_mov_b32 s14, s10
63 ; GFX11-NEXT: s_mov_b32 s15, s11
64 ; GFX11-NEXT: s_mov_b32 s6, s10
65 ; GFX11-NEXT: s_mov_b32 s7, s11
66 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
67 ; GFX11-NEXT: s_mov_b32 s12, s2
68 ; GFX11-NEXT: s_mov_b32 s13, s3
69 ; GFX11-NEXT: buffer_load_u16 v0, off, s[12:15], 0
70 ; GFX11-NEXT: buffer_load_u16 v1, off, s[4:7], 0
71 ; GFX11-NEXT: s_mov_b32 s8, s0
72 ; GFX11-NEXT: s_mov_b32 s9, s1
73 ; GFX11-NEXT: s_waitcnt vmcnt(0)
74 ; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1
75 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
76 ; GFX11-NEXT: v_add_f16_e32 v0, 0x4900, v0
77 ; GFX11-NEXT: buffer_store_b16 v0, off, s[8:11], 0
78 ; GFX11-NEXT: s_endpgm
79 ptr addrspace(1) %r,
80 ptr addrspace(1) %a,
81 ptr addrspace(1) %b) #0 {
82 entry:
83 %a.val = load half, ptr addrspace(1) %a
84 %b.val = load half, ptr addrspace(1) %b
86 %t.val = fmul half %a.val, %b.val
87 %r.val = fadd half %t.val, 10.0
89 store half %r.val, ptr addrspace(1) %r
90 ret void
91 }
93 define amdgpu_kernel void @madak_f16_use_2(
94 ; SI-LABEL: madak_f16_use_2:
95 ; SI: ; %bb.0: ; %entry
96 ; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x9
97 ; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x11
98 ; SI-NEXT: s_mov_b32 s3, 0xf000
99 ; SI-NEXT: s_mov_b32 s2, -1
100 ; SI-NEXT: s_mov_b32 s18, s2
101 ; SI-NEXT: s_waitcnt lgkmcnt(0)
102 ; SI-NEXT: s_mov_b32 s16, s12
103 ; SI-NEXT: s_mov_b32 s17, s13
104 ; SI-NEXT: s_mov_b32 s19, s3
105 ; SI-NEXT: s_mov_b32 s12, s14
106 ; SI-NEXT: s_mov_b32 s13, s15
107 ; SI-NEXT: s_mov_b32 s14, s2
108 ; SI-NEXT: s_mov_b32 s15, s3
109 ; SI-NEXT: s_mov_b32 s6, s2
110 ; SI-NEXT: s_mov_b32 s7, s3
111 ; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 glc
112 ; SI-NEXT: s_waitcnt vmcnt(0)
113 ; SI-NEXT: buffer_load_ushort v1, off, s[12:15], 0 glc
114 ; SI-NEXT: s_waitcnt vmcnt(0)
115 ; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
116 ; SI-NEXT: s_waitcnt vmcnt(0)
117 ; SI-NEXT: v_mov_b32_e32 v3, 0x41200000
118 ; SI-NEXT: s_mov_b32 s0, s8
119 ; SI-NEXT: s_mov_b32 s1, s9
120 ; SI-NEXT: s_mov_b32 s4, s10
121 ; SI-NEXT: s_mov_b32 s5, s11
122 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
123 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
124 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
125 ; SI-NEXT: v_madak_f32 v1, v0, v1, 0x41200000
126 ; SI-NEXT: v_mac_f32_e32 v3, v0, v2
127 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
128 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
129 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
130 ; SI-NEXT: buffer_store_short v1, off, s[4:7], 0
131 ; SI-NEXT: s_endpgm
132 ;
133 ; VI-LABEL: madak_f16_use_2:
134 ; VI: ; %bb.0: ; %entry
135 ; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
136 ; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x44
137 ; VI-NEXT: s_mov_b32 s3, 0xf000
138 ; VI-NEXT: s_mov_b32 s2, -1
139 ; VI-NEXT: s_mov_b32 s18, s2
140 ; VI-NEXT: s_waitcnt lgkmcnt(0)
141 ; VI-NEXT: s_mov_b32 s16, s12
142 ; VI-NEXT: s_mov_b32 s17, s13
143 ; VI-NEXT: s_mov_b32 s19, s3
144 ; VI-NEXT: s_mov_b32 s12, s14
145 ; VI-NEXT: s_mov_b32 s13, s15
146 ; VI-NEXT: s_mov_b32 s14, s2
147 ; VI-NEXT: s_mov_b32 s15, s3
148 ; VI-NEXT: s_mov_b32 s6, s2
149 ; VI-NEXT: s_mov_b32 s7, s3
150 ; VI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 glc
151 ; VI-NEXT: s_waitcnt vmcnt(0)
152 ; VI-NEXT: buffer_load_ushort v1, off, s[12:15], 0 glc
153 ; VI-NEXT: s_waitcnt vmcnt(0)
154 ; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
155 ; VI-NEXT: s_waitcnt vmcnt(0)
156 ; VI-NEXT: v_mov_b32_e32 v3, 0x4900
157 ; VI-NEXT: s_mov_b32 s0, s8
158 ; VI-NEXT: s_mov_b32 s1, s9
159 ; VI-NEXT: s_mov_b32 s4, s10
160 ; VI-NEXT: s_mov_b32 s5, s11
161 ; VI-NEXT: v_madak_f16 v1, v0, v1, 0x4900
162 ; VI-NEXT: v_mac_f16_e32 v3, v0, v2
163 ; VI-NEXT: buffer_store_short v1, off, s[0:3], 0
164 ; VI-NEXT: buffer_store_short v3, off, s[4:7], 0
165 ; VI-NEXT: s_endpgm
166 ;
167 ; GFX11-LABEL: madak_f16_use_2:
168 ; GFX11: ; %bb.0: ; %entry
169 ; GFX11-NEXT: s_clause 0x1
170 ; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x24
171 ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x44
172 ; GFX11-NEXT: s_mov_b32 s6, -1
173 ; GFX11-NEXT: s_mov_b32 s7, 0x31016000
174 ; GFX11-NEXT: s_mov_b32 s18, s6
175 ; GFX11-NEXT: s_mov_b32 s19, s7
176 ; GFX11-NEXT: s_mov_b32 s22, s6
177 ; GFX11-NEXT: s_mov_b32 s23, s7
178 ; GFX11-NEXT: s_mov_b32 s2, s6
179 ; GFX11-NEXT: s_mov_b32 s3, s7
180 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
181 ; GFX11-NEXT: s_mov_b32 s16, s12
182 ; GFX11-NEXT: s_mov_b32 s17, s13
183 ; GFX11-NEXT: s_mov_b32 s20, s14
184 ; GFX11-NEXT: s_mov_b32 s21, s15
185 ; GFX11-NEXT: buffer_load_u16 v0, off, s[16:19], 0 glc dlc
186 ; GFX11-NEXT: s_waitcnt vmcnt(0)
187 ; GFX11-NEXT: buffer_load_u16 v1, off, s[20:23], 0 glc dlc
188 ; GFX11-NEXT: s_waitcnt vmcnt(0)
189 ; GFX11-NEXT: buffer_load_u16 v2, off, s[0:3], 0 glc dlc
190 ; GFX11-NEXT: s_waitcnt vmcnt(0)
191 ; GFX11-NEXT: s_mov_b32 s4, s8
192 ; GFX11-NEXT: s_mov_b32 s5, s9
193 ; GFX11-NEXT: s_mov_b32 s0, s10
194 ; GFX11-NEXT: s_mov_b32 s1, s11
195 ; GFX11-NEXT: v_mul_f16_e32 v1, v0, v1
196 ; GFX11-NEXT: v_mul_f16_e32 v0, v0, v2
197 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
198 ; GFX11-NEXT: v_add_f16_e32 v1, 0x4900, v1
199 ; GFX11-NEXT: v_add_f16_e32 v0, 0x4900, v0
200 ; GFX11-NEXT: buffer_store_b16 v1, off, s[4:7], 0
201 ; GFX11-NEXT: buffer_store_b16 v0, off, s[0:3], 0
202 ; GFX11-NEXT: s_endpgm
203 ptr addrspace(1) %r0,
204 ptr addrspace(1) %r1,
205 ptr addrspace(1) %a,
206 ptr addrspace(1) %b,
207 ptr addrspace(1) %c) #0 {
208 entry:
209 %a.val = load volatile half, ptr addrspace(1) %a
210 %b.val = load volatile half, ptr addrspace(1) %b
211 %c.val = load volatile half, ptr addrspace(1) %c
213 %t0.val = fmul half %a.val, %b.val
214 %t1.val = fmul half %a.val, %c.val
215 %r0.val = fadd half %t0.val, 10.0
216 %r1.val = fadd half %t1.val, 10.0
218 store half %r0.val, ptr addrspace(1) %r0
219 store half %r1.val, ptr addrspace(1) %r1
220 ret void
221 }
223 attributes #0 = { "denormal-fp-math"="preserve-sign,preserve-sign" }