2 ; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
3 ; N=3 STMIA_UPD should have latency 2cyc and writeback latency 1cyc
5 ; CHECK: ********** MI Scheduling **********
6 ; We need second, post-ra scheduling to have STM instruction combined from single-stores
7 ; CHECK: ********** MI Scheduling **********
8 ; CHECK: schedule starting
11 ; CHECK-NEXT: Latency : 2
14 ; CHECK-SAME: Latency=1
16 define i32 @bar(i32 %v0, i32 %v1, i32 %v2, ptr %addr) {
18 store i32 %v0, ptr %addr
20 %addr.2 = getelementptr i32, ptr %addr, i32 1
21 store i32 %v1, ptr %addr.2
23 %addr.3 = getelementptr i32, ptr %addr, i32 2
24 store i32 %v2, ptr %addr.3
26 %ptr_after = getelementptr i32, ptr %addr, i32 3
27 %val = ptrtoint ptr %ptr_after to i32
29 %rv1 = mul i32 %val, %v0
30 %rv2 = mul i32 %rv1, %v1
31 %rv3 = mul i32 %rv2, %v2