| blob | a0dfba5509f9ee00f141a407805df1ca940068f9 |
1 ; RUN: llc -march=hexagon -O2 < %s -verify-machineinstrs | FileCheck %s
2 ; CHECK-NOT: vmem(r30+#-1){{ *} = v{{[0-9]+}}
3 ; CHECK-NOT: v{{[0-9]+}} = vmem(r30+#-1)
4 ; CHECK: v{{[0-9]+}} = vmux
6 target triple = "hexagon"
8 ; Function Attrs: nounwind
9 define void @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, ptr nocapture %a4, ptr nocapture %a5) #0 {
10 b0:
11 %v0 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %a3)
12 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v0)
13 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009)
14 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> undef, <16 x i32> undef)
15 %v4 = sdiv i32 %a2, 64
16 %v5 = icmp sgt i32 %a2, 63
17 br i1 %v5, label %b1, label %b6
19 b1: ; preds = %b0
20 %v8 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v3, <16 x i32> %v3)
21 br label %b2
23 b2: ; preds = %b4, %b1
24 %v9 = phi i32 [ 0, %b1 ], [ %v100, %b4 ]
25 %v10 = phi ptr [ %a0, %b1 ], [ %v87, %b4 ]
26 %v11 = phi ptr [ %a5, %b1 ], [ %v99, %b4 ]
27 %v12 = phi ptr [ %a4, %b1 ], [ %v95, %b4 ]
28 %v14 = load <16 x i32>, ptr %v10, align 64, !tbaa !0
29 br label %b3
31 b3: ; preds = %b3, %b2
32 %v15 = phi i32 [ -4, %b2 ], [ %v83, %b3 ]
33 %v16 = phi <32 x i32> [ %v8, %b2 ], [ %v78, %b3 ]
34 %v17 = phi <16 x i32> [ %v3, %b2 ], [ %v82, %b3 ]
35 %v18 = mul nsw i32 %v15, %a1
36 %v19 = getelementptr inbounds i8, ptr %v10, i32 %v18
37 %v21 = add i32 %v18, -64
38 %v22 = getelementptr inbounds i8, ptr %v10, i32 %v21
39 %v24 = load <16 x i32>, ptr %v22, align 64, !tbaa !0
40 %v25 = load <16 x i32>, ptr %v19, align 64, !tbaa !0
41 %v26 = add i32 %v18, 64
42 %v27 = getelementptr inbounds i8, ptr %v10, i32 %v26
43 %v29 = load <16 x i32>, ptr %v27, align 64, !tbaa !0
44 %v30 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v25, <16 x i32> %v14)
45 %v31 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v30, <16 x i32> %v1)
46 %v32 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v31, <16 x i32> %v3, <16 x i32> %v25)
47 %v33 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %v16, <16 x i32> %v32, i32 16843009)
48 %v34 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v31, <16 x i32> %v17, <16 x i32> %v2)
49 %v35 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v25, <16 x i32> %v24, i32 1)
50 %v36 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v29, <16 x i32> %v25, i32 1)
51 %v37 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v25, <16 x i32> %v24, i32 2)
52 %v38 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v29, <16 x i32> %v25, i32 2)
53 %v39 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v35, <16 x i32> %v14)
54 %v40 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v36, <16 x i32> %v14)
55 %v41 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v37, <16 x i32> %v14)
56 %v42 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v38, <16 x i32> %v14)
57 %v43 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v39, <16 x i32> %v1)
58 %v44 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v40, <16 x i32> %v1)
59 %v45 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v41, <16 x i32> %v1)
60 %v46 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v42, <16 x i32> %v1)
61 %v47 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v43, <16 x i32> %v3, <16 x i32> %v35)
62 %v48 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v44, <16 x i32> %v3, <16 x i32> %v36)
63 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v45, <16 x i32> %v3, <16 x i32> %v37)
64 %v50 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v46, <16 x i32> %v3, <16 x i32> %v38)
65 %v51 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v48, <16 x i32> %v47)
66 %v52 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v33, <32 x i32> %v51, i32 16843009)
67 %v53 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v50, <16 x i32> %v49)
68 %v54 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v52, <32 x i32> %v53, i32 16843009)
69 %v55 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v43, <16 x i32> %v34, <16 x i32> %v2)
70 %v56 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v44, <16 x i32> %v55, <16 x i32> %v2)
71 %v57 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v45, <16 x i32> %v56, <16 x i32> %v2)
72 %v58 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v46, <16 x i32> %v57, <16 x i32> %v2)
73 %v59 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v25, <16 x i32> %v24, i32 3)
74 %v60 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v29, <16 x i32> %v25, i32 3)
75 %v61 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v25, <16 x i32> %v24, i32 4)
76 %v62 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v29, <16 x i32> %v25, i32 4)
77 %v63 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v59, <16 x i32> %v14)
78 %v64 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v60, <16 x i32> %v14)
79 %v65 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v61, <16 x i32> %v14)
80 %v66 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v62, <16 x i32> %v14)
81 %v67 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v63, <16 x i32> %v1)
82 %v68 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v64, <16 x i32> %v1)
83 %v69 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v65, <16 x i32> %v1)
84 %v70 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v66, <16 x i32> %v1)
85 %v71 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v67, <16 x i32> %v3, <16 x i32> %v59)
86 %v72 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v68, <16 x i32> %v3, <16 x i32> %v60)
87 %v73 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v69, <16 x i32> %v3, <16 x i32> %v61)
88 %v74 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v70, <16 x i32> %v3, <16 x i32> %v62)
89 %v75 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v72, <16 x i32> %v71)
90 %v76 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v54, <32 x i32> %v75, i32 16843009)
91 %v77 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v74, <16 x i32> %v73)
92 %v78 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v76, <32 x i32> %v77, i32 16843009)
93 %v79 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v67, <16 x i32> %v58, <16 x i32> %v2)
94 %v80 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v68, <16 x i32> %v79, <16 x i32> %v2)
95 %v81 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v69, <16 x i32> %v80, <16 x i32> %v2)
96 %v82 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v70, <16 x i32> %v81, <16 x i32> %v2)
97 %v83 = add nsw i32 %v15, 1
98 %v84 = icmp eq i32 %v83, 5
99 br i1 %v84, label %b4, label %b3
101 b4: ; preds = %b3
102 %v85 = phi <16 x i32> [ %v82, %b3 ]
103 %v86 = phi <32 x i32> [ %v78, %b3 ]
104 %v87 = getelementptr inbounds i8, ptr %v10, i32 64
105 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86)
106 %v89 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v86)
107 %v90 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %v88, <16 x i32> %v89, i32 -2)
108 %v91 = tail call <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32> %v85)
109 %v92 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v90)
110 %v93 = getelementptr inbounds <16 x i32>, ptr %v12, i32 1
111 store <16 x i32> %v92, ptr %v12, align 64, !tbaa !0
112 %v94 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v90)
113 %v95 = getelementptr inbounds <16 x i32>, ptr %v12, i32 2
114 store <16 x i32> %v94, ptr %v93, align 64, !tbaa !0
115 %v96 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v91)
116 %v97 = getelementptr inbounds <16 x i32>, ptr %v11, i32 1
117 store <16 x i32> %v96, ptr %v11, align 64, !tbaa !0
118 %v98 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v91)
119 %v99 = getelementptr inbounds <16 x i32>, ptr %v11, i32 2
120 store <16 x i32> %v98, ptr %v97, align 64, !tbaa !0
121 %v100 = add nsw i32 %v9, 1
122 %v101 = icmp slt i32 %v100, %v4
123 br i1 %v101, label %b2, label %b5
125 b5: ; preds = %b4
126 br label %b6
128 b6: ; preds = %b5, %b0
129 ret void
130 }
132 ; Function Attrs: nounwind readnone
133 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
135 ; Function Attrs: nounwind readnone
136 declare i32 @llvm.hexagon.S2.vsplatrb(i32) #1
138 ; Function Attrs: nounwind readnone
139 declare <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32>, <16 x i32>) #1
141 ; Function Attrs: nounwind readnone
142 declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1
144 ; Function Attrs: nounwind readnone
145 declare <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32>, <16 x i32>) #1
147 ; Function Attrs: nounwind readnone
148 declare <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32>, <16 x i32>) #1
150 ; Function Attrs: nounwind readnone
151 declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #1
153 ; Function Attrs: nounwind readnone
154 declare <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32>, <16 x i32>, i32) #1
156 ; Function Attrs: nounwind readnone
157 declare <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1>, <16 x i32>, <16 x i32>) #1
159 ; Function Attrs: nounwind readnone
160 declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #1
162 ; Function Attrs: nounwind readnone
163 declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
165 ; Function Attrs: nounwind readnone
166 declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #1
168 ; Function Attrs: nounwind readnone
169 declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1
171 ; Function Attrs: nounwind readnone
172 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
174 ; Function Attrs: nounwind readnone
175 declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
177 ; Function Attrs: nounwind readnone
178 declare <32 x i32> @llvm.hexagon.V6.vunpackub(<16 x i32>) #1
180 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
181 attributes #1 = { nounwind readnone }
183 !0 = !{!1, !1, i64 0}
184 !1 = !{!"omnipotent char", !2, i64 0}
185 !2 = !{!"Simple C/C++ TBAA"}