| blob | 1e50b5c7940b3e7d2dc6755cb18313a0c1b99bbc |
1 ; RUN: llc -march=hexagon -enable-pipeliner=false -hexagon-vector-combine=false < %s | FileCheck %s
3 ; Test that the vsplat and vmemu are not all serialized due to chain edges
4 ; caused by the hasSideEffects flag. The exact code generation may change
5 ; due to the scheduling changes, but we shouldn't see a series of
6 ; vsplat and vmemu instructions that each occur in a single packet.
8 ; CHECK: loop0(.LBB0_[[LOOP:.]],
9 ; CHECK: .LBB0_[[LOOP]]:
10 ; CHECK: vsplat
11 ; CHECK-NEXT: vsplat
12 ; CHECK: vsplat
13 ; CHECK-NEXT: vsplat
14 ; CHECK: endloop0
16 @g0 = global [256 x i8] c"^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^00226644,,..**8888::66,,,,&&^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^22000022..4444>>::8888**..^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^<<66220000226644<<>>::^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^>><<446622000022>>", align 64
18 ; Function Attrs: nounwind
19 define void @f0(ptr noalias nocapture readonly %a0, ptr noalias nocapture readonly %a1, ptr noalias nocapture %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) #0 {
20 b0:
21 %v0 = load <16 x i32>, ptr @g0, align 64, !tbaa !0
22 %v1 = load <16 x i32>, ptr getelementptr inbounds ([256 x i8], ptr @g0, i32 0, i32 64), align 64, !tbaa !0
23 %v2 = load <16 x i32>, ptr getelementptr inbounds ([256 x i8], ptr @g0, i32 0, i32 128), align 64, !tbaa !0
24 %v3 = load <16 x i32>, ptr getelementptr inbounds ([256 x i8], ptr @g0, i32 0, i32 192), align 64, !tbaa !0
25 %v4 = icmp sgt i32 %a5, 0
26 br i1 %v4, label %b1, label %b5
28 b1: ; preds = %b0
29 %v6 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
30 %v8 = mul nsw i32 %a3, 4
31 %v9 = add i32 %v8, %a6
32 %v10 = add i32 %v9, 32
33 %v11 = add i32 %a5, -1
34 br label %b2
36 b2: ; preds = %b4, %b1
37 %v12 = phi i32 [ 0, %b1 ], [ %v59, %b4 ]
38 %v13 = phi ptr [ %a2, %b1 ], [ %v58, %b4 ]
39 %v14 = getelementptr ptr, ptr %a0, i32 %v12
40 br label %b3
42 b3: ; preds = %b3, %b2
43 %v15 = phi ptr [ %v14, %b2 ], [ %v57, %b3 ]
44 %v16 = phi i32 [ 0, %b2 ], [ %v55, %b3 ]
45 %v17 = phi ptr [ %a1, %b2 ], [ %v23, %b3 ]
46 %v18 = phi <16 x i32> [ %v6, %b2 ], [ %v54, %b3 ]
47 %v19 = load ptr, ptr %v15, align 4, !tbaa !3
48 %v20 = getelementptr inbounds i16, ptr %v19, i32 %v9
49 %v21 = getelementptr inbounds i64, ptr %v17, i32 1
50 %v22 = load i64, ptr %v17, align 8, !tbaa !0
51 %v23 = getelementptr inbounds i64, ptr %v17, i32 2
52 %v24 = load i64, ptr %v21, align 8, !tbaa !0
53 %v25 = trunc i64 %v22 to i32
54 %v26 = lshr i64 %v22, 32
55 %v27 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v25)
56 %v28 = trunc i64 %v26 to i32
57 %v29 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v28)
58 %v30 = trunc i64 %v24 to i32
59 %v31 = lshr i64 %v24, 32
60 %v32 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v30)
61 %v33 = trunc i64 %v31 to i32
62 %v34 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v33)
63 %v36 = load <16 x i32>, ptr %v20, align 4, !tbaa !0
64 %v37 = getelementptr inbounds i16, ptr %v19, i32 %v10
65 %v39 = load <16 x i32>, ptr %v37, align 4, !tbaa !0
66 %v40 = tail call <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32> %v39, <16 x i32> %v36)
67 %v41 = tail call <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32> %v40, <16 x i32> %v40)
68 %v42 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v0)
69 %v43 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v1)
70 %v44 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v2)
71 %v45 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v3)
72 %v46 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v27, <16 x i32> %v42)
73 %v47 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v29, <16 x i32> %v43)
74 %v48 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v32, <16 x i32> %v44)
75 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v34, <16 x i32> %v45)
76 %v50 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32> %v46, <16 x i32> %v46)
77 %v51 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v50, <16 x i32> %v47, <16 x i32> %v47)
78 %v52 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v51, <16 x i32> %v48, <16 x i32> %v48)
79 %v53 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v52, <16 x i32> %v49, <16 x i32> %v49)
80 %v54 = tail call <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32> %v18, <16 x i32> %v53, i32 6)
81 %v55 = add nsw i32 %v16, 1
82 %v56 = icmp eq i32 %v16, 7
83 %v57 = getelementptr ptr, ptr %v15, i32 1
84 br i1 %v56, label %b4, label %b3
86 b4: ; preds = %b3
87 %v58 = getelementptr inbounds <16 x i32>, ptr %v13, i32 1
88 store <16 x i32> %v54, ptr %v13, align 64, !tbaa !0
89 %v59 = add nsw i32 %v12, 1
90 %v60 = icmp eq i32 %v12, %v11
91 br i1 %v60, label %b5, label %b2
93 b5: ; preds = %b4, %b0
94 ret void
95 }
97 ; Function Attrs: nounwind readnone
98 declare <16 x i32> @llvm.hexagon.V6.vd0() #1
100 ; Function Attrs: nounwind readnone
101 declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
103 ; Function Attrs: nounwind readnone
104 declare <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32>, <16 x i32>) #1
106 ; Function Attrs: nounwind readnone
107 declare <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32>, <16 x i32>) #1
109 ; Function Attrs: nounwind readnone
110 declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1
112 ; Function Attrs: nounwind readnone
113 declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #1
115 ; Function Attrs: nounwind readnone
116 declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32>, <16 x i32>, <16 x i32>) #1
118 ; Function Attrs: nounwind readnone
119 declare <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32>, <16 x i32>, i32) #1
121 attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
122 attributes #1 = { nounwind readnone }
124 !0 = !{!1, !1, i64 0}
125 !1 = !{!"omnipotent char", !2, i64 0}
126 !2 = !{!"Simple C/C++ TBAA"}
127 !3 = !{!4, !4, i64 0}
128 !4 = !{!"any pointer", !1, i64 0}