llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-long-branch-reg.ll

   1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-s-branch-bits=4 -stop-after=branch-relaxation -verify-machineinstrs %s -o - | FileCheck %s
   2
   3 ; Test that long branch reserved register is serialized through
   4 ; MIR.
   5
   6 ; CHECK-LABEL: {{^}}name: uniform_long_forward_branch
   7 ; CHECK: machineFunctionInfo:
   8 ; CHECK-NEXT: explicitKernArgSize: 12
   9 ; CHECK-NEXT: maxKernArgAlign: 8
  10 ; CHECK-NEXT: ldsSize: 0
  11 ; CHECK-NEXT: gdsSize: 0
  12 ; CHECK-NEXT: dynLDSAlign: 1
  13 ; CHECK-NEXT: isEntryFunction: true
  14 ; CHECK-NEXT: isChainFunction: false
  15 ; CHECK-NEXT: noSignedZerosFPMath: false
  16 ; CHECK-NEXT: memoryBound: false
  17 ; CHECK-NEXT: waveLimiter: false
  18 ; CHECK-NEXT: hasSpilledSGPRs: false
  19 ; CHECK-NEXT: hasSpilledVGPRs: false
  20 ; CHECK-NEXT: scratchRSrcReg:  '$sgpr96_sgpr97_sgpr98_sgpr99'
  21 ; CHECK-NEXT: frameOffsetReg:  '$fp_reg'
  22 ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32'
  23 ; CHECK-NEXT: bytesInStackArgArea: 0
  24 ; CHECK-NEXT: returnsVoid:     true
  25 ; CHECK-NEXT: argumentInfo:
  26 ; CHECK-NEXT: privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
  27 ; CHECK-NEXT: kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
  28 ; CHECK-NEXT: workGroupIDX:    { reg: '$sgpr6' }
  29 ; CHECK-NEXT: privateSegmentWaveByteOffset: { reg: '$sgpr7' }
  30 ; CHECK-NEXT: workItemIDX:     { reg: '$vgpr0' }
  31 ; CHECK-NEXT: psInputAddr:     0
  32 ; CHECK-NEXT: psInputEnable:   0
  33 ; CHECK-NEXT: maxMemoryClusterDWords:   8
  34 ; CHECK-NEXT: mode:
  35 ; CHECK-NEXT: ieee:            true
  36 ; CHECK-NEXT: dx10-clamp:      true
  37 ; CHECK-NEXT: fp32-input-denormals: true
  38 ; CHECK-NEXT: fp32-output-denormals: true
  39 ; CHECK-NEXT: fp64-fp16-input-denormals: true
  40 ; CHECK-NEXT: fp64-fp16-output-denormals: true
  41 ; CHECK-NEXT: BitsOf32BitAddress: 0
  42 ; CHECK-NEXT: occupancy:       8
  43 ; CHECK-NEXT: vgprForAGPRCopy: ''
  44 ; CHECK-NEXT: sgprForEXECCopy: '$sgpr100_sgpr101'
  45 ; CHECK-NEXT: longBranchReservedReg: '$sgpr2_sgpr3'
  46 ; CHECK-NEXT: hasInitWholeWave: false
  47 ; CHECK-NEXT: body:
  48 define amdgpu_kernel void @uniform_long_forward_branch(ptr addrspace(1) %arg, i32 %arg1) #0 {
  49 bb0:
  50   %tmp = icmp ne i32 %arg1, 0
  51   br i1 %tmp, label %bb2, label %bb3
  52
  53 bb2:
  54   store volatile i32 17, ptr addrspace(1) undef
  55   br label %bb4
  56
  57 bb3:
  58   ; 32 byte asm
  59   call void asm sideeffect
  60   "v_nop_e64
  61   v_nop_e64
  62   v_nop_e64
  63   v_nop_e64", ""() #0
  64   br label %bb4
  65
  66 bb4:
  67   store volatile i32 63, ptr addrspace(1) %arg
  68   ret void
  69 }
  70
  71 attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }
  72 attributes #1 = { nounwind readnone }