| blob | 2b8129acb91fce2600519dbb70a4f5f45b8e0d20 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \
3 ; RUN: -check-prefix=MIPS
4 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \
5 ; RUN: -check-prefix=MIPS32
6 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
7 ; RUN: -check-prefix=32R2
8 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
9 ; RUN: -check-prefix=32R2
10 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
11 ; RUN: -check-prefix=32R2
12 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
13 ; RUN: -check-prefix=32R6
14 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \
15 ; RUN: -check-prefix=MIPS3
16 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \
17 ; RUN: -check-prefix=MIPS64
18 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \
19 ; RUN: -check-prefix=MIPS64
20 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
21 ; RUN: -check-prefix=MIPS64R2
22 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
23 ; RUN: -check-prefix=MIPS64R2
24 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
25 ; RUN: -check-prefix=MIPS64R2
26 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
27 ; RUN: -check-prefix=MIPS64R6
28 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
29 ; RUN: -check-prefix=MMR3
30 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
31 ; RUN: -check-prefix=MMR6
33 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
34 ; MIPS-LABEL: ashr_i1:
35 ; MIPS: # %bb.0: # %entry
36 ; MIPS-NEXT: jr $ra
37 ; MIPS-NEXT: move $2, $4
38 ;
39 ; MIPS32-LABEL: ashr_i1:
40 ; MIPS32: # %bb.0: # %entry
41 ; MIPS32-NEXT: jr $ra
42 ; MIPS32-NEXT: move $2, $4
43 ;
44 ; 32R2-LABEL: ashr_i1:
45 ; 32R2: # %bb.0: # %entry
46 ; 32R2-NEXT: jr $ra
47 ; 32R2-NEXT: move $2, $4
48 ;
49 ; 32R6-LABEL: ashr_i1:
50 ; 32R6: # %bb.0: # %entry
51 ; 32R6-NEXT: jr $ra
52 ; 32R6-NEXT: move $2, $4
53 ;
54 ; MIPS3-LABEL: ashr_i1:
55 ; MIPS3: # %bb.0: # %entry
56 ; MIPS3-NEXT: jr $ra
57 ; MIPS3-NEXT: move $2, $4
58 ;
59 ; MIPS64-LABEL: ashr_i1:
60 ; MIPS64: # %bb.0: # %entry
61 ; MIPS64-NEXT: jr $ra
62 ; MIPS64-NEXT: move $2, $4
63 ;
64 ; MIPS64R2-LABEL: ashr_i1:
65 ; MIPS64R2: # %bb.0: # %entry
66 ; MIPS64R2-NEXT: jr $ra
67 ; MIPS64R2-NEXT: move $2, $4
68 ;
69 ; MIPS64R6-LABEL: ashr_i1:
70 ; MIPS64R6: # %bb.0: # %entry
71 ; MIPS64R6-NEXT: jr $ra
72 ; MIPS64R6-NEXT: move $2, $4
73 ;
74 ; MMR3-LABEL: ashr_i1:
75 ; MMR3: # %bb.0: # %entry
76 ; MMR3-NEXT: move $2, $4
77 ; MMR3-NEXT: jrc $ra
78 ;
79 ; MMR6-LABEL: ashr_i1:
80 ; MMR6: # %bb.0: # %entry
81 ; MMR6-NEXT: move $2, $4
82 ; MMR6-NEXT: jrc $ra
83 entry:
84 %r = ashr i1 %a, %b
85 ret i1 %r
86 }
88 ; FIXME: The andi instruction is redundant.
89 define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) {
90 ; MIPS-LABEL: ashr_i8:
91 ; MIPS: # %bb.0: # %entry
92 ; MIPS-NEXT: jr $ra
93 ; MIPS-NEXT: srav $2, $4, $5
94 ;
95 ; MIPS32-LABEL: ashr_i8:
96 ; MIPS32: # %bb.0: # %entry
97 ; MIPS32-NEXT: jr $ra
98 ; MIPS32-NEXT: srav $2, $4, $5
99 ;
100 ; 32R2-LABEL: ashr_i8:
101 ; 32R2: # %bb.0: # %entry
102 ; 32R2-NEXT: jr $ra
103 ; 32R2-NEXT: srav $2, $4, $5
104 ;
105 ; 32R6-LABEL: ashr_i8:
106 ; 32R6: # %bb.0: # %entry
107 ; 32R6-NEXT: jr $ra
108 ; 32R6-NEXT: srav $2, $4, $5
109 ;
110 ; MIPS3-LABEL: ashr_i8:
111 ; MIPS3: # %bb.0: # %entry
112 ; MIPS3-NEXT: jr $ra
113 ; MIPS3-NEXT: srav $2, $4, $5
114 ;
115 ; MIPS64-LABEL: ashr_i8:
116 ; MIPS64: # %bb.0: # %entry
117 ; MIPS64-NEXT: jr $ra
118 ; MIPS64-NEXT: srav $2, $4, $5
119 ;
120 ; MIPS64R2-LABEL: ashr_i8:
121 ; MIPS64R2: # %bb.0: # %entry
122 ; MIPS64R2-NEXT: jr $ra
123 ; MIPS64R2-NEXT: srav $2, $4, $5
124 ;
125 ; MIPS64R6-LABEL: ashr_i8:
126 ; MIPS64R6: # %bb.0: # %entry
127 ; MIPS64R6-NEXT: jr $ra
128 ; MIPS64R6-NEXT: srav $2, $4, $5
129 ;
130 ; MMR3-LABEL: ashr_i8:
131 ; MMR3: # %bb.0: # %entry
132 ; MMR3-NEXT: andi16 $2, $5, 255
133 ; MMR3-NEXT: jr $ra
134 ; MMR3-NEXT: srav $2, $4, $2
135 ;
136 ; MMR6-LABEL: ashr_i8:
137 ; MMR6: # %bb.0: # %entry
138 ; MMR6-NEXT: andi16 $2, $5, 255
139 ; MMR6-NEXT: srav $2, $4, $2
140 ; MMR6-NEXT: jrc $ra
141 entry:
142 %r = ashr i8 %a, %b
143 ret i8 %r
144 }
146 ; FIXME: The andi instruction is redundant.
147 define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) {
148 ; MIPS-LABEL: ashr_i16:
149 ; MIPS: # %bb.0: # %entry
150 ; MIPS-NEXT: jr $ra
151 ; MIPS-NEXT: srav $2, $4, $5
152 ;
153 ; MIPS32-LABEL: ashr_i16:
154 ; MIPS32: # %bb.0: # %entry
155 ; MIPS32-NEXT: jr $ra
156 ; MIPS32-NEXT: srav $2, $4, $5
157 ;
158 ; 32R2-LABEL: ashr_i16:
159 ; 32R2: # %bb.0: # %entry
160 ; 32R2-NEXT: jr $ra
161 ; 32R2-NEXT: srav $2, $4, $5
162 ;
163 ; 32R6-LABEL: ashr_i16:
164 ; 32R6: # %bb.0: # %entry
165 ; 32R6-NEXT: jr $ra
166 ; 32R6-NEXT: srav $2, $4, $5
167 ;
168 ; MIPS3-LABEL: ashr_i16:
169 ; MIPS3: # %bb.0: # %entry
170 ; MIPS3-NEXT: jr $ra
171 ; MIPS3-NEXT: srav $2, $4, $5
172 ;
173 ; MIPS64-LABEL: ashr_i16:
174 ; MIPS64: # %bb.0: # %entry
175 ; MIPS64-NEXT: jr $ra
176 ; MIPS64-NEXT: srav $2, $4, $5
177 ;
178 ; MIPS64R2-LABEL: ashr_i16:
179 ; MIPS64R2: # %bb.0: # %entry
180 ; MIPS64R2-NEXT: jr $ra
181 ; MIPS64R2-NEXT: srav $2, $4, $5
182 ;
183 ; MIPS64R6-LABEL: ashr_i16:
184 ; MIPS64R6: # %bb.0: # %entry
185 ; MIPS64R6-NEXT: jr $ra
186 ; MIPS64R6-NEXT: srav $2, $4, $5
187 ;
188 ; MMR3-LABEL: ashr_i16:
189 ; MMR3: # %bb.0: # %entry
190 ; MMR3-NEXT: andi16 $2, $5, 65535
191 ; MMR3-NEXT: jr $ra
192 ; MMR3-NEXT: srav $2, $4, $2
193 ;
194 ; MMR6-LABEL: ashr_i16:
195 ; MMR6: # %bb.0: # %entry
196 ; MMR6-NEXT: andi16 $2, $5, 65535
197 ; MMR6-NEXT: srav $2, $4, $2
198 ; MMR6-NEXT: jrc $ra
199 entry:
200 %r = ashr i16 %a, %b
201 ret i16 %r
202 }
204 define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) {
205 ; MIPS-LABEL: ashr_i32:
206 ; MIPS: # %bb.0: # %entry
207 ; MIPS-NEXT: jr $ra
208 ; MIPS-NEXT: srav $2, $4, $5
209 ;
210 ; MIPS32-LABEL: ashr_i32:
211 ; MIPS32: # %bb.0: # %entry
212 ; MIPS32-NEXT: jr $ra
213 ; MIPS32-NEXT: srav $2, $4, $5
214 ;
215 ; 32R2-LABEL: ashr_i32:
216 ; 32R2: # %bb.0: # %entry
217 ; 32R2-NEXT: jr $ra
218 ; 32R2-NEXT: srav $2, $4, $5
219 ;
220 ; 32R6-LABEL: ashr_i32:
221 ; 32R6: # %bb.0: # %entry
222 ; 32R6-NEXT: jr $ra
223 ; 32R6-NEXT: srav $2, $4, $5
224 ;
225 ; MIPS3-LABEL: ashr_i32:
226 ; MIPS3: # %bb.0: # %entry
227 ; MIPS3-NEXT: jr $ra
228 ; MIPS3-NEXT: srav $2, $4, $5
229 ;
230 ; MIPS64-LABEL: ashr_i32:
231 ; MIPS64: # %bb.0: # %entry
232 ; MIPS64-NEXT: jr $ra
233 ; MIPS64-NEXT: srav $2, $4, $5
234 ;
235 ; MIPS64R2-LABEL: ashr_i32:
236 ; MIPS64R2: # %bb.0: # %entry
237 ; MIPS64R2-NEXT: jr $ra
238 ; MIPS64R2-NEXT: srav $2, $4, $5
239 ;
240 ; MIPS64R6-LABEL: ashr_i32:
241 ; MIPS64R6: # %bb.0: # %entry
242 ; MIPS64R6-NEXT: jr $ra
243 ; MIPS64R6-NEXT: srav $2, $4, $5
244 ;
245 ; MMR3-LABEL: ashr_i32:
246 ; MMR3: # %bb.0: # %entry
247 ; MMR3-NEXT: jr $ra
248 ; MMR3-NEXT: srav $2, $4, $5
249 ;
250 ; MMR6-LABEL: ashr_i32:
251 ; MMR6: # %bb.0: # %entry
252 ; MMR6-NEXT: srav $2, $4, $5
253 ; MMR6-NEXT: jrc $ra
254 entry:
255 %r = ashr i32 %a, %b
256 ret i32 %r
257 }
259 define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
260 ; MIPS-LABEL: ashr_i64:
261 ; MIPS: # %bb.0: # %entry
262 ; MIPS-NEXT: andi $1, $7, 32
263 ; MIPS-NEXT: bnez $1, $BB4_2
264 ; MIPS-NEXT: srav $3, $4, $7
265 ; MIPS-NEXT: # %bb.1: # %entry
266 ; MIPS-NEXT: srlv $1, $5, $7
267 ; MIPS-NEXT: xori $2, $7, 31
268 ; MIPS-NEXT: sll $4, $4, 1
269 ; MIPS-NEXT: sllv $2, $4, $2
270 ; MIPS-NEXT: or $1, $2, $1
271 ; MIPS-NEXT: move $2, $3
272 ; MIPS-NEXT: jr $ra
273 ; MIPS-NEXT: move $3, $1
274 ; MIPS-NEXT: $BB4_2:
275 ; MIPS-NEXT: jr $ra
276 ; MIPS-NEXT: sra $2, $4, 31
277 ;
278 ; MIPS32-LABEL: ashr_i64:
279 ; MIPS32: # %bb.0: # %entry
280 ; MIPS32-NEXT: srlv $1, $5, $7
281 ; MIPS32-NEXT: xori $2, $7, 31
282 ; MIPS32-NEXT: sll $3, $4, 1
283 ; MIPS32-NEXT: sllv $2, $3, $2
284 ; MIPS32-NEXT: or $3, $2, $1
285 ; MIPS32-NEXT: srav $2, $4, $7
286 ; MIPS32-NEXT: andi $1, $7, 32
287 ; MIPS32-NEXT: movn $3, $2, $1
288 ; MIPS32-NEXT: sra $4, $4, 31
289 ; MIPS32-NEXT: jr $ra
290 ; MIPS32-NEXT: movn $2, $4, $1
291 ;
292 ; 32R2-LABEL: ashr_i64:
293 ; 32R2: # %bb.0: # %entry
294 ; 32R2-NEXT: srlv $1, $5, $7
295 ; 32R2-NEXT: xori $2, $7, 31
296 ; 32R2-NEXT: sll $3, $4, 1
297 ; 32R2-NEXT: sllv $2, $3, $2
298 ; 32R2-NEXT: or $3, $2, $1
299 ; 32R2-NEXT: srav $2, $4, $7
300 ; 32R2-NEXT: andi $1, $7, 32
301 ; 32R2-NEXT: movn $3, $2, $1
302 ; 32R2-NEXT: sra $4, $4, 31
303 ; 32R2-NEXT: jr $ra
304 ; 32R2-NEXT: movn $2, $4, $1
305 ;
306 ; 32R6-LABEL: ashr_i64:
307 ; 32R6: # %bb.0: # %entry
308 ; 32R6-NEXT: srav $1, $4, $7
309 ; 32R6-NEXT: andi $3, $7, 32
310 ; 32R6-NEXT: seleqz $2, $1, $3
311 ; 32R6-NEXT: sra $6, $4, 31
312 ; 32R6-NEXT: selnez $6, $6, $3
313 ; 32R6-NEXT: or $2, $6, $2
314 ; 32R6-NEXT: srlv $5, $5, $7
315 ; 32R6-NEXT: xori $6, $7, 31
316 ; 32R6-NEXT: sll $4, $4, 1
317 ; 32R6-NEXT: sllv $4, $4, $6
318 ; 32R6-NEXT: or $4, $4, $5
319 ; 32R6-NEXT: seleqz $4, $4, $3
320 ; 32R6-NEXT: selnez $1, $1, $3
321 ; 32R6-NEXT: jr $ra
322 ; 32R6-NEXT: or $3, $1, $4
323 ;
324 ; MIPS3-LABEL: ashr_i64:
325 ; MIPS3: # %bb.0: # %entry
326 ; MIPS3-NEXT: jr $ra
327 ; MIPS3-NEXT: dsrav $2, $4, $5
328 ;
329 ; MIPS64-LABEL: ashr_i64:
330 ; MIPS64: # %bb.0: # %entry
331 ; MIPS64-NEXT: jr $ra
332 ; MIPS64-NEXT: dsrav $2, $4, $5
333 ;
334 ; MIPS64R2-LABEL: ashr_i64:
335 ; MIPS64R2: # %bb.0: # %entry
336 ; MIPS64R2-NEXT: jr $ra
337 ; MIPS64R2-NEXT: dsrav $2, $4, $5
338 ;
339 ; MIPS64R6-LABEL: ashr_i64:
340 ; MIPS64R6: # %bb.0: # %entry
341 ; MIPS64R6-NEXT: jr $ra
342 ; MIPS64R6-NEXT: dsrav $2, $4, $5
343 ;
344 ; MMR3-LABEL: ashr_i64:
345 ; MMR3: # %bb.0: # %entry
346 ; MMR3-NEXT: srlv $2, $5, $7
347 ; MMR3-NEXT: xori $1, $7, 31
348 ; MMR3-NEXT: sll16 $3, $4, 1
349 ; MMR3-NEXT: sllv $3, $3, $1
350 ; MMR3-NEXT: or16 $3, $2
351 ; MMR3-NEXT: srav $2, $4, $7
352 ; MMR3-NEXT: andi16 $5, $7, 32
353 ; MMR3-NEXT: movn $3, $2, $5
354 ; MMR3-NEXT: sra $1, $4, 31
355 ; MMR3-NEXT: jr $ra
356 ; MMR3-NEXT: movn $2, $1, $5
357 ;
358 ; MMR6-LABEL: ashr_i64:
359 ; MMR6: # %bb.0: # %entry
360 ; MMR6-NEXT: srav $1, $4, $7
361 ; MMR6-NEXT: andi16 $3, $7, 32
362 ; MMR6-NEXT: seleqz $2, $1, $3
363 ; MMR6-NEXT: sra $6, $4, 31
364 ; MMR6-NEXT: selnez $6, $6, $3
365 ; MMR6-NEXT: or $2, $6, $2
366 ; MMR6-NEXT: srlv $5, $5, $7
367 ; MMR6-NEXT: xori $6, $7, 31
368 ; MMR6-NEXT: sll16 $4, $4, 1
369 ; MMR6-NEXT: sllv $4, $4, $6
370 ; MMR6-NEXT: or $4, $4, $5
371 ; MMR6-NEXT: seleqz $4, $4, $3
372 ; MMR6-NEXT: selnez $1, $1, $3
373 ; MMR6-NEXT: or $3, $1, $4
374 ; MMR6-NEXT: jrc $ra
375 entry:
376 %r = ashr i64 %a, %b
377 ret i64 %r
378 }
380 define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
381 ; MIPS-LABEL: ashr_i128:
382 ; MIPS: # %bb.0: # %entry
383 ; MIPS-NEXT: addiu $sp, $sp, -32
384 ; MIPS-NEXT: .cfi_def_cfa_offset 32
385 ; MIPS-NEXT: sra $1, $4, 31
386 ; MIPS-NEXT: sw $7, 28($sp)
387 ; MIPS-NEXT: sw $6, 24($sp)
388 ; MIPS-NEXT: sw $5, 20($sp)
389 ; MIPS-NEXT: sw $4, 16($sp)
390 ; MIPS-NEXT: sw $1, 12($sp)
391 ; MIPS-NEXT: sw $1, 8($sp)
392 ; MIPS-NEXT: sw $1, 4($sp)
393 ; MIPS-NEXT: sw $1, 0($sp)
394 ; MIPS-NEXT: addiu $1, $sp, 0
395 ; MIPS-NEXT: addiu $1, $1, 16
396 ; MIPS-NEXT: lw $2, 60($sp)
397 ; MIPS-NEXT: srl $3, $2, 3
398 ; MIPS-NEXT: andi $3, $3, 12
399 ; MIPS-NEXT: subu $1, $1, $3
400 ; MIPS-NEXT: lw $3, 4($1)
401 ; MIPS-NEXT: lw $5, 8($1)
402 ; MIPS-NEXT: srlv $4, $5, $2
403 ; MIPS-NEXT: sll $6, $3, 1
404 ; MIPS-NEXT: andi $7, $2, 31
405 ; MIPS-NEXT: xori $7, $7, 31
406 ; MIPS-NEXT: sllv $6, $6, $7
407 ; MIPS-NEXT: srlv $3, $3, $2
408 ; MIPS-NEXT: lw $8, 0($1)
409 ; MIPS-NEXT: sll $9, $8, 1
410 ; MIPS-NEXT: sllv $9, $9, $7
411 ; MIPS-NEXT: or $3, $3, $9
412 ; MIPS-NEXT: or $4, $4, $6
413 ; MIPS-NEXT: lw $1, 12($1)
414 ; MIPS-NEXT: srlv $1, $1, $2
415 ; MIPS-NEXT: sll $5, $5, 1
416 ; MIPS-NEXT: sllv $5, $5, $7
417 ; MIPS-NEXT: or $5, $1, $5
418 ; MIPS-NEXT: srav $2, $8, $2
419 ; MIPS-NEXT: jr $ra
420 ; MIPS-NEXT: addiu $sp, $sp, 32
421 ;
422 ; MIPS32-LABEL: ashr_i128:
423 ; MIPS32: # %bb.0: # %entry
424 ; MIPS32-NEXT: addiu $sp, $sp, -32
425 ; MIPS32-NEXT: .cfi_def_cfa_offset 32
426 ; MIPS32-NEXT: sra $1, $4, 31
427 ; MIPS32-NEXT: sw $7, 28($sp)
428 ; MIPS32-NEXT: sw $6, 24($sp)
429 ; MIPS32-NEXT: sw $5, 20($sp)
430 ; MIPS32-NEXT: sw $4, 16($sp)
431 ; MIPS32-NEXT: sw $1, 12($sp)
432 ; MIPS32-NEXT: sw $1, 8($sp)
433 ; MIPS32-NEXT: sw $1, 4($sp)
434 ; MIPS32-NEXT: sw $1, 0($sp)
435 ; MIPS32-NEXT: addiu $1, $sp, 0
436 ; MIPS32-NEXT: addiu $1, $1, 16
437 ; MIPS32-NEXT: lw $2, 60($sp)
438 ; MIPS32-NEXT: srl $3, $2, 3
439 ; MIPS32-NEXT: andi $3, $3, 12
440 ; MIPS32-NEXT: subu $1, $1, $3
441 ; MIPS32-NEXT: lw $3, 4($1)
442 ; MIPS32-NEXT: lw $5, 8($1)
443 ; MIPS32-NEXT: srlv $4, $5, $2
444 ; MIPS32-NEXT: sll $6, $3, 1
445 ; MIPS32-NEXT: andi $7, $2, 31
446 ; MIPS32-NEXT: xori $7, $7, 31
447 ; MIPS32-NEXT: sllv $6, $6, $7
448 ; MIPS32-NEXT: srlv $3, $3, $2
449 ; MIPS32-NEXT: lw $8, 0($1)
450 ; MIPS32-NEXT: sll $9, $8, 1
451 ; MIPS32-NEXT: sllv $9, $9, $7
452 ; MIPS32-NEXT: or $3, $3, $9
453 ; MIPS32-NEXT: or $4, $4, $6
454 ; MIPS32-NEXT: lw $1, 12($1)
455 ; MIPS32-NEXT: srlv $1, $1, $2
456 ; MIPS32-NEXT: sll $5, $5, 1
457 ; MIPS32-NEXT: sllv $5, $5, $7
458 ; MIPS32-NEXT: or $5, $1, $5
459 ; MIPS32-NEXT: srav $2, $8, $2
460 ; MIPS32-NEXT: jr $ra
461 ; MIPS32-NEXT: addiu $sp, $sp, 32
462 ;
463 ; 32R2-LABEL: ashr_i128:
464 ; 32R2: # %bb.0: # %entry
465 ; 32R2-NEXT: addiu $sp, $sp, -32
466 ; 32R2-NEXT: .cfi_def_cfa_offset 32
467 ; 32R2-NEXT: sra $1, $4, 31
468 ; 32R2-NEXT: sw $7, 28($sp)
469 ; 32R2-NEXT: sw $6, 24($sp)
470 ; 32R2-NEXT: sw $5, 20($sp)
471 ; 32R2-NEXT: sw $4, 16($sp)
472 ; 32R2-NEXT: sw $1, 12($sp)
473 ; 32R2-NEXT: sw $1, 8($sp)
474 ; 32R2-NEXT: sw $1, 4($sp)
475 ; 32R2-NEXT: sw $1, 0($sp)
476 ; 32R2-NEXT: addiu $1, $sp, 0
477 ; 32R2-NEXT: addiu $1, $1, 16
478 ; 32R2-NEXT: lw $2, 60($sp)
479 ; 32R2-NEXT: srl $3, $2, 3
480 ; 32R2-NEXT: andi $3, $3, 12
481 ; 32R2-NEXT: subu $1, $1, $3
482 ; 32R2-NEXT: lw $3, 4($1)
483 ; 32R2-NEXT: lw $5, 8($1)
484 ; 32R2-NEXT: srlv $4, $5, $2
485 ; 32R2-NEXT: sll $6, $3, 1
486 ; 32R2-NEXT: andi $7, $2, 31
487 ; 32R2-NEXT: xori $7, $7, 31
488 ; 32R2-NEXT: sllv $6, $6, $7
489 ; 32R2-NEXT: srlv $3, $3, $2
490 ; 32R2-NEXT: lw $8, 0($1)
491 ; 32R2-NEXT: sll $9, $8, 1
492 ; 32R2-NEXT: sllv $9, $9, $7
493 ; 32R2-NEXT: or $3, $3, $9
494 ; 32R2-NEXT: or $4, $4, $6
495 ; 32R2-NEXT: lw $1, 12($1)
496 ; 32R2-NEXT: srlv $1, $1, $2
497 ; 32R2-NEXT: sll $5, $5, 1
498 ; 32R2-NEXT: sllv $5, $5, $7
499 ; 32R2-NEXT: or $5, $1, $5
500 ; 32R2-NEXT: srav $2, $8, $2
501 ; 32R2-NEXT: jr $ra
502 ; 32R2-NEXT: addiu $sp, $sp, 32
503 ;
504 ; 32R6-LABEL: ashr_i128:
505 ; 32R6: # %bb.0: # %entry
506 ; 32R6-NEXT: addiu $sp, $sp, -32
507 ; 32R6-NEXT: .cfi_def_cfa_offset 32
508 ; 32R6-NEXT: sra $1, $4, 31
509 ; 32R6-NEXT: sw $7, 28($sp)
510 ; 32R6-NEXT: sw $6, 24($sp)
511 ; 32R6-NEXT: sw $5, 20($sp)
512 ; 32R6-NEXT: sw $4, 16($sp)
513 ; 32R6-NEXT: sw $1, 12($sp)
514 ; 32R6-NEXT: sw $1, 8($sp)
515 ; 32R6-NEXT: sw $1, 4($sp)
516 ; 32R6-NEXT: sw $1, 0($sp)
517 ; 32R6-NEXT: addiu $1, $sp, 0
518 ; 32R6-NEXT: addiu $1, $1, 16
519 ; 32R6-NEXT: lw $2, 60($sp)
520 ; 32R6-NEXT: srl $3, $2, 3
521 ; 32R6-NEXT: andi $3, $3, 12
522 ; 32R6-NEXT: subu $1, $1, $3
523 ; 32R6-NEXT: lw $3, 4($1)
524 ; 32R6-NEXT: lw $5, 8($1)
525 ; 32R6-NEXT: srlv $4, $5, $2
526 ; 32R6-NEXT: sll $6, $3, 1
527 ; 32R6-NEXT: andi $7, $2, 31
528 ; 32R6-NEXT: xori $7, $7, 31
529 ; 32R6-NEXT: sllv $6, $6, $7
530 ; 32R6-NEXT: srlv $3, $3, $2
531 ; 32R6-NEXT: lw $8, 0($1)
532 ; 32R6-NEXT: sll $9, $8, 1
533 ; 32R6-NEXT: sllv $9, $9, $7
534 ; 32R6-NEXT: or $3, $3, $9
535 ; 32R6-NEXT: or $4, $4, $6
536 ; 32R6-NEXT: lw $1, 12($1)
537 ; 32R6-NEXT: srlv $1, $1, $2
538 ; 32R6-NEXT: sll $5, $5, 1
539 ; 32R6-NEXT: sllv $5, $5, $7
540 ; 32R6-NEXT: or $5, $1, $5
541 ; 32R6-NEXT: srav $2, $8, $2
542 ; 32R6-NEXT: jr $ra
543 ; 32R6-NEXT: addiu $sp, $sp, 32
544 ;
545 ; MIPS3-LABEL: ashr_i128:
546 ; MIPS3: # %bb.0: # %entry
547 ; MIPS3-NEXT: sll $2, $7, 0
548 ; MIPS3-NEXT: andi $1, $2, 64
549 ; MIPS3-NEXT: bnez $1, .LBB5_2
550 ; MIPS3-NEXT: dsrav $3, $4, $7
551 ; MIPS3-NEXT: # %bb.1: # %entry
552 ; MIPS3-NEXT: dsrlv $1, $5, $7
553 ; MIPS3-NEXT: dsll $4, $4, 1
554 ; MIPS3-NEXT: xori $2, $2, 63
555 ; MIPS3-NEXT: dsllv $2, $4, $2
556 ; MIPS3-NEXT: or $1, $2, $1
557 ; MIPS3-NEXT: move $2, $3
558 ; MIPS3-NEXT: jr $ra
559 ; MIPS3-NEXT: move $3, $1
560 ; MIPS3-NEXT: .LBB5_2:
561 ; MIPS3-NEXT: jr $ra
562 ; MIPS3-NEXT: dsra $2, $4, 63
563 ;
564 ; MIPS64-LABEL: ashr_i128:
565 ; MIPS64: # %bb.0: # %entry
566 ; MIPS64-NEXT: dsrlv $1, $5, $7
567 ; MIPS64-NEXT: dsll $2, $4, 1
568 ; MIPS64-NEXT: sll $5, $7, 0
569 ; MIPS64-NEXT: xori $3, $5, 63
570 ; MIPS64-NEXT: dsllv $2, $2, $3
571 ; MIPS64-NEXT: or $3, $2, $1
572 ; MIPS64-NEXT: dsrav $2, $4, $7
573 ; MIPS64-NEXT: andi $1, $5, 64
574 ; MIPS64-NEXT: movn $3, $2, $1
575 ; MIPS64-NEXT: dsra $4, $4, 63
576 ; MIPS64-NEXT: jr $ra
577 ; MIPS64-NEXT: movn $2, $4, $1
578 ;
579 ; MIPS64R2-LABEL: ashr_i128:
580 ; MIPS64R2: # %bb.0: # %entry
581 ; MIPS64R2-NEXT: dsrlv $1, $5, $7
582 ; MIPS64R2-NEXT: dsll $2, $4, 1
583 ; MIPS64R2-NEXT: sll $5, $7, 0
584 ; MIPS64R2-NEXT: xori $3, $5, 63
585 ; MIPS64R2-NEXT: dsllv $2, $2, $3
586 ; MIPS64R2-NEXT: or $3, $2, $1
587 ; MIPS64R2-NEXT: dsrav $2, $4, $7
588 ; MIPS64R2-NEXT: andi $1, $5, 64
589 ; MIPS64R2-NEXT: movn $3, $2, $1
590 ; MIPS64R2-NEXT: dsra $4, $4, 63
591 ; MIPS64R2-NEXT: jr $ra
592 ; MIPS64R2-NEXT: movn $2, $4, $1
593 ;
594 ; MIPS64R6-LABEL: ashr_i128:
595 ; MIPS64R6: # %bb.0: # %entry
596 ; MIPS64R6-NEXT: dsrav $1, $4, $7
597 ; MIPS64R6-NEXT: sll $3, $7, 0
598 ; MIPS64R6-NEXT: andi $2, $3, 64
599 ; MIPS64R6-NEXT: sll $6, $2, 0
600 ; MIPS64R6-NEXT: seleqz $2, $1, $6
601 ; MIPS64R6-NEXT: dsra $8, $4, 63
602 ; MIPS64R6-NEXT: selnez $8, $8, $6
603 ; MIPS64R6-NEXT: or $2, $8, $2
604 ; MIPS64R6-NEXT: dsrlv $5, $5, $7
605 ; MIPS64R6-NEXT: dsll $4, $4, 1
606 ; MIPS64R6-NEXT: xori $3, $3, 63
607 ; MIPS64R6-NEXT: dsllv $3, $4, $3
608 ; MIPS64R6-NEXT: or $3, $3, $5
609 ; MIPS64R6-NEXT: seleqz $3, $3, $6
610 ; MIPS64R6-NEXT: selnez $1, $1, $6
611 ; MIPS64R6-NEXT: jr $ra
612 ; MIPS64R6-NEXT: or $3, $1, $3
613 ;
614 ; MMR3-LABEL: ashr_i128:
615 ; MMR3: # %bb.0: # %entry
616 ; MMR3-NEXT: addiusp -40
617 ; MMR3-NEXT: .cfi_def_cfa_offset 40
618 ; MMR3-NEXT: swp $16, 32($sp)
619 ; MMR3-NEXT: .cfi_offset 17, -4
620 ; MMR3-NEXT: .cfi_offset 16, -8
621 ; MMR3-NEXT: sra $1, $4, 31
622 ; MMR3-NEXT: swp $6, 24($sp)
623 ; MMR3-NEXT: swp $4, 16($sp)
624 ; MMR3-NEXT: sw $1, 12($sp)
625 ; MMR3-NEXT: sw $1, 8($sp)
626 ; MMR3-NEXT: sw $1, 4($sp)
627 ; MMR3-NEXT: sw $1, 0($sp)
628 ; MMR3-NEXT: addiur1sp $2, 0
629 ; MMR3-NEXT: addiur2 $2, $2, 16
630 ; MMR3-NEXT: lw $3, 68($sp)
631 ; MMR3-NEXT: srl16 $4, $3, 3
632 ; MMR3-NEXT: andi $4, $4, 12
633 ; MMR3-NEXT: subu16 $5, $2, $4
634 ; MMR3-NEXT: lwp $6, 4($5)
635 ; MMR3-NEXT: andi16 $2, $3, 31
636 ; MMR3-NEXT: srlv $16, $7, $2
637 ; MMR3-NEXT: sll16 $3, $6, 1
638 ; MMR3-NEXT: xori $1, $2, 31
639 ; MMR3-NEXT: sllv $4, $3, $1
640 ; MMR3-NEXT: srlv $6, $6, $2
641 ; MMR3-NEXT: lw16 $17, 0($5)
642 ; MMR3-NEXT: sll16 $3, $17, 1
643 ; MMR3-NEXT: sllv $3, $3, $1
644 ; MMR3-NEXT: or16 $3, $6
645 ; MMR3-NEXT: or16 $4, $16
646 ; MMR3-NEXT: lw16 $5, 12($5)
647 ; MMR3-NEXT: srlv $6, $5, $2
648 ; MMR3-NEXT: sll16 $5, $7, 1
649 ; MMR3-NEXT: sllv $5, $5, $1
650 ; MMR3-NEXT: or16 $5, $6
651 ; MMR3-NEXT: srav $2, $17, $2
652 ; MMR3-NEXT: lwp $16, 32($sp)
653 ; MMR3-NEXT: addiusp 40
654 ; MMR3-NEXT: jrc $ra
655 ;
656 ; MMR6-LABEL: ashr_i128:
657 ; MMR6: # %bb.0: # %entry
658 ; MMR6-NEXT: addiu $sp, $sp, -40
659 ; MMR6-NEXT: .cfi_def_cfa_offset 40
660 ; MMR6-NEXT: sw $16, 36($sp) # 4-byte Folded Spill
661 ; MMR6-NEXT: .cfi_offset 16, -4
662 ; MMR6-NEXT: sra $1, $4, 31
663 ; MMR6-NEXT: sw $7, 28($sp)
664 ; MMR6-NEXT: sw $6, 24($sp)
665 ; MMR6-NEXT: sw $5, 20($sp)
666 ; MMR6-NEXT: sw $4, 16($sp)
667 ; MMR6-NEXT: sw $1, 12($sp)
668 ; MMR6-NEXT: sw $1, 8($sp)
669 ; MMR6-NEXT: sw $1, 4($sp)
670 ; MMR6-NEXT: sw $1, 0($sp)
671 ; MMR6-NEXT: addiu $2, $sp, 0
672 ; MMR6-NEXT: addiur2 $2, $2, 16
673 ; MMR6-NEXT: lw $3, 68($sp)
674 ; MMR6-NEXT: srl16 $4, $3, 3
675 ; MMR6-NEXT: andi $4, $4, 12
676 ; MMR6-NEXT: subu16 $2, $2, $4
677 ; MMR6-NEXT: lw16 $4, 4($2)
678 ; MMR6-NEXT: lw16 $5, 8($2)
679 ; MMR6-NEXT: andi16 $6, $3, 31
680 ; MMR6-NEXT: srlv $1, $5, $6
681 ; MMR6-NEXT: sll16 $3, $4, 1
682 ; MMR6-NEXT: xori $7, $6, 31
683 ; MMR6-NEXT: sllv $8, $3, $7
684 ; MMR6-NEXT: srlv $3, $4, $6
685 ; MMR6-NEXT: lw16 $16, 0($2)
686 ; MMR6-NEXT: sll16 $4, $16, 1
687 ; MMR6-NEXT: sllv $4, $4, $7
688 ; MMR6-NEXT: or $3, $3, $4
689 ; MMR6-NEXT: or $4, $1, $8
690 ; MMR6-NEXT: lw16 $2, 12($2)
691 ; MMR6-NEXT: srlv $1, $2, $6
692 ; MMR6-NEXT: sll16 $2, $5, 1
693 ; MMR6-NEXT: sllv $2, $2, $7
694 ; MMR6-NEXT: or $5, $1, $2
695 ; MMR6-NEXT: srav $2, $16, $6
696 ; MMR6-NEXT: lw $16, 36($sp) # 4-byte Folded Reload
697 ; MMR6-NEXT: addiu $sp, $sp, 40
698 ; MMR6-NEXT: jrc $ra
699 entry:
700 %r = ashr i128 %a, %b
701 ret i128 %r
702 }