| blob | 9451f1e9be0967194c04621c6d77fa47d75a0001 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
3 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS2
4 ; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
5 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
6 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic \
7 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
8 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic \
9 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
10 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic \
11 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
12 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic \
13 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP32R6
15 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
16 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS3
17 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic \
18 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS3
19 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
20 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
21 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic \
22 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
23 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic \
24 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
25 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic \
26 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
27 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic \
28 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP64R6
30 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips \
31 ; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
32 ; RUN: FileCheck %s -check-prefix=MMR3
33 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \
34 ; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
35 ; RUN: FileCheck %s -check-prefix=MMR6
37 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
38 ; MIPS2-LABEL: udiv_i1:
39 ; MIPS2: # %bb.0: # %entry
40 ; MIPS2-NEXT: jr $ra
41 ; MIPS2-NEXT: move $2, $4
42 ;
43 ; GP32-LABEL: udiv_i1:
44 ; GP32: # %bb.0: # %entry
45 ; GP32-NEXT: jr $ra
46 ; GP32-NEXT: move $2, $4
47 ;
48 ; GP32R6-LABEL: udiv_i1:
49 ; GP32R6: # %bb.0: # %entry
50 ; GP32R6-NEXT: jr $ra
51 ; GP32R6-NEXT: move $2, $4
52 ;
53 ; MIPS3-LABEL: udiv_i1:
54 ; MIPS3: # %bb.0: # %entry
55 ; MIPS3-NEXT: jr $ra
56 ; MIPS3-NEXT: move $2, $4
57 ;
58 ; GP64-LABEL: udiv_i1:
59 ; GP64: # %bb.0: # %entry
60 ; GP64-NEXT: jr $ra
61 ; GP64-NEXT: move $2, $4
62 ;
63 ; GP64R6-LABEL: udiv_i1:
64 ; GP64R6: # %bb.0: # %entry
65 ; GP64R6-NEXT: jr $ra
66 ; GP64R6-NEXT: move $2, $4
67 ;
68 ; MMR3-LABEL: udiv_i1:
69 ; MMR3: # %bb.0: # %entry
70 ; MMR3-NEXT: move $2, $4
71 ; MMR3-NEXT: jrc $ra
72 ;
73 ; MMR6-LABEL: udiv_i1:
74 ; MMR6: # %bb.0: # %entry
75 ; MMR6-NEXT: move $2, $4
76 ; MMR6-NEXT: jrc $ra
77 entry:
78 %r = udiv i1 %a, %b
79 ret i1 %r
80 }
82 define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {
83 ; MIPS2-LABEL: udiv_i8:
84 ; MIPS2: # %bb.0: # %entry
85 ; MIPS2-NEXT: divu $zero, $4, $5
86 ; MIPS2-NEXT: teq $5, $zero, 7
87 ; MIPS2-NEXT: mflo $2
88 ; MIPS2-NEXT: jr $ra
89 ; MIPS2-NEXT: nop
90 ;
91 ; GP32-LABEL: udiv_i8:
92 ; GP32: # %bb.0: # %entry
93 ; GP32-NEXT: divu $zero, $4, $5
94 ; GP32-NEXT: teq $5, $zero, 7
95 ; GP32-NEXT: jr $ra
96 ; GP32-NEXT: mflo $2
97 ;
98 ; GP32R6-LABEL: udiv_i8:
99 ; GP32R6: # %bb.0: # %entry
100 ; GP32R6-NEXT: divu $2, $4, $5
101 ; GP32R6-NEXT: teq $5, $zero, 7
102 ; GP32R6-NEXT: jrc $ra
103 ;
104 ; MIPS3-LABEL: udiv_i8:
105 ; MIPS3: # %bb.0: # %entry
106 ; MIPS3-NEXT: divu $zero, $4, $5
107 ; MIPS3-NEXT: teq $5, $zero, 7
108 ; MIPS3-NEXT: mflo $2
109 ; MIPS3-NEXT: jr $ra
110 ; MIPS3-NEXT: nop
111 ;
112 ; GP64-LABEL: udiv_i8:
113 ; GP64: # %bb.0: # %entry
114 ; GP64-NEXT: divu $zero, $4, $5
115 ; GP64-NEXT: teq $5, $zero, 7
116 ; GP64-NEXT: jr $ra
117 ; GP64-NEXT: mflo $2
118 ;
119 ; GP64R6-LABEL: udiv_i8:
120 ; GP64R6: # %bb.0: # %entry
121 ; GP64R6-NEXT: divu $2, $4, $5
122 ; GP64R6-NEXT: teq $5, $zero, 7
123 ; GP64R6-NEXT: jrc $ra
124 ;
125 ; MMR3-LABEL: udiv_i8:
126 ; MMR3: # %bb.0: # %entry
127 ; MMR3-NEXT: divu $zero, $4, $5
128 ; MMR3-NEXT: teq $5, $zero, 7
129 ; MMR3-NEXT: mflo16 $2
130 ; MMR3-NEXT: jrc $ra
131 ;
132 ; MMR6-LABEL: udiv_i8:
133 ; MMR6: # %bb.0: # %entry
134 ; MMR6-NEXT: divu $2, $4, $5
135 ; MMR6-NEXT: teq $5, $zero, 7
136 ; MMR6-NEXT: jrc $ra
137 entry:
138 %r = udiv i8 %a, %b
139 ret i8 %r
140 }
142 define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) {
143 ; MIPS2-LABEL: udiv_i16:
144 ; MIPS2: # %bb.0: # %entry
145 ; MIPS2-NEXT: divu $zero, $4, $5
146 ; MIPS2-NEXT: teq $5, $zero, 7
147 ; MIPS2-NEXT: mflo $2
148 ; MIPS2-NEXT: jr $ra
149 ; MIPS2-NEXT: nop
150 ;
151 ; GP32-LABEL: udiv_i16:
152 ; GP32: # %bb.0: # %entry
153 ; GP32-NEXT: divu $zero, $4, $5
154 ; GP32-NEXT: teq $5, $zero, 7
155 ; GP32-NEXT: jr $ra
156 ; GP32-NEXT: mflo $2
157 ;
158 ; GP32R6-LABEL: udiv_i16:
159 ; GP32R6: # %bb.0: # %entry
160 ; GP32R6-NEXT: divu $2, $4, $5
161 ; GP32R6-NEXT: teq $5, $zero, 7
162 ; GP32R6-NEXT: jrc $ra
163 ;
164 ; MIPS3-LABEL: udiv_i16:
165 ; MIPS3: # %bb.0: # %entry
166 ; MIPS3-NEXT: divu $zero, $4, $5
167 ; MIPS3-NEXT: teq $5, $zero, 7
168 ; MIPS3-NEXT: mflo $2
169 ; MIPS3-NEXT: jr $ra
170 ; MIPS3-NEXT: nop
171 ;
172 ; GP64-LABEL: udiv_i16:
173 ; GP64: # %bb.0: # %entry
174 ; GP64-NEXT: divu $zero, $4, $5
175 ; GP64-NEXT: teq $5, $zero, 7
176 ; GP64-NEXT: jr $ra
177 ; GP64-NEXT: mflo $2
178 ;
179 ; GP64R6-LABEL: udiv_i16:
180 ; GP64R6: # %bb.0: # %entry
181 ; GP64R6-NEXT: divu $2, $4, $5
182 ; GP64R6-NEXT: teq $5, $zero, 7
183 ; GP64R6-NEXT: jrc $ra
184 ;
185 ; MMR3-LABEL: udiv_i16:
186 ; MMR3: # %bb.0: # %entry
187 ; MMR3-NEXT: divu $zero, $4, $5
188 ; MMR3-NEXT: teq $5, $zero, 7
189 ; MMR3-NEXT: mflo16 $2
190 ; MMR3-NEXT: jrc $ra
191 ;
192 ; MMR6-LABEL: udiv_i16:
193 ; MMR6: # %bb.0: # %entry
194 ; MMR6-NEXT: divu $2, $4, $5
195 ; MMR6-NEXT: teq $5, $zero, 7
196 ; MMR6-NEXT: jrc $ra
197 entry:
198 %r = udiv i16 %a, %b
199 ret i16 %r
200 }
202 define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) {
203 ; MIPS2-LABEL: udiv_i32:
204 ; MIPS2: # %bb.0: # %entry
205 ; MIPS2-NEXT: divu $zero, $4, $5
206 ; MIPS2-NEXT: teq $5, $zero, 7
207 ; MIPS2-NEXT: mflo $2
208 ; MIPS2-NEXT: jr $ra
209 ; MIPS2-NEXT: nop
210 ;
211 ; GP32-LABEL: udiv_i32:
212 ; GP32: # %bb.0: # %entry
213 ; GP32-NEXT: divu $zero, $4, $5
214 ; GP32-NEXT: teq $5, $zero, 7
215 ; GP32-NEXT: jr $ra
216 ; GP32-NEXT: mflo $2
217 ;
218 ; GP32R6-LABEL: udiv_i32:
219 ; GP32R6: # %bb.0: # %entry
220 ; GP32R6-NEXT: divu $2, $4, $5
221 ; GP32R6-NEXT: teq $5, $zero, 7
222 ; GP32R6-NEXT: jrc $ra
223 ;
224 ; MIPS3-LABEL: udiv_i32:
225 ; MIPS3: # %bb.0: # %entry
226 ; MIPS3-NEXT: divu $zero, $4, $5
227 ; MIPS3-NEXT: teq $5, $zero, 7
228 ; MIPS3-NEXT: mflo $2
229 ; MIPS3-NEXT: jr $ra
230 ; MIPS3-NEXT: nop
231 ;
232 ; GP64-LABEL: udiv_i32:
233 ; GP64: # %bb.0: # %entry
234 ; GP64-NEXT: divu $zero, $4, $5
235 ; GP64-NEXT: teq $5, $zero, 7
236 ; GP64-NEXT: jr $ra
237 ; GP64-NEXT: mflo $2
238 ;
239 ; GP64R6-LABEL: udiv_i32:
240 ; GP64R6: # %bb.0: # %entry
241 ; GP64R6-NEXT: divu $2, $4, $5
242 ; GP64R6-NEXT: teq $5, $zero, 7
243 ; GP64R6-NEXT: jrc $ra
244 ;
245 ; MMR3-LABEL: udiv_i32:
246 ; MMR3: # %bb.0: # %entry
247 ; MMR3-NEXT: divu $zero, $4, $5
248 ; MMR3-NEXT: teq $5, $zero, 7
249 ; MMR3-NEXT: mflo16 $2
250 ; MMR3-NEXT: jrc $ra
251 ;
252 ; MMR6-LABEL: udiv_i32:
253 ; MMR6: # %bb.0: # %entry
254 ; MMR6-NEXT: divu $2, $4, $5
255 ; MMR6-NEXT: teq $5, $zero, 7
256 ; MMR6-NEXT: jrc $ra
257 entry:
258 %r = udiv i32 %a, %b
259 ret i32 %r
260 }
262 define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) {
263 ; MIPS2-LABEL: udiv_i64:
264 ; MIPS2: # %bb.0: # %entry
265 ; MIPS2-NEXT: lui $2, %hi(_gp_disp)
266 ; MIPS2-NEXT: addiu $2, $2, %lo(_gp_disp)
267 ; MIPS2-NEXT: addiu $sp, $sp, -24
268 ; MIPS2-NEXT: .cfi_def_cfa_offset 24
269 ; MIPS2-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
270 ; MIPS2-NEXT: .cfi_offset 31, -4
271 ; MIPS2-NEXT: addu $gp, $2, $25
272 ; MIPS2-NEXT: lw $25, %call16(__udivdi3)($gp)
273 ; MIPS2-NEXT: jalr $25
274 ; MIPS2-NEXT: nop
275 ; MIPS2-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
276 ; MIPS2-NEXT: jr $ra
277 ; MIPS2-NEXT: addiu $sp, $sp, 24
278 ;
279 ; GP32-LABEL: udiv_i64:
280 ; GP32: # %bb.0: # %entry
281 ; GP32-NEXT: lui $2, %hi(_gp_disp)
282 ; GP32-NEXT: addiu $2, $2, %lo(_gp_disp)
283 ; GP32-NEXT: addiu $sp, $sp, -24
284 ; GP32-NEXT: .cfi_def_cfa_offset 24
285 ; GP32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
286 ; GP32-NEXT: .cfi_offset 31, -4
287 ; GP32-NEXT: addu $gp, $2, $25
288 ; GP32-NEXT: lw $25, %call16(__udivdi3)($gp)
289 ; GP32-NEXT: jalr $25
290 ; GP32-NEXT: nop
291 ; GP32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
292 ; GP32-NEXT: jr $ra
293 ; GP32-NEXT: addiu $sp, $sp, 24
294 ;
295 ; GP32R6-LABEL: udiv_i64:
296 ; GP32R6: # %bb.0: # %entry
297 ; GP32R6-NEXT: lui $2, %hi(_gp_disp)
298 ; GP32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
299 ; GP32R6-NEXT: addiu $sp, $sp, -24
300 ; GP32R6-NEXT: .cfi_def_cfa_offset 24
301 ; GP32R6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
302 ; GP32R6-NEXT: .cfi_offset 31, -4
303 ; GP32R6-NEXT: addu $gp, $2, $25
304 ; GP32R6-NEXT: lw $25, %call16(__udivdi3)($gp)
305 ; GP32R6-NEXT: jalrc $25
306 ; GP32R6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
307 ; GP32R6-NEXT: jr $ra
308 ; GP32R6-NEXT: addiu $sp, $sp, 24
309 ;
310 ; MIPS3-LABEL: udiv_i64:
311 ; MIPS3: # %bb.0: # %entry
312 ; MIPS3-NEXT: ddivu $zero, $4, $5
313 ; MIPS3-NEXT: teq $5, $zero, 7
314 ; MIPS3-NEXT: mflo $2
315 ; MIPS3-NEXT: jr $ra
316 ; MIPS3-NEXT: nop
317 ;
318 ; GP64-LABEL: udiv_i64:
319 ; GP64: # %bb.0: # %entry
320 ; GP64-NEXT: ddivu $zero, $4, $5
321 ; GP64-NEXT: teq $5, $zero, 7
322 ; GP64-NEXT: jr $ra
323 ; GP64-NEXT: mflo $2
324 ;
325 ; GP64R6-LABEL: udiv_i64:
326 ; GP64R6: # %bb.0: # %entry
327 ; GP64R6-NEXT: ddivu $2, $4, $5
328 ; GP64R6-NEXT: teq $5, $zero, 7
329 ; GP64R6-NEXT: jrc $ra
330 ;
331 ; MMR3-LABEL: udiv_i64:
332 ; MMR3: # %bb.0: # %entry
333 ; MMR3-NEXT: lui $2, %hi(_gp_disp)
334 ; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
335 ; MMR3-NEXT: addiusp -24
336 ; MMR3-NEXT: .cfi_def_cfa_offset 24
337 ; MMR3-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
338 ; MMR3-NEXT: .cfi_offset 31, -4
339 ; MMR3-NEXT: addu $gp, $2, $25
340 ; MMR3-NEXT: lw $25, %call16(__udivdi3)($gp)
341 ; MMR3-NEXT: jalr $25
342 ; MMR3-NEXT: nop
343 ; MMR3-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
344 ; MMR3-NEXT: addiusp 24
345 ; MMR3-NEXT: jrc $ra
346 ;
347 ; MMR6-LABEL: udiv_i64:
348 ; MMR6: # %bb.0: # %entry
349 ; MMR6-NEXT: lui $2, %hi(_gp_disp)
350 ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
351 ; MMR6-NEXT: addiu $sp, $sp, -24
352 ; MMR6-NEXT: .cfi_def_cfa_offset 24
353 ; MMR6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
354 ; MMR6-NEXT: .cfi_offset 31, -4
355 ; MMR6-NEXT: addu $gp, $2, $25
356 ; MMR6-NEXT: lw $25, %call16(__udivdi3)($gp)
357 ; MMR6-NEXT: jalr $25
358 ; MMR6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
359 ; MMR6-NEXT: addiu $sp, $sp, 24
360 ; MMR6-NEXT: jrc $ra
361 entry:
362 %r = udiv i64 %a, %b
363 ret i64 %r
364 }
366 define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) {
367 ; MIPS2-LABEL: udiv_i128:
368 ; MIPS2: # %bb.0: # %entry
369 ; MIPS2-NEXT: lui $2, %hi(_gp_disp)
370 ; MIPS2-NEXT: addiu $2, $2, %lo(_gp_disp)
371 ; MIPS2-NEXT: addiu $sp, $sp, -40
372 ; MIPS2-NEXT: .cfi_def_cfa_offset 40
373 ; MIPS2-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
374 ; MIPS2-NEXT: .cfi_offset 31, -4
375 ; MIPS2-NEXT: addu $gp, $2, $25
376 ; MIPS2-NEXT: lw $1, 60($sp)
377 ; MIPS2-NEXT: lw $2, 64($sp)
378 ; MIPS2-NEXT: lw $3, 68($sp)
379 ; MIPS2-NEXT: sw $3, 28($sp)
380 ; MIPS2-NEXT: sw $2, 24($sp)
381 ; MIPS2-NEXT: sw $1, 20($sp)
382 ; MIPS2-NEXT: lw $1, 56($sp)
383 ; MIPS2-NEXT: sw $1, 16($sp)
384 ; MIPS2-NEXT: lw $25, %call16(__udivti3)($gp)
385 ; MIPS2-NEXT: jalr $25
386 ; MIPS2-NEXT: nop
387 ; MIPS2-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
388 ; MIPS2-NEXT: jr $ra
389 ; MIPS2-NEXT: addiu $sp, $sp, 40
390 ;
391 ; GP32-LABEL: udiv_i128:
392 ; GP32: # %bb.0: # %entry
393 ; GP32-NEXT: lui $2, %hi(_gp_disp)
394 ; GP32-NEXT: addiu $2, $2, %lo(_gp_disp)
395 ; GP32-NEXT: addiu $sp, $sp, -40
396 ; GP32-NEXT: .cfi_def_cfa_offset 40
397 ; GP32-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
398 ; GP32-NEXT: .cfi_offset 31, -4
399 ; GP32-NEXT: addu $gp, $2, $25
400 ; GP32-NEXT: lw $1, 60($sp)
401 ; GP32-NEXT: lw $2, 64($sp)
402 ; GP32-NEXT: lw $3, 68($sp)
403 ; GP32-NEXT: sw $3, 28($sp)
404 ; GP32-NEXT: sw $2, 24($sp)
405 ; GP32-NEXT: sw $1, 20($sp)
406 ; GP32-NEXT: lw $1, 56($sp)
407 ; GP32-NEXT: sw $1, 16($sp)
408 ; GP32-NEXT: lw $25, %call16(__udivti3)($gp)
409 ; GP32-NEXT: jalr $25
410 ; GP32-NEXT: nop
411 ; GP32-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
412 ; GP32-NEXT: jr $ra
413 ; GP32-NEXT: addiu $sp, $sp, 40
414 ;
415 ; GP32R6-LABEL: udiv_i128:
416 ; GP32R6: # %bb.0: # %entry
417 ; GP32R6-NEXT: lui $2, %hi(_gp_disp)
418 ; GP32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
419 ; GP32R6-NEXT: addiu $sp, $sp, -40
420 ; GP32R6-NEXT: .cfi_def_cfa_offset 40
421 ; GP32R6-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
422 ; GP32R6-NEXT: .cfi_offset 31, -4
423 ; GP32R6-NEXT: addu $gp, $2, $25
424 ; GP32R6-NEXT: lw $1, 60($sp)
425 ; GP32R6-NEXT: lw $2, 64($sp)
426 ; GP32R6-NEXT: lw $3, 68($sp)
427 ; GP32R6-NEXT: sw $3, 28($sp)
428 ; GP32R6-NEXT: sw $2, 24($sp)
429 ; GP32R6-NEXT: sw $1, 20($sp)
430 ; GP32R6-NEXT: lw $1, 56($sp)
431 ; GP32R6-NEXT: sw $1, 16($sp)
432 ; GP32R6-NEXT: lw $25, %call16(__udivti3)($gp)
433 ; GP32R6-NEXT: jalrc $25
434 ; GP32R6-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
435 ; GP32R6-NEXT: jr $ra
436 ; GP32R6-NEXT: addiu $sp, $sp, 40
437 ;
438 ; MIPS3-LABEL: udiv_i128:
439 ; MIPS3: # %bb.0: # %entry
440 ; MIPS3-NEXT: daddiu $sp, $sp, -16
441 ; MIPS3-NEXT: .cfi_def_cfa_offset 16
442 ; MIPS3-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
443 ; MIPS3-NEXT: sd $gp, 0($sp) # 8-byte Folded Spill
444 ; MIPS3-NEXT: .cfi_offset 31, -8
445 ; MIPS3-NEXT: .cfi_offset 28, -16
446 ; MIPS3-NEXT: lui $1, %hi(%neg(%gp_rel(udiv_i128)))
447 ; MIPS3-NEXT: daddu $1, $1, $25
448 ; MIPS3-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(udiv_i128)))
449 ; MIPS3-NEXT: ld $25, %call16(__udivti3)($gp)
450 ; MIPS3-NEXT: jalr $25
451 ; MIPS3-NEXT: nop
452 ; MIPS3-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
453 ; MIPS3-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
454 ; MIPS3-NEXT: jr $ra
455 ; MIPS3-NEXT: daddiu $sp, $sp, 16
456 ;
457 ; GP64-LABEL: udiv_i128:
458 ; GP64: # %bb.0: # %entry
459 ; GP64-NEXT: daddiu $sp, $sp, -16
460 ; GP64-NEXT: .cfi_def_cfa_offset 16
461 ; GP64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
462 ; GP64-NEXT: sd $gp, 0($sp) # 8-byte Folded Spill
463 ; GP64-NEXT: .cfi_offset 31, -8
464 ; GP64-NEXT: .cfi_offset 28, -16
465 ; GP64-NEXT: lui $1, %hi(%neg(%gp_rel(udiv_i128)))
466 ; GP64-NEXT: daddu $1, $1, $25
467 ; GP64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(udiv_i128)))
468 ; GP64-NEXT: ld $25, %call16(__udivti3)($gp)
469 ; GP64-NEXT: jalr $25
470 ; GP64-NEXT: nop
471 ; GP64-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
472 ; GP64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
473 ; GP64-NEXT: jr $ra
474 ; GP64-NEXT: daddiu $sp, $sp, 16
475 ;
476 ; GP64R6-LABEL: udiv_i128:
477 ; GP64R6: # %bb.0: # %entry
478 ; GP64R6-NEXT: daddiu $sp, $sp, -16
479 ; GP64R6-NEXT: .cfi_def_cfa_offset 16
480 ; GP64R6-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
481 ; GP64R6-NEXT: sd $gp, 0($sp) # 8-byte Folded Spill
482 ; GP64R6-NEXT: .cfi_offset 31, -8
483 ; GP64R6-NEXT: .cfi_offset 28, -16
484 ; GP64R6-NEXT: lui $1, %hi(%neg(%gp_rel(udiv_i128)))
485 ; GP64R6-NEXT: daddu $1, $1, $25
486 ; GP64R6-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(udiv_i128)))
487 ; GP64R6-NEXT: ld $25, %call16(__udivti3)($gp)
488 ; GP64R6-NEXT: jalrc $25
489 ; GP64R6-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
490 ; GP64R6-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
491 ; GP64R6-NEXT: jr $ra
492 ; GP64R6-NEXT: daddiu $sp, $sp, 16
493 ;
494 ; MMR3-LABEL: udiv_i128:
495 ; MMR3: # %bb.0: # %entry
496 ; MMR3-NEXT: lui $2, %hi(_gp_disp)
497 ; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
498 ; MMR3-NEXT: addiusp -40
499 ; MMR3-NEXT: .cfi_def_cfa_offset 40
500 ; MMR3-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
501 ; MMR3-NEXT: sw $17, 32($sp) # 4-byte Folded Spill
502 ; MMR3-NEXT: .cfi_offset 31, -4
503 ; MMR3-NEXT: .cfi_offset 17, -8
504 ; MMR3-NEXT: addu $gp, $2, $25
505 ; MMR3-NEXT: move $1, $7
506 ; MMR3-NEXT: lw $7, 60($sp)
507 ; MMR3-NEXT: lw $17, 64($sp)
508 ; MMR3-NEXT: lw $3, 68($sp)
509 ; MMR3-NEXT: move $2, $sp
510 ; MMR3-NEXT: sw16 $3, 28($2)
511 ; MMR3-NEXT: sw16 $17, 24($2)
512 ; MMR3-NEXT: sw16 $7, 20($2)
513 ; MMR3-NEXT: lw $3, 56($sp)
514 ; MMR3-NEXT: sw16 $3, 16($2)
515 ; MMR3-NEXT: lw $25, %call16(__udivti3)($gp)
516 ; MMR3-NEXT: move $7, $1
517 ; MMR3-NEXT: jalr $25
518 ; MMR3-NEXT: nop
519 ; MMR3-NEXT: lw $17, 32($sp) # 4-byte Folded Reload
520 ; MMR3-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
521 ; MMR3-NEXT: addiusp 40
522 ; MMR3-NEXT: jrc $ra
523 ;
524 ; MMR6-LABEL: udiv_i128:
525 ; MMR6: # %bb.0: # %entry
526 ; MMR6-NEXT: lui $2, %hi(_gp_disp)
527 ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
528 ; MMR6-NEXT: addiu $sp, $sp, -40
529 ; MMR6-NEXT: .cfi_def_cfa_offset 40
530 ; MMR6-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
531 ; MMR6-NEXT: sw $17, 32($sp) # 4-byte Folded Spill
532 ; MMR6-NEXT: .cfi_offset 31, -4
533 ; MMR6-NEXT: .cfi_offset 17, -8
534 ; MMR6-NEXT: addu $gp, $2, $25
535 ; MMR6-NEXT: move $1, $7
536 ; MMR6-NEXT: lw $7, 60($sp)
537 ; MMR6-NEXT: lw $17, 64($sp)
538 ; MMR6-NEXT: lw $3, 68($sp)
539 ; MMR6-NEXT: move $2, $sp
540 ; MMR6-NEXT: sw16 $3, 28($2)
541 ; MMR6-NEXT: sw16 $17, 24($2)
542 ; MMR6-NEXT: sw16 $7, 20($2)
543 ; MMR6-NEXT: lw $3, 56($sp)
544 ; MMR6-NEXT: sw16 $3, 16($2)
545 ; MMR6-NEXT: lw $25, %call16(__udivti3)($gp)
546 ; MMR6-NEXT: move $7, $1
547 ; MMR6-NEXT: jalr $25
548 ; MMR6-NEXT: lw $17, 32($sp) # 4-byte Folded Reload
549 ; MMR6-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
550 ; MMR6-NEXT: addiu $sp, $sp, 40
551 ; MMR6-NEXT: jrc $ra
552 entry:
553 %r = udiv i128 %a, %b
554 ret i128 %r
555 }