1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+micromips -relocation-model=pic < %s | FileCheck %s
4 ; Test that the delay slot filler correctly handles indirect branches for
5 ; microMIPS in regard to incorrectly using 16bit instructions in delay slots of
8 define i32 @test(i32 signext %x, i32 signext %c) {
10 ; CHECK: # %bb.0: # %entry
11 ; CHECK-NEXT: lui $2, %hi(_gp_disp)
12 ; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)
13 ; CHECK-NEXT: addiur2 $5, $5, -1
14 ; CHECK-NEXT: sltiu $1, $5, 4
15 ; CHECK-NEXT: beqz $1, $BB0_6
16 ; CHECK-NEXT: addu $3, $2, $25
17 ; CHECK-NEXT: # %bb.1: # %entry
18 ; CHECK-NEXT: li16 $2, 0
19 ; CHECK-NEXT: sll16 $5, $5, 2
20 ; CHECK-NEXT: lw $6, %got($JTI0_0)($3)
21 ; CHECK-NEXT: addu16 $5, $5, $6
22 ; CHECK-NEXT: lw $5, %lo($JTI0_0)($5)
23 ; CHECK-NEXT: addu16 $3, $5, $3
26 ; CHECK-NEXT: $BB0_2: # %sw.bb2
27 ; CHECK-NEXT: addiur2 $2, $4, 1
29 ; CHECK-NEXT: $BB0_3: # %sw.bb3
30 ; CHECK-NEXT: addius5 $4, 2
31 ; CHECK-NEXT: move $2, $4
33 ; CHECK-NEXT: $BB0_4: # %sw.bb5
34 ; CHECK-NEXT: addius5 $4, 3
35 ; CHECK-NEXT: move $2, $4
36 ; CHECK-NEXT: $BB0_5: # %for.cond.cleanup
39 ; CHECK-NEXT: move $2, $4
42 switch i32 %c, label %sw.epilog [
44 i32 1, label %for.cond.cleanup
50 %add = add nsw i32 %x, 1
54 %add4 = add nsw i32 %x, 2
58 %add6 = add nsw i32 %x, 3
62 %a.0 = phi i32 [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add, %sw.bb2 ], [ %x, %entry ]
63 br label %for.cond.cleanup
66 %a.028 = phi i32 [ %a.0, %sw.epilog ], [ 0, %entry ]