1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
7 ; RUN: FileCheck %s --check-prefix=CHECK-BE
9 ; This test case tests spilling the CR LT bit on Power10. On Power10, this is
10 ; achieved by setb %reg, %CRREG (lt bit) -> stw %reg, $FI instead of:
11 ; mfocrf %reg, %CRREG -> rlwinm %reg1, %reg, $SH, 0, 0 -> stw %reg1, $FI.
13 ; Without fine-grained control over clobbering individual CR bits,
14 ; it is difficult to produce a concise test case that will ensure a specific
15 ; bit of any CR field is spilled. We need to test the spilling of a CR bit
16 ; other than the LT bit. Hence this test case is rather complex.
19 %1 = type { ptr, ptr, ptr, i32 }
21 @call_1 = external dso_local unnamed_addr global i32, align 4
22 declare ptr @call_2() local_unnamed_addr
23 declare i32 @call_3() local_unnamed_addr
24 declare void @call_4() local_unnamed_addr
26 define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
27 ; CHECK-LABEL: P10_Spill_CR_LT:
28 ; CHECK: # %bb.0: # %bb
29 ; CHECK-NEXT: mfcr r12
31 ; CHECK-NEXT: std r0, 16(r1)
32 ; CHECK-NEXT: stw r12, 8(r1)
33 ; CHECK-NEXT: stdu r1, -64(r1)
34 ; CHECK-NEXT: .cfi_def_cfa_offset 64
35 ; CHECK-NEXT: .cfi_offset lr, 16
36 ; CHECK-NEXT: .cfi_offset r29, -24
37 ; CHECK-NEXT: .cfi_offset r30, -16
38 ; CHECK-NEXT: .cfi_offset cr2, 8
39 ; CHECK-NEXT: .cfi_offset cr3, 8
40 ; CHECK-NEXT: .cfi_offset cr4, 8
41 ; CHECK-NEXT: std r29, 40(r1) # 8-byte Folded Spill
42 ; CHECK-NEXT: std r30, 48(r1) # 8-byte Folded Spill
43 ; CHECK-NEXT: bl call_2@notoc
44 ; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_13
45 ; CHECK-NEXT: # %bb.1: # %bb
46 ; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_14
47 ; CHECK-NEXT: # %bb.2: # %bb4
48 ; CHECK-NEXT: cmpdi cr3, r3, 0
49 ; CHECK-NEXT: lwz r3, 0(r3)
50 ; CHECK-NEXT: # implicit-def: $r30
51 ; CHECK-NEXT: crnot 4*cr3+lt, 4*cr3+eq
52 ; CHECK-NEXT: cmpwi cr4, r3, 0
53 ; CHECK-NEXT: .p2align 4
54 ; CHECK-NEXT: .LBB0_3: # %bb12
56 ; CHECK-NEXT: bl call_3@notoc
57 ; CHECK-NEXT: cmpwi r3, 1
58 ; CHECK-NEXT: crnand 4*cr5+lt, eq, 4*cr4+gt
59 ; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_8
60 ; CHECK-NEXT: # %bb.4: # %bb23
62 ; CHECK-NEXT: plwz r3, call_1@PCREL(0), 1
63 ; CHECK-NEXT: cmplwi r3, 0
64 ; CHECK-NEXT: bne- cr0, .LBB0_9
65 ; CHECK-NEXT: # %bb.5: # %bb30
67 ; CHECK-NEXT: bc 12, 4*cr3+eq, .LBB0_11
68 ; CHECK-NEXT: # %bb.6: # %bb32
70 ; CHECK-NEXT: andi. r3, r30, 2
71 ; CHECK-NEXT: rlwinm r29, r30, 0, 24, 22
72 ; CHECK-NEXT: mcrf cr2, cr0
73 ; CHECK-NEXT: bl call_4@notoc
74 ; CHECK-NEXT: mr r30, r29
75 ; CHECK-NEXT: beq+ cr2, .LBB0_3
76 ; CHECK-NEXT: # %bb.7: # %bb37
77 ; CHECK-NEXT: .LBB0_8: # %bb22
78 ; CHECK-NEXT: .LBB0_9: # %bb27
79 ; CHECK-NEXT: bc 4, 4*cr3+lt, .LBB0_12
80 ; CHECK-NEXT: # %bb.10: # %bb28
81 ; CHECK-NEXT: .LBB0_11: # %bb35
82 ; CHECK-NEXT: .LBB0_12: # %bb29
83 ; CHECK-NEXT: .LBB0_13: # %bb3
84 ; CHECK-NEXT: .LBB0_14: # %bb2
86 ; CHECK-BE-LABEL: P10_Spill_CR_LT:
87 ; CHECK-BE: # %bb.0: # %bb
88 ; CHECK-BE-NEXT: mfcr r12
89 ; CHECK-BE-NEXT: mflr r0
90 ; CHECK-BE-NEXT: std r0, 16(r1)
91 ; CHECK-BE-NEXT: stw r12, 8(r1)
92 ; CHECK-BE-NEXT: stdu r1, -144(r1)
93 ; CHECK-BE-NEXT: .cfi_def_cfa_offset 144
94 ; CHECK-BE-NEXT: .cfi_offset lr, 16
95 ; CHECK-BE-NEXT: .cfi_offset r28, -32
96 ; CHECK-BE-NEXT: .cfi_offset r29, -24
97 ; CHECK-BE-NEXT: .cfi_offset r30, -16
98 ; CHECK-BE-NEXT: .cfi_offset cr2, 8
99 ; CHECK-BE-NEXT: .cfi_offset cr2, 8
100 ; CHECK-BE-NEXT: .cfi_offset cr2, 8
101 ; CHECK-BE-NEXT: std r28, 112(r1) # 8-byte Folded Spill
102 ; CHECK-BE-NEXT: std r29, 120(r1) # 8-byte Folded Spill
103 ; CHECK-BE-NEXT: std r30, 128(r1) # 8-byte Folded Spill
104 ; CHECK-BE-NEXT: bl call_2
106 ; CHECK-BE-NEXT: bc 12, 4*cr5+lt, .LBB0_13
107 ; CHECK-BE-NEXT: # %bb.1: # %bb
108 ; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_14
109 ; CHECK-BE-NEXT: # %bb.2: # %bb4
110 ; CHECK-BE-NEXT: cmpdi cr3, r3, 0
111 ; CHECK-BE-NEXT: lwz r3, 0(r3)
112 ; CHECK-BE-NEXT: addis r30, r2, call_1@toc@ha
113 ; CHECK-BE-NEXT: # implicit-def: $r29
114 ; CHECK-BE-NEXT: crnot 4*cr3+lt, 4*cr3+eq
115 ; CHECK-BE-NEXT: cmpwi cr4, r3, 0
116 ; CHECK-BE-NEXT: .p2align 4
117 ; CHECK-BE-NEXT: .LBB0_3: # %bb12
119 ; CHECK-BE-NEXT: bl call_3
121 ; CHECK-BE-NEXT: cmpwi r3, 1
122 ; CHECK-BE-NEXT: crnand 4*cr5+lt, eq, 4*cr4+gt
123 ; CHECK-BE-NEXT: bc 4, 4*cr5+lt, .LBB0_8
124 ; CHECK-BE-NEXT: # %bb.4: # %bb23
126 ; CHECK-BE-NEXT: lwz r3, call_1@toc@l(r30)
127 ; CHECK-BE-NEXT: cmplwi r3, 0
128 ; CHECK-BE-NEXT: bne- cr0, .LBB0_9
129 ; CHECK-BE-NEXT: # %bb.5: # %bb30
131 ; CHECK-BE-NEXT: bc 12, 4*cr3+eq, .LBB0_11
132 ; CHECK-BE-NEXT: # %bb.6: # %bb32
134 ; CHECK-BE-NEXT: andi. r3, r29, 2
135 ; CHECK-BE-NEXT: rlwinm r28, r29, 0, 24, 22
136 ; CHECK-BE-NEXT: mcrf cr2, cr0
137 ; CHECK-BE-NEXT: bl call_4
139 ; CHECK-BE-NEXT: mr r29, r28
140 ; CHECK-BE-NEXT: beq+ cr2, .LBB0_3
141 ; CHECK-BE-NEXT: # %bb.7: # %bb37
142 ; CHECK-BE-NEXT: .LBB0_8: # %bb22
143 ; CHECK-BE-NEXT: .LBB0_9: # %bb27
144 ; CHECK-BE-NEXT: bc 4, 4*cr3+lt, .LBB0_12
145 ; CHECK-BE-NEXT: # %bb.10: # %bb28
146 ; CHECK-BE-NEXT: .LBB0_11: # %bb35
147 ; CHECK-BE-NEXT: .LBB0_12: # %bb29
148 ; CHECK-BE-NEXT: .LBB0_13: # %bb3
149 ; CHECK-BE-NEXT: .LBB0_14: # %bb2
151 %tmp = tail call ptr @call_2()
152 %tmp1 = icmp ne ptr %tmp, null
153 switch i32 undef, label %bb4 [
165 %tmp5 = load i64, ptr undef, align 8
166 %tmp6 = trunc i64 %tmp5 to i32
167 %tmp7 = add i32 0, %tmp6
168 %tmp8 = icmp sgt i32 %tmp7, 0
169 %tmp9 = icmp eq i8 0, 0
170 %tmp10 = zext i1 %tmp9 to i32
171 %tmp11 = icmp eq ptr %tmp, null
174 bb12: ; preds = %bb38, %bb4
175 %tmp13 = phi i32 [ %tmp10, %bb4 ], [ undef, %bb38 ]
176 %tmp14 = phi i32 [ undef, %bb4 ], [ %tmp17, %bb38 ]
177 %tmp15 = icmp ne i32 %tmp13, 0
178 %tmp16 = and i32 %tmp14, -257
179 %tmp17 = select i1 %tmp15, i32 %tmp16, i32 undef
182 bb18: ; preds = %bb12
183 %tmp19 = call zeroext i32 @call_3()
184 %tmp20 = icmp eq i32 %tmp19, 1
185 %tmp21 = and i1 %tmp8, %tmp20
186 br i1 %tmp21, label %bb22, label %bb23
188 bb22: ; preds = %bb18
191 bb23: ; preds = %bb18
194 bb24: ; preds = %bb23
195 %tmp25 = load i32, ptr @call_1, align 4
196 %tmp26 = icmp eq i32 %tmp25, 0
197 br i1 %tmp26, label %bb30, label %bb27
199 bb27: ; preds = %bb24
200 br i1 %tmp1, label %bb28, label %bb29
202 bb28: ; preds = %bb27
205 bb29: ; preds = %bb27
208 bb30: ; preds = %bb24
211 bb31: ; preds = %bb30
212 br i1 %tmp11, label %bb35, label %bb32
214 bb32: ; preds = %bb31
215 %tmp33 = and i32 %tmp17, 2
216 %tmp34 = icmp eq i32 %tmp33, 0
220 bb35: ; preds = %bb31
223 bb36: ; preds = %bb32
224 br i1 %tmp34, label %bb38, label %bb37
226 bb37: ; preds = %bb36
229 bb38: ; preds = %bb36