| blob | b540948b20f75692220eda94db65a474dd7b100a |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9,CHECK-PWR9-LE
3 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9,CHECK-PWR9-BE
4 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-PWR78,CHECK-PWR8 -implicit-check-not vabsdu
5 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,CHECK-PWR78,CHECK-PWR7 -implicit-check-not vmaxsd
7 define <4 x i32> @simple_absv_32(<4 x i32> %a) local_unnamed_addr {
8 ; CHECK-PWR9-LABEL: simple_absv_32:
9 ; CHECK-PWR9: # %bb.0: # %entry
10 ; CHECK-PWR9-NEXT: vnegw v3, v2
11 ; CHECK-PWR9-NEXT: vmaxsw v2, v2, v3
12 ; CHECK-PWR9-NEXT: blr
13 ;
14 ; CHECK-PWR78-LABEL: simple_absv_32:
15 ; CHECK-PWR78: # %bb.0: # %entry
16 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
17 ; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2
18 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
19 ; CHECK-PWR78-NEXT: blr
20 entry:
21 %sub.i = sub <4 x i32> zeroinitializer, %a
22 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %a, <4 x i32> %sub.i)
23 ret <4 x i32> %0
24 }
26 define <4 x i32> @simple_absv_32_swap(<4 x i32> %a) local_unnamed_addr {
27 ; CHECK-PWR9-LABEL: simple_absv_32_swap:
28 ; CHECK-PWR9: # %bb.0: # %entry
29 ; CHECK-PWR9-NEXT: vnegw v3, v2
30 ; CHECK-PWR9-NEXT: vmaxsw v2, v2, v3
31 ; CHECK-PWR9-NEXT: blr
32 ;
33 ; CHECK-PWR78-LABEL: simple_absv_32_swap:
34 ; CHECK-PWR78: # %bb.0: # %entry
35 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
36 ; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2
37 ; CHECK-PWR78-NEXT: vmaxsw v2, v3, v2
38 ; CHECK-PWR78-NEXT: blr
39 entry:
40 %sub.i = sub <4 x i32> zeroinitializer, %a
41 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub.i, <4 x i32> %a)
42 ret <4 x i32> %0
43 }
45 define <8 x i16> @simple_absv_16(<8 x i16> %a) local_unnamed_addr {
46 ; CHECK-LABEL: simple_absv_16:
47 ; CHECK: # %bb.0: # %entry
48 ; CHECK-NEXT: xxlxor v3, v3, v3
49 ; CHECK-NEXT: vsubuhm v3, v3, v2
50 ; CHECK-NEXT: vmaxsh v2, v2, v3
51 ; CHECK-NEXT: blr
52 entry:
53 %sub.i = sub <8 x i16> zeroinitializer, %a
54 %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %a, <8 x i16> %sub.i)
55 ret <8 x i16> %0
56 }
58 define <16 x i8> @simple_absv_8(<16 x i8> %a) local_unnamed_addr {
59 ; CHECK-LABEL: simple_absv_8:
60 ; CHECK: # %bb.0: # %entry
61 ; CHECK-NEXT: xxlxor v3, v3, v3
62 ; CHECK-NEXT: vsububm v3, v3, v2
63 ; CHECK-NEXT: vmaxsb v2, v2, v3
64 ; CHECK-NEXT: blr
65 entry:
66 %sub.i = sub <16 x i8> zeroinitializer, %a
67 %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %a, <16 x i8> %sub.i)
68 ret <16 x i8> %0
69 }
71 ; v2i64 vmax isn't avaiable on pwr7
72 define <2 x i64> @sub_absv_64(<2 x i64> %a, <2 x i64> %b) local_unnamed_addr {
73 ; CHECK-PWR9-LABEL: sub_absv_64:
74 ; CHECK-PWR9: # %bb.0: # %entry
75 ; CHECK-PWR9-NEXT: vsubudm v2, v2, v3
76 ; CHECK-PWR9-NEXT: vnegd v3, v2
77 ; CHECK-PWR9-NEXT: vmaxsd v2, v2, v3
78 ; CHECK-PWR9-NEXT: blr
79 ;
80 ; CHECK-PWR8-LABEL: sub_absv_64:
81 ; CHECK-PWR8: # %bb.0: # %entry
82 ; CHECK-PWR8-NEXT: vsubudm v2, v2, v3
83 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
84 ; CHECK-PWR8-NEXT: vsubudm v3, v3, v2
85 ; CHECK-PWR8-NEXT: vmaxsd v2, v2, v3
86 ; CHECK-PWR8-NEXT: blr
87 ;
88 ; CHECK-PWR7-LABEL: sub_absv_64:
89 ; CHECK-PWR7: # %bb.0: # %entry
90 ; CHECK-PWR7-NEXT: addi r3, r1, -48
91 ; CHECK-PWR7-NEXT: stxvd2x v2, 0, r3
92 ; CHECK-PWR7-NEXT: addi r3, r1, -32
93 ; CHECK-PWR7-NEXT: stxvd2x v3, 0, r3
94 ; CHECK-PWR7-NEXT: ld r4, -40(r1)
95 ; CHECK-PWR7-NEXT: ld r5, -24(r1)
96 ; CHECK-PWR7-NEXT: ld r3, -48(r1)
97 ; CHECK-PWR7-NEXT: sub r4, r4, r5
98 ; CHECK-PWR7-NEXT: sradi r5, r4, 63
99 ; CHECK-PWR7-NEXT: xor r4, r4, r5
100 ; CHECK-PWR7-NEXT: sub r4, r4, r5
101 ; CHECK-PWR7-NEXT: ld r5, -32(r1)
102 ; CHECK-PWR7-NEXT: std r4, -8(r1)
103 ; CHECK-PWR7-NEXT: sub r3, r3, r5
104 ; CHECK-PWR7-NEXT: sradi r4, r3, 63
105 ; CHECK-PWR7-NEXT: xor r3, r3, r4
106 ; CHECK-PWR7-NEXT: sub r3, r3, r4
107 ; CHECK-PWR7-NEXT: std r3, -16(r1)
108 ; CHECK-PWR7-NEXT: addi r3, r1, -16
109 ; CHECK-PWR7-NEXT: lxvd2x v2, 0, r3
110 ; CHECK-PWR7-NEXT: blr
111 entry:
112 %0 = sub nsw <2 x i64> %a, %b
113 %1 = icmp sgt <2 x i64> %0, <i64 -1, i64 -1>
114 %2 = sub <2 x i64> zeroinitializer, %0
115 %3 = select <2 x i1> %1, <2 x i64> %0, <2 x i64> %2
116 ret <2 x i64> %3
117 }
119 ; The select pattern can only be detected for v4i32.
120 define <4 x i32> @sub_absv_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
121 ; CHECK-PWR9-LABEL: sub_absv_32:
122 ; CHECK-PWR9: # %bb.0: # %entry
123 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
124 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
125 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
126 ; CHECK-PWR9-NEXT: blr
127 ;
128 ; CHECK-PWR78-LABEL: sub_absv_32:
129 ; CHECK-PWR78: # %bb.0: # %entry
130 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v3
131 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
132 ; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2
133 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
134 ; CHECK-PWR78-NEXT: blr
135 entry:
136 %0 = sub nsw <4 x i32> %a, %b
137 %1 = icmp sgt <4 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1>
138 %2 = sub <4 x i32> zeroinitializer, %0
139 %3 = select <4 x i1> %1, <4 x i32> %0, <4 x i32> %2
140 ret <4 x i32> %3
141 }
143 define <8 x i16> @sub_absv_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
144 ; CHECK-LABEL: sub_absv_16:
145 ; CHECK: # %bb.0: # %entry
146 ; CHECK-NEXT: vsubuhm v2, v2, v3
147 ; CHECK-NEXT: xxlxor v3, v3, v3
148 ; CHECK-NEXT: vsubuhm v3, v3, v2
149 ; CHECK-NEXT: vmaxsh v2, v2, v3
150 ; CHECK-NEXT: blr
151 entry:
152 %0 = sub nsw <8 x i16> %a, %b
153 %1 = icmp sgt <8 x i16> %0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
154 %2 = sub <8 x i16> zeroinitializer, %0
155 %3 = select <8 x i1> %1, <8 x i16> %0, <8 x i16> %2
156 ret <8 x i16> %3
157 }
159 define <16 x i8> @sub_absv_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
160 ; CHECK-LABEL: sub_absv_8:
161 ; CHECK: # %bb.0: # %entry
162 ; CHECK-NEXT: vsububm v2, v2, v3
163 ; CHECK-NEXT: xxlxor v3, v3, v3
164 ; CHECK-NEXT: vsububm v3, v3, v2
165 ; CHECK-NEXT: vmaxsb v2, v2, v3
166 ; CHECK-NEXT: blr
167 entry:
168 %0 = sub nsw <16 x i8> %a, %b
169 %1 = icmp sgt <16 x i8> %0, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
170 %2 = sub <16 x i8> zeroinitializer, %0
171 %3 = select <16 x i1> %1, <16 x i8> %0, <16 x i8> %2
172 ret <16 x i8> %3
173 }
175 define <8 x i16> @sub_absv_16_ext(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
176 ; CHECK-LABEL: sub_absv_16_ext:
177 ; CHECK: # %bb.0: # %entry
178 ; CHECK-NEXT: vminsh v4, v2, v3
179 ; CHECK-NEXT: vmaxsh v2, v2, v3
180 ; CHECK-NEXT: vsubuhm v2, v2, v4
181 ; CHECK-NEXT: blr
182 entry:
183 %0 = sext <8 x i16> %a to <8 x i32>
184 %1 = sext <8 x i16> %b to <8 x i32>
185 %2 = sub nsw <8 x i32> %0, %1
186 %3 = icmp sgt <8 x i32> %2, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
187 %4 = sub nsw <8 x i32> zeroinitializer, %2
188 %5 = select <8 x i1> %3, <8 x i32> %2, <8 x i32> %4
189 %6 = trunc <8 x i32> %5 to <8 x i16>
190 ret <8 x i16> %6
191 }
193 ; FIXME: This does not produce ISD::ABS. This does not even vectorize correctly!
194 ; This function should look like sub_absv_32 and sub_absv_16 except that the type is v16i8.
195 ; Function Attrs: norecurse nounwind readnone
196 define <16 x i8> @sub_absv_8_ext(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
197 ; CHECK-PWR9-LE-LABEL: sub_absv_8_ext:
198 ; CHECK-PWR9-LE: # %bb.0: # %entry
199 ; CHECK-PWR9-LE-NEXT: li r3, 0
200 ; CHECK-PWR9-LE-NEXT: li r5, 2
201 ; CHECK-PWR9-LE-NEXT: li r4, 1
202 ; CHECK-PWR9-LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
203 ; CHECK-PWR9-LE-NEXT: vextubrx r6, r3, v2
204 ; CHECK-PWR9-LE-NEXT: vextubrx r3, r3, v3
205 ; CHECK-PWR9-LE-NEXT: vextubrx r8, r5, v2
206 ; CHECK-PWR9-LE-NEXT: vextubrx r5, r5, v3
207 ; CHECK-PWR9-LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
208 ; CHECK-PWR9-LE-NEXT: std r28, -32(r1) # 8-byte Folded Spill
209 ; CHECK-PWR9-LE-NEXT: std r27, -40(r1) # 8-byte Folded Spill
210 ; CHECK-PWR9-LE-NEXT: std r26, -48(r1) # 8-byte Folded Spill
211 ; CHECK-PWR9-LE-NEXT: std r25, -56(r1) # 8-byte Folded Spill
212 ; CHECK-PWR9-LE-NEXT: clrlwi r6, r6, 24
213 ; CHECK-PWR9-LE-NEXT: clrlwi r3, r3, 24
214 ; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24
215 ; CHECK-PWR9-LE-NEXT: clrlwi r5, r5, 24
216 ; CHECK-PWR9-LE-NEXT: vextubrx r7, r4, v2
217 ; CHECK-PWR9-LE-NEXT: vextubrx r4, r4, v3
218 ; CHECK-PWR9-LE-NEXT: sub r3, r6, r3
219 ; CHECK-PWR9-LE-NEXT: sub r6, r8, r5
220 ; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24
221 ; CHECK-PWR9-LE-NEXT: clrlwi r4, r4, 24
222 ; CHECK-PWR9-LE-NEXT: sub r4, r7, r4
223 ; CHECK-PWR9-LE-NEXT: srawi r5, r3, 31
224 ; CHECK-PWR9-LE-NEXT: srawi r7, r4, 31
225 ; CHECK-PWR9-LE-NEXT: xor r3, r3, r5
226 ; CHECK-PWR9-LE-NEXT: xor r4, r4, r7
227 ; CHECK-PWR9-LE-NEXT: sub r5, r3, r5
228 ; CHECK-PWR9-LE-NEXT: srawi r3, r6, 31
229 ; CHECK-PWR9-LE-NEXT: sub r4, r4, r7
230 ; CHECK-PWR9-LE-NEXT: xor r6, r6, r3
231 ; CHECK-PWR9-LE-NEXT: sub r3, r6, r3
232 ; CHECK-PWR9-LE-NEXT: li r6, 3
233 ; CHECK-PWR9-LE-NEXT: vextubrx r7, r6, v2
234 ; CHECK-PWR9-LE-NEXT: vextubrx r6, r6, v3
235 ; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24
236 ; CHECK-PWR9-LE-NEXT: clrlwi r6, r6, 24
237 ; CHECK-PWR9-LE-NEXT: sub r6, r7, r6
238 ; CHECK-PWR9-LE-NEXT: srawi r7, r6, 31
239 ; CHECK-PWR9-LE-NEXT: xor r6, r6, r7
240 ; CHECK-PWR9-LE-NEXT: sub r6, r6, r7
241 ; CHECK-PWR9-LE-NEXT: li r7, 4
242 ; CHECK-PWR9-LE-NEXT: vextubrx r8, r7, v2
243 ; CHECK-PWR9-LE-NEXT: vextubrx r7, r7, v3
244 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r6
245 ; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24
246 ; CHECK-PWR9-LE-NEXT: clrlwi r7, r7, 24
247 ; CHECK-PWR9-LE-NEXT: sub r7, r8, r7
248 ; CHECK-PWR9-LE-NEXT: srawi r8, r7, 31
249 ; CHECK-PWR9-LE-NEXT: xor r7, r7, r8
250 ; CHECK-PWR9-LE-NEXT: sub r7, r7, r8
251 ; CHECK-PWR9-LE-NEXT: li r8, 5
252 ; CHECK-PWR9-LE-NEXT: vextubrx r9, r8, v2
253 ; CHECK-PWR9-LE-NEXT: vextubrx r8, r8, v3
254 ; CHECK-PWR9-LE-NEXT: clrlwi r9, r9, 24
255 ; CHECK-PWR9-LE-NEXT: clrlwi r8, r8, 24
256 ; CHECK-PWR9-LE-NEXT: sub r8, r9, r8
257 ; CHECK-PWR9-LE-NEXT: srawi r9, r8, 31
258 ; CHECK-PWR9-LE-NEXT: xor r8, r8, r9
259 ; CHECK-PWR9-LE-NEXT: sub r8, r8, r9
260 ; CHECK-PWR9-LE-NEXT: li r9, 6
261 ; CHECK-PWR9-LE-NEXT: vextubrx r10, r9, v2
262 ; CHECK-PWR9-LE-NEXT: vextubrx r9, r9, v3
263 ; CHECK-PWR9-LE-NEXT: clrlwi r10, r10, 24
264 ; CHECK-PWR9-LE-NEXT: clrlwi r9, r9, 24
265 ; CHECK-PWR9-LE-NEXT: sub r9, r10, r9
266 ; CHECK-PWR9-LE-NEXT: srawi r10, r9, 31
267 ; CHECK-PWR9-LE-NEXT: xor r9, r9, r10
268 ; CHECK-PWR9-LE-NEXT: sub r9, r9, r10
269 ; CHECK-PWR9-LE-NEXT: li r10, 7
270 ; CHECK-PWR9-LE-NEXT: vextubrx r11, r10, v2
271 ; CHECK-PWR9-LE-NEXT: vextubrx r10, r10, v3
272 ; CHECK-PWR9-LE-NEXT: clrlwi r11, r11, 24
273 ; CHECK-PWR9-LE-NEXT: clrlwi r10, r10, 24
274 ; CHECK-PWR9-LE-NEXT: sub r10, r11, r10
275 ; CHECK-PWR9-LE-NEXT: srawi r11, r10, 31
276 ; CHECK-PWR9-LE-NEXT: xor r10, r10, r11
277 ; CHECK-PWR9-LE-NEXT: sub r10, r10, r11
278 ; CHECK-PWR9-LE-NEXT: li r11, 8
279 ; CHECK-PWR9-LE-NEXT: vextubrx r12, r11, v2
280 ; CHECK-PWR9-LE-NEXT: vextubrx r11, r11, v3
281 ; CHECK-PWR9-LE-NEXT: mtvsrd v5, r10
282 ; CHECK-PWR9-LE-NEXT: clrlwi r12, r12, 24
283 ; CHECK-PWR9-LE-NEXT: clrlwi r11, r11, 24
284 ; CHECK-PWR9-LE-NEXT: sub r11, r12, r11
285 ; CHECK-PWR9-LE-NEXT: srawi r12, r11, 31
286 ; CHECK-PWR9-LE-NEXT: xor r11, r11, r12
287 ; CHECK-PWR9-LE-NEXT: sub r11, r11, r12
288 ; CHECK-PWR9-LE-NEXT: li r12, 9
289 ; CHECK-PWR9-LE-NEXT: vextubrx r0, r12, v2
290 ; CHECK-PWR9-LE-NEXT: vextubrx r12, r12, v3
291 ; CHECK-PWR9-LE-NEXT: clrlwi r0, r0, 24
292 ; CHECK-PWR9-LE-NEXT: clrlwi r12, r12, 24
293 ; CHECK-PWR9-LE-NEXT: sub r12, r0, r12
294 ; CHECK-PWR9-LE-NEXT: srawi r0, r12, 31
295 ; CHECK-PWR9-LE-NEXT: xor r12, r12, r0
296 ; CHECK-PWR9-LE-NEXT: sub r12, r12, r0
297 ; CHECK-PWR9-LE-NEXT: li r0, 10
298 ; CHECK-PWR9-LE-NEXT: vextubrx r30, r0, v2
299 ; CHECK-PWR9-LE-NEXT: vextubrx r0, r0, v3
300 ; CHECK-PWR9-LE-NEXT: clrlwi r30, r30, 24
301 ; CHECK-PWR9-LE-NEXT: clrlwi r0, r0, 24
302 ; CHECK-PWR9-LE-NEXT: sub r0, r30, r0
303 ; CHECK-PWR9-LE-NEXT: srawi r30, r0, 31
304 ; CHECK-PWR9-LE-NEXT: xor r0, r0, r30
305 ; CHECK-PWR9-LE-NEXT: sub r0, r0, r30
306 ; CHECK-PWR9-LE-NEXT: li r30, 11
307 ; CHECK-PWR9-LE-NEXT: vextubrx r29, r30, v2
308 ; CHECK-PWR9-LE-NEXT: vextubrx r30, r30, v3
309 ; CHECK-PWR9-LE-NEXT: clrlwi r29, r29, 24
310 ; CHECK-PWR9-LE-NEXT: clrlwi r30, r30, 24
311 ; CHECK-PWR9-LE-NEXT: sub r30, r29, r30
312 ; CHECK-PWR9-LE-NEXT: srawi r29, r30, 31
313 ; CHECK-PWR9-LE-NEXT: xor r30, r30, r29
314 ; CHECK-PWR9-LE-NEXT: sub r30, r30, r29
315 ; CHECK-PWR9-LE-NEXT: li r29, 12
316 ; CHECK-PWR9-LE-NEXT: vextubrx r28, r29, v2
317 ; CHECK-PWR9-LE-NEXT: vextubrx r29, r29, v3
318 ; CHECK-PWR9-LE-NEXT: clrlwi r28, r28, 24
319 ; CHECK-PWR9-LE-NEXT: clrlwi r29, r29, 24
320 ; CHECK-PWR9-LE-NEXT: sub r29, r28, r29
321 ; CHECK-PWR9-LE-NEXT: srawi r28, r29, 31
322 ; CHECK-PWR9-LE-NEXT: xor r29, r29, r28
323 ; CHECK-PWR9-LE-NEXT: sub r29, r29, r28
324 ; CHECK-PWR9-LE-NEXT: li r28, 13
325 ; CHECK-PWR9-LE-NEXT: vextubrx r27, r28, v2
326 ; CHECK-PWR9-LE-NEXT: vextubrx r28, r28, v3
327 ; CHECK-PWR9-LE-NEXT: clrlwi r27, r27, 24
328 ; CHECK-PWR9-LE-NEXT: clrlwi r28, r28, 24
329 ; CHECK-PWR9-LE-NEXT: sub r28, r27, r28
330 ; CHECK-PWR9-LE-NEXT: srawi r27, r28, 31
331 ; CHECK-PWR9-LE-NEXT: xor r28, r28, r27
332 ; CHECK-PWR9-LE-NEXT: sub r28, r28, r27
333 ; CHECK-PWR9-LE-NEXT: li r27, 14
334 ; CHECK-PWR9-LE-NEXT: vextubrx r26, r27, v2
335 ; CHECK-PWR9-LE-NEXT: vextubrx r27, r27, v3
336 ; CHECK-PWR9-LE-NEXT: clrlwi r26, r26, 24
337 ; CHECK-PWR9-LE-NEXT: clrlwi r27, r27, 24
338 ; CHECK-PWR9-LE-NEXT: sub r27, r26, r27
339 ; CHECK-PWR9-LE-NEXT: srawi r26, r27, 31
340 ; CHECK-PWR9-LE-NEXT: xor r27, r27, r26
341 ; CHECK-PWR9-LE-NEXT: sub r27, r27, r26
342 ; CHECK-PWR9-LE-NEXT: li r26, 15
343 ; CHECK-PWR9-LE-NEXT: vextubrx r25, r26, v2
344 ; CHECK-PWR9-LE-NEXT: vextubrx r26, r26, v3
345 ; CHECK-PWR9-LE-NEXT: mtvsrd v2, r5
346 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r4
347 ; CHECK-PWR9-LE-NEXT: vmrghb v2, v3, v2
348 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r3
349 ; CHECK-PWR9-LE-NEXT: clrlwi r25, r25, 24
350 ; CHECK-PWR9-LE-NEXT: clrlwi r26, r26, 24
351 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
352 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r8
353 ; CHECK-PWR9-LE-NEXT: sub r26, r25, r26
354 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2
355 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r7
356 ; CHECK-PWR9-LE-NEXT: srawi r25, r26, 31
357 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
358 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r9
359 ; CHECK-PWR9-LE-NEXT: xor r26, r26, r25
360 ; CHECK-PWR9-LE-NEXT: vmrghb v4, v5, v4
361 ; CHECK-PWR9-LE-NEXT: sub r26, r26, r25
362 ; CHECK-PWR9-LE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
363 ; CHECK-PWR9-LE-NEXT: mtvsrd v5, r26
364 ; CHECK-PWR9-LE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
365 ; CHECK-PWR9-LE-NEXT: vmrglh v3, v4, v3
366 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r30
367 ; CHECK-PWR9-LE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
368 ; CHECK-PWR9-LE-NEXT: xxmrglw vs0, v3, v2
369 ; CHECK-PWR9-LE-NEXT: mtvsrd v2, r11
370 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r12
371 ; CHECK-PWR9-LE-NEXT: vmrghb v2, v3, v2
372 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r0
373 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
374 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r28
375 ; CHECK-PWR9-LE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
376 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2
377 ; CHECK-PWR9-LE-NEXT: mtvsrd v3, r29
378 ; CHECK-PWR9-LE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
379 ; CHECK-PWR9-LE-NEXT: vmrghb v3, v4, v3
380 ; CHECK-PWR9-LE-NEXT: mtvsrd v4, r27
381 ; CHECK-PWR9-LE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
382 ; CHECK-PWR9-LE-NEXT: vmrghb v4, v5, v4
383 ; CHECK-PWR9-LE-NEXT: vmrglh v3, v4, v3
384 ; CHECK-PWR9-LE-NEXT: xxmrglw vs1, v3, v2
385 ; CHECK-PWR9-LE-NEXT: xxmrgld v2, vs1, vs0
386 ; CHECK-PWR9-LE-NEXT: blr
387 ;
388 ; CHECK-PWR9-BE-LABEL: sub_absv_8_ext:
389 ; CHECK-PWR9-BE: # %bb.0: # %entry
390 ; CHECK-PWR9-BE-NEXT: li r3, 0
391 ; CHECK-PWR9-BE-NEXT: li r4, 1
392 ; CHECK-PWR9-BE-NEXT: li r5, 2
393 ; CHECK-PWR9-BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
394 ; CHECK-PWR9-BE-NEXT: vextublx r6, r3, v2
395 ; CHECK-PWR9-BE-NEXT: vextublx r3, r3, v3
396 ; CHECK-PWR9-BE-NEXT: vextublx r7, r4, v2
397 ; CHECK-PWR9-BE-NEXT: vextublx r4, r4, v3
398 ; CHECK-PWR9-BE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
399 ; CHECK-PWR9-BE-NEXT: std r28, -32(r1) # 8-byte Folded Spill
400 ; CHECK-PWR9-BE-NEXT: std r27, -40(r1) # 8-byte Folded Spill
401 ; CHECK-PWR9-BE-NEXT: std r26, -48(r1) # 8-byte Folded Spill
402 ; CHECK-PWR9-BE-NEXT: std r25, -56(r1) # 8-byte Folded Spill
403 ; CHECK-PWR9-BE-NEXT: clrlwi r6, r6, 24
404 ; CHECK-PWR9-BE-NEXT: clrlwi r3, r3, 24
405 ; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24
406 ; CHECK-PWR9-BE-NEXT: clrlwi r4, r4, 24
407 ; CHECK-PWR9-BE-NEXT: vextublx r8, r5, v2
408 ; CHECK-PWR9-BE-NEXT: vextublx r5, r5, v3
409 ; CHECK-PWR9-BE-NEXT: sub r3, r6, r3
410 ; CHECK-PWR9-BE-NEXT: sub r4, r7, r4
411 ; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24
412 ; CHECK-PWR9-BE-NEXT: clrlwi r5, r5, 24
413 ; CHECK-PWR9-BE-NEXT: sub r5, r8, r5
414 ; CHECK-PWR9-BE-NEXT: srawi r6, r3, 31
415 ; CHECK-PWR9-BE-NEXT: srawi r7, r4, 31
416 ; CHECK-PWR9-BE-NEXT: srawi r8, r5, 31
417 ; CHECK-PWR9-BE-NEXT: xor r3, r3, r6
418 ; CHECK-PWR9-BE-NEXT: xor r4, r4, r7
419 ; CHECK-PWR9-BE-NEXT: xor r5, r5, r8
420 ; CHECK-PWR9-BE-NEXT: sub r3, r3, r6
421 ; CHECK-PWR9-BE-NEXT: li r6, 3
422 ; CHECK-PWR9-BE-NEXT: sub r4, r4, r7
423 ; CHECK-PWR9-BE-NEXT: sub r5, r5, r8
424 ; CHECK-PWR9-BE-NEXT: vextublx r7, r6, v2
425 ; CHECK-PWR9-BE-NEXT: vextublx r6, r6, v3
426 ; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24
427 ; CHECK-PWR9-BE-NEXT: clrlwi r6, r6, 24
428 ; CHECK-PWR9-BE-NEXT: sub r6, r7, r6
429 ; CHECK-PWR9-BE-NEXT: srawi r7, r6, 31
430 ; CHECK-PWR9-BE-NEXT: xor r6, r6, r7
431 ; CHECK-PWR9-BE-NEXT: sub r6, r6, r7
432 ; CHECK-PWR9-BE-NEXT: li r7, 4
433 ; CHECK-PWR9-BE-NEXT: vextublx r8, r7, v2
434 ; CHECK-PWR9-BE-NEXT: vextublx r7, r7, v3
435 ; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24
436 ; CHECK-PWR9-BE-NEXT: clrlwi r7, r7, 24
437 ; CHECK-PWR9-BE-NEXT: sub r7, r8, r7
438 ; CHECK-PWR9-BE-NEXT: srawi r8, r7, 31
439 ; CHECK-PWR9-BE-NEXT: xor r7, r7, r8
440 ; CHECK-PWR9-BE-NEXT: sub r7, r7, r8
441 ; CHECK-PWR9-BE-NEXT: li r8, 5
442 ; CHECK-PWR9-BE-NEXT: vextublx r9, r8, v2
443 ; CHECK-PWR9-BE-NEXT: vextublx r8, r8, v3
444 ; CHECK-PWR9-BE-NEXT: clrlwi r9, r9, 24
445 ; CHECK-PWR9-BE-NEXT: clrlwi r8, r8, 24
446 ; CHECK-PWR9-BE-NEXT: sub r8, r9, r8
447 ; CHECK-PWR9-BE-NEXT: srawi r9, r8, 31
448 ; CHECK-PWR9-BE-NEXT: xor r8, r8, r9
449 ; CHECK-PWR9-BE-NEXT: sub r8, r8, r9
450 ; CHECK-PWR9-BE-NEXT: li r9, 6
451 ; CHECK-PWR9-BE-NEXT: vextublx r10, r9, v2
452 ; CHECK-PWR9-BE-NEXT: vextublx r9, r9, v3
453 ; CHECK-PWR9-BE-NEXT: clrlwi r10, r10, 24
454 ; CHECK-PWR9-BE-NEXT: clrlwi r9, r9, 24
455 ; CHECK-PWR9-BE-NEXT: sub r9, r10, r9
456 ; CHECK-PWR9-BE-NEXT: srawi r10, r9, 31
457 ; CHECK-PWR9-BE-NEXT: xor r9, r9, r10
458 ; CHECK-PWR9-BE-NEXT: sub r9, r9, r10
459 ; CHECK-PWR9-BE-NEXT: li r10, 7
460 ; CHECK-PWR9-BE-NEXT: vextublx r11, r10, v2
461 ; CHECK-PWR9-BE-NEXT: vextublx r10, r10, v3
462 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r9
463 ; CHECK-PWR9-BE-NEXT: clrlwi r11, r11, 24
464 ; CHECK-PWR9-BE-NEXT: clrlwi r10, r10, 24
465 ; CHECK-PWR9-BE-NEXT: sub r10, r11, r10
466 ; CHECK-PWR9-BE-NEXT: srawi r11, r10, 31
467 ; CHECK-PWR9-BE-NEXT: xor r10, r10, r11
468 ; CHECK-PWR9-BE-NEXT: sub r10, r10, r11
469 ; CHECK-PWR9-BE-NEXT: li r11, 8
470 ; CHECK-PWR9-BE-NEXT: vextublx r12, r11, v2
471 ; CHECK-PWR9-BE-NEXT: vextublx r11, r11, v3
472 ; CHECK-PWR9-BE-NEXT: clrlwi r12, r12, 24
473 ; CHECK-PWR9-BE-NEXT: clrlwi r11, r11, 24
474 ; CHECK-PWR9-BE-NEXT: sub r11, r12, r11
475 ; CHECK-PWR9-BE-NEXT: srawi r12, r11, 31
476 ; CHECK-PWR9-BE-NEXT: xor r11, r11, r12
477 ; CHECK-PWR9-BE-NEXT: sub r11, r11, r12
478 ; CHECK-PWR9-BE-NEXT: li r12, 9
479 ; CHECK-PWR9-BE-NEXT: vextublx r0, r12, v2
480 ; CHECK-PWR9-BE-NEXT: vextublx r12, r12, v3
481 ; CHECK-PWR9-BE-NEXT: clrlwi r0, r0, 24
482 ; CHECK-PWR9-BE-NEXT: clrlwi r12, r12, 24
483 ; CHECK-PWR9-BE-NEXT: sub r12, r0, r12
484 ; CHECK-PWR9-BE-NEXT: srawi r0, r12, 31
485 ; CHECK-PWR9-BE-NEXT: xor r12, r12, r0
486 ; CHECK-PWR9-BE-NEXT: sub r12, r12, r0
487 ; CHECK-PWR9-BE-NEXT: li r0, 10
488 ; CHECK-PWR9-BE-NEXT: vextublx r30, r0, v2
489 ; CHECK-PWR9-BE-NEXT: vextublx r0, r0, v3
490 ; CHECK-PWR9-BE-NEXT: mtvsrwz v4, r12
491 ; CHECK-PWR9-BE-NEXT: clrlwi r30, r30, 24
492 ; CHECK-PWR9-BE-NEXT: clrlwi r0, r0, 24
493 ; CHECK-PWR9-BE-NEXT: sub r0, r30, r0
494 ; CHECK-PWR9-BE-NEXT: srawi r30, r0, 31
495 ; CHECK-PWR9-BE-NEXT: xor r0, r0, r30
496 ; CHECK-PWR9-BE-NEXT: sub r0, r0, r30
497 ; CHECK-PWR9-BE-NEXT: li r30, 11
498 ; CHECK-PWR9-BE-NEXT: vextublx r29, r30, v2
499 ; CHECK-PWR9-BE-NEXT: vextublx r30, r30, v3
500 ; CHECK-PWR9-BE-NEXT: clrlwi r29, r29, 24
501 ; CHECK-PWR9-BE-NEXT: clrlwi r30, r30, 24
502 ; CHECK-PWR9-BE-NEXT: sub r30, r29, r30
503 ; CHECK-PWR9-BE-NEXT: srawi r29, r30, 31
504 ; CHECK-PWR9-BE-NEXT: xor r30, r30, r29
505 ; CHECK-PWR9-BE-NEXT: sub r30, r30, r29
506 ; CHECK-PWR9-BE-NEXT: li r29, 12
507 ; CHECK-PWR9-BE-NEXT: vextublx r28, r29, v2
508 ; CHECK-PWR9-BE-NEXT: vextublx r29, r29, v3
509 ; CHECK-PWR9-BE-NEXT: clrlwi r28, r28, 24
510 ; CHECK-PWR9-BE-NEXT: clrlwi r29, r29, 24
511 ; CHECK-PWR9-BE-NEXT: sub r29, r28, r29
512 ; CHECK-PWR9-BE-NEXT: srawi r28, r29, 31
513 ; CHECK-PWR9-BE-NEXT: xor r29, r29, r28
514 ; CHECK-PWR9-BE-NEXT: sub r29, r29, r28
515 ; CHECK-PWR9-BE-NEXT: li r28, 13
516 ; CHECK-PWR9-BE-NEXT: vextublx r27, r28, v2
517 ; CHECK-PWR9-BE-NEXT: vextublx r28, r28, v3
518 ; CHECK-PWR9-BE-NEXT: clrlwi r27, r27, 24
519 ; CHECK-PWR9-BE-NEXT: clrlwi r28, r28, 24
520 ; CHECK-PWR9-BE-NEXT: sub r28, r27, r28
521 ; CHECK-PWR9-BE-NEXT: srawi r27, r28, 31
522 ; CHECK-PWR9-BE-NEXT: xor r28, r28, r27
523 ; CHECK-PWR9-BE-NEXT: sub r28, r28, r27
524 ; CHECK-PWR9-BE-NEXT: li r27, 14
525 ; CHECK-PWR9-BE-NEXT: vextublx r26, r27, v2
526 ; CHECK-PWR9-BE-NEXT: vextublx r27, r27, v3
527 ; CHECK-PWR9-BE-NEXT: clrlwi r26, r26, 24
528 ; CHECK-PWR9-BE-NEXT: clrlwi r27, r27, 24
529 ; CHECK-PWR9-BE-NEXT: sub r27, r26, r27
530 ; CHECK-PWR9-BE-NEXT: srawi r26, r27, 31
531 ; CHECK-PWR9-BE-NEXT: xor r27, r27, r26
532 ; CHECK-PWR9-BE-NEXT: sub r27, r27, r26
533 ; CHECK-PWR9-BE-NEXT: li r26, 15
534 ; CHECK-PWR9-BE-NEXT: vextublx r25, r26, v2
535 ; CHECK-PWR9-BE-NEXT: vextublx r26, r26, v3
536 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r27
537 ; CHECK-PWR9-BE-NEXT: addis r27, r2, .LCPI9_0@toc@ha
538 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r28
539 ; CHECK-PWR9-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
540 ; CHECK-PWR9-BE-NEXT: addi r27, r27, .LCPI9_0@toc@l
541 ; CHECK-PWR9-BE-NEXT: clrlwi r25, r25, 24
542 ; CHECK-PWR9-BE-NEXT: clrlwi r26, r26, 24
543 ; CHECK-PWR9-BE-NEXT: lxv vs1, 0(r27)
544 ; CHECK-PWR9-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
545 ; CHECK-PWR9-BE-NEXT: sub r26, r25, r26
546 ; CHECK-PWR9-BE-NEXT: srawi r25, r26, 31
547 ; CHECK-PWR9-BE-NEXT: xor r26, r26, r25
548 ; CHECK-PWR9-BE-NEXT: sub r26, r26, r25
549 ; CHECK-PWR9-BE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
550 ; CHECK-PWR9-BE-NEXT: mtvsrwz v2, r26
551 ; CHECK-PWR9-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
552 ; CHECK-PWR9-BE-NEXT: xxperm v2, vs0, vs1
553 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r29
554 ; CHECK-PWR9-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
555 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs0, vs1
556 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r0
557 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2
558 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r30
559 ; CHECK-PWR9-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
560 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs0, vs1
561 ; CHECK-PWR9-BE-NEXT: mtfprwz f0, r11
562 ; CHECK-PWR9-BE-NEXT: xxperm v4, vs0, vs1
563 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3
564 ; CHECK-PWR9-BE-NEXT: mtvsrwz v4, r4
565 ; CHECK-PWR9-BE-NEXT: xxmrghw vs0, v3, v2
566 ; CHECK-PWR9-BE-NEXT: mtvsrwz v2, r10
567 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r8
568 ; CHECK-PWR9-BE-NEXT: xxperm v2, vs2, vs1
569 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r7
570 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs2, vs1
571 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r5
572 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2
573 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r6
574 ; CHECK-PWR9-BE-NEXT: xxperm v3, vs2, vs1
575 ; CHECK-PWR9-BE-NEXT: mtfprwz f2, r3
576 ; CHECK-PWR9-BE-NEXT: xxperm v4, vs2, vs1
577 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3
578 ; CHECK-PWR9-BE-NEXT: xxmrghw vs1, v3, v2
579 ; CHECK-PWR9-BE-NEXT: xxmrghd v2, vs1, vs0
580 ; CHECK-PWR9-BE-NEXT: blr
581 ;
582 ; CHECK-PWR8-LABEL: sub_absv_8_ext:
583 ; CHECK-PWR8: # %bb.0: # %entry
584 ; CHECK-PWR8-NEXT: xxswapd vs0, v2
585 ; CHECK-PWR8-NEXT: xxswapd vs1, v3
586 ; CHECK-PWR8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
587 ; CHECK-PWR8-NEXT: std r28, -32(r1) # 8-byte Folded Spill
588 ; CHECK-PWR8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
589 ; CHECK-PWR8-NEXT: std r26, -48(r1) # 8-byte Folded Spill
590 ; CHECK-PWR8-NEXT: mffprd r11, f0
591 ; CHECK-PWR8-NEXT: mffprd r8, f1
592 ; CHECK-PWR8-NEXT: std r27, -40(r1) # 8-byte Folded Spill
593 ; CHECK-PWR8-NEXT: std r25, -56(r1) # 8-byte Folded Spill
594 ; CHECK-PWR8-NEXT: clrldi r3, r11, 56
595 ; CHECK-PWR8-NEXT: clrldi r4, r8, 56
596 ; CHECK-PWR8-NEXT: rldicl r5, r11, 56, 56
597 ; CHECK-PWR8-NEXT: rldicl r6, r8, 56, 56
598 ; CHECK-PWR8-NEXT: rldicl r7, r11, 48, 56
599 ; CHECK-PWR8-NEXT: rldicl r9, r8, 48, 56
600 ; CHECK-PWR8-NEXT: rldicl r0, r11, 32, 56
601 ; CHECK-PWR8-NEXT: rldicl r30, r8, 32, 56
602 ; CHECK-PWR8-NEXT: rldicl r29, r11, 24, 56
603 ; CHECK-PWR8-NEXT: rldicl r28, r8, 24, 56
604 ; CHECK-PWR8-NEXT: rldicl r10, r11, 40, 56
605 ; CHECK-PWR8-NEXT: rldicl r12, r8, 40, 56
606 ; CHECK-PWR8-NEXT: rldicl r27, r11, 16, 56
607 ; CHECK-PWR8-NEXT: rldicl r11, r11, 8, 56
608 ; CHECK-PWR8-NEXT: std r24, -64(r1) # 8-byte Folded Spill
609 ; CHECK-PWR8-NEXT: clrlwi r3, r3, 24
610 ; CHECK-PWR8-NEXT: clrlwi r4, r4, 24
611 ; CHECK-PWR8-NEXT: clrlwi r5, r5, 24
612 ; CHECK-PWR8-NEXT: clrlwi r6, r6, 24
613 ; CHECK-PWR8-NEXT: clrlwi r7, r7, 24
614 ; CHECK-PWR8-NEXT: clrlwi r9, r9, 24
615 ; CHECK-PWR8-NEXT: sub r3, r3, r4
616 ; CHECK-PWR8-NEXT: clrlwi r0, r0, 24
617 ; CHECK-PWR8-NEXT: clrlwi r30, r30, 24
618 ; CHECK-PWR8-NEXT: sub r4, r5, r6
619 ; CHECK-PWR8-NEXT: sub r5, r7, r9
620 ; CHECK-PWR8-NEXT: clrlwi r29, r29, 24
621 ; CHECK-PWR8-NEXT: clrlwi r28, r28, 24
622 ; CHECK-PWR8-NEXT: sub r7, r0, r30
623 ; CHECK-PWR8-NEXT: sub r9, r29, r28
624 ; CHECK-PWR8-NEXT: clrlwi r10, r10, 24
625 ; CHECK-PWR8-NEXT: clrlwi r12, r12, 24
626 ; CHECK-PWR8-NEXT: sub r6, r10, r12
627 ; CHECK-PWR8-NEXT: clrlwi r27, r27, 24
628 ; CHECK-PWR8-NEXT: clrlwi r11, r11, 24
629 ; CHECK-PWR8-NEXT: srawi r0, r5, 31
630 ; CHECK-PWR8-NEXT: srawi r29, r7, 31
631 ; CHECK-PWR8-NEXT: srawi r12, r4, 31
632 ; CHECK-PWR8-NEXT: srawi r28, r9, 31
633 ; CHECK-PWR8-NEXT: srawi r30, r6, 31
634 ; CHECK-PWR8-NEXT: srawi r10, r3, 31
635 ; CHECK-PWR8-NEXT: xor r5, r5, r0
636 ; CHECK-PWR8-NEXT: xor r26, r7, r29
637 ; CHECK-PWR8-NEXT: sub r7, r5, r0
638 ; CHECK-PWR8-NEXT: rldicl r5, r8, 16, 56
639 ; CHECK-PWR8-NEXT: rldicl r8, r8, 8, 56
640 ; CHECK-PWR8-NEXT: xor r4, r4, r12
641 ; CHECK-PWR8-NEXT: xor r25, r9, r28
642 ; CHECK-PWR8-NEXT: sub r9, r4, r12
643 ; CHECK-PWR8-NEXT: sub r4, r26, r29
644 ; CHECK-PWR8-NEXT: mtvsrd v1, r9
645 ; CHECK-PWR8-NEXT: clrlwi r5, r5, 24
646 ; CHECK-PWR8-NEXT: sub r5, r27, r5
647 ; CHECK-PWR8-NEXT: clrlwi r8, r8, 24
648 ; CHECK-PWR8-NEXT: sub r8, r11, r8
649 ; CHECK-PWR8-NEXT: xor r6, r6, r30
650 ; CHECK-PWR8-NEXT: sub r6, r6, r30
651 ; CHECK-PWR8-NEXT: xor r3, r3, r10
652 ; CHECK-PWR8-NEXT: sub r10, r3, r10
653 ; CHECK-PWR8-NEXT: sub r3, r25, r28
654 ; CHECK-PWR8-NEXT: mtvsrd v6, r6
655 ; CHECK-PWR8-NEXT: mtvsrd v7, r3
656 ; CHECK-PWR8-NEXT: srawi r12, r5, 31
657 ; CHECK-PWR8-NEXT: srawi r11, r8, 31
658 ; CHECK-PWR8-NEXT: xor r5, r5, r12
659 ; CHECK-PWR8-NEXT: xor r8, r8, r11
660 ; CHECK-PWR8-NEXT: sub r5, r5, r12
661 ; CHECK-PWR8-NEXT: sub r8, r8, r11
662 ; CHECK-PWR8-NEXT: mfvsrd r11, v2
663 ; CHECK-PWR8-NEXT: mfvsrd r12, v3
664 ; CHECK-PWR8-NEXT: mtvsrd v8, r8
665 ; CHECK-PWR8-NEXT: clrldi r0, r11, 56
666 ; CHECK-PWR8-NEXT: clrldi r30, r12, 56
667 ; CHECK-PWR8-NEXT: rldicl r29, r12, 56, 56
668 ; CHECK-PWR8-NEXT: rldicl r28, r12, 48, 56
669 ; CHECK-PWR8-NEXT: rldicl r27, r12, 40, 56
670 ; CHECK-PWR8-NEXT: rldicl r26, r12, 32, 56
671 ; CHECK-PWR8-NEXT: rldicl r25, r12, 24, 56
672 ; CHECK-PWR8-NEXT: rldicl r24, r12, 16, 56
673 ; CHECK-PWR8-NEXT: rldicl r12, r12, 8, 56
674 ; CHECK-PWR8-NEXT: clrlwi r0, r0, 24
675 ; CHECK-PWR8-NEXT: clrlwi r30, r30, 24
676 ; CHECK-PWR8-NEXT: clrlwi r29, r29, 24
677 ; CHECK-PWR8-NEXT: clrlwi r28, r28, 24
678 ; CHECK-PWR8-NEXT: clrlwi r27, r27, 24
679 ; CHECK-PWR8-NEXT: clrlwi r26, r26, 24
680 ; CHECK-PWR8-NEXT: clrlwi r25, r25, 24
681 ; CHECK-PWR8-NEXT: clrlwi r24, r24, 24
682 ; CHECK-PWR8-NEXT: clrlwi r12, r12, 24
683 ; CHECK-PWR8-NEXT: sub r0, r0, r30
684 ; CHECK-PWR8-NEXT: srawi r30, r0, 31
685 ; CHECK-PWR8-NEXT: xor r0, r0, r30
686 ; CHECK-PWR8-NEXT: sub r0, r0, r30
687 ; CHECK-PWR8-NEXT: rldicl r30, r11, 56, 56
688 ; CHECK-PWR8-NEXT: clrlwi r30, r30, 24
689 ; CHECK-PWR8-NEXT: mtvsrd v2, r0
690 ; CHECK-PWR8-NEXT: sub r30, r30, r29
691 ; CHECK-PWR8-NEXT: srawi r29, r30, 31
692 ; CHECK-PWR8-NEXT: xor r30, r30, r29
693 ; CHECK-PWR8-NEXT: sub r30, r30, r29
694 ; CHECK-PWR8-NEXT: rldicl r29, r11, 48, 56
695 ; CHECK-PWR8-NEXT: clrlwi r29, r29, 24
696 ; CHECK-PWR8-NEXT: mtvsrd v3, r30
697 ; CHECK-PWR8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
698 ; CHECK-PWR8-NEXT: sub r29, r29, r28
699 ; CHECK-PWR8-NEXT: srawi r28, r29, 31
700 ; CHECK-PWR8-NEXT: xor r29, r29, r28
701 ; CHECK-PWR8-NEXT: sub r29, r29, r28
702 ; CHECK-PWR8-NEXT: rldicl r28, r11, 40, 56
703 ; CHECK-PWR8-NEXT: clrlwi r28, r28, 24
704 ; CHECK-PWR8-NEXT: sub r28, r28, r27
705 ; CHECK-PWR8-NEXT: srawi r27, r28, 31
706 ; CHECK-PWR8-NEXT: xor r28, r28, r27
707 ; CHECK-PWR8-NEXT: sub r28, r28, r27
708 ; CHECK-PWR8-NEXT: rldicl r27, r11, 32, 56
709 ; CHECK-PWR8-NEXT: clrlwi r27, r27, 24
710 ; CHECK-PWR8-NEXT: mtvsrd v4, r28
711 ; CHECK-PWR8-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
712 ; CHECK-PWR8-NEXT: sub r27, r27, r26
713 ; CHECK-PWR8-NEXT: srawi r26, r27, 31
714 ; CHECK-PWR8-NEXT: xor r27, r27, r26
715 ; CHECK-PWR8-NEXT: sub r27, r27, r26
716 ; CHECK-PWR8-NEXT: rldicl r26, r11, 24, 56
717 ; CHECK-PWR8-NEXT: clrlwi r26, r26, 24
718 ; CHECK-PWR8-NEXT: sub r26, r26, r25
719 ; CHECK-PWR8-NEXT: srawi r25, r26, 31
720 ; CHECK-PWR8-NEXT: xor r26, r26, r25
721 ; CHECK-PWR8-NEXT: sub r26, r26, r25
722 ; CHECK-PWR8-NEXT: rldicl r25, r11, 16, 56
723 ; CHECK-PWR8-NEXT: rldicl r11, r11, 8, 56
724 ; CHECK-PWR8-NEXT: clrlwi r25, r25, 24
725 ; CHECK-PWR8-NEXT: clrlwi r11, r11, 24
726 ; CHECK-PWR8-NEXT: mtvsrd v5, r26
727 ; CHECK-PWR8-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
728 ; CHECK-PWR8-NEXT: sub r25, r25, r24
729 ; CHECK-PWR8-NEXT: sub r11, r11, r12
730 ; CHECK-PWR8-NEXT: srawi r24, r25, 31
731 ; CHECK-PWR8-NEXT: srawi r12, r11, 31
732 ; CHECK-PWR8-NEXT: xor r25, r25, r24
733 ; CHECK-PWR8-NEXT: xor r11, r11, r12
734 ; CHECK-PWR8-NEXT: sub r25, r25, r24
735 ; CHECK-PWR8-NEXT: sub r11, r11, r12
736 ; CHECK-PWR8-NEXT: ld r24, -64(r1) # 8-byte Folded Reload
737 ; CHECK-PWR8-NEXT: mtvsrd v0, r11
738 ; CHECK-PWR8-NEXT: vmrghb v2, v3, v2
739 ; CHECK-PWR8-NEXT: mtvsrd v3, r29
740 ; CHECK-PWR8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
741 ; CHECK-PWR8-NEXT: vmrghb v3, v4, v3
742 ; CHECK-PWR8-NEXT: mtvsrd v4, r27
743 ; CHECK-PWR8-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
744 ; CHECK-PWR8-NEXT: vmrglh v2, v3, v2
745 ; CHECK-PWR8-NEXT: vmrghb v4, v5, v4
746 ; CHECK-PWR8-NEXT: mtvsrd v5, r25
747 ; CHECK-PWR8-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
748 ; CHECK-PWR8-NEXT: vmrghb v5, v0, v5
749 ; CHECK-PWR8-NEXT: mtvsrd v0, r10
750 ; CHECK-PWR8-NEXT: vmrglh v3, v5, v4
751 ; CHECK-PWR8-NEXT: xxmrglw vs0, v3, v2
752 ; CHECK-PWR8-NEXT: vmrghb v0, v1, v0
753 ; CHECK-PWR8-NEXT: mtvsrd v1, r7
754 ; CHECK-PWR8-NEXT: vmrghb v1, v6, v1
755 ; CHECK-PWR8-NEXT: mtvsrd v6, r4
756 ; CHECK-PWR8-NEXT: vmrglh v4, v1, v0
757 ; CHECK-PWR8-NEXT: vmrghb v6, v7, v6
758 ; CHECK-PWR8-NEXT: mtvsrd v7, r5
759 ; CHECK-PWR8-NEXT: vmrghb v7, v8, v7
760 ; CHECK-PWR8-NEXT: vmrglh v5, v7, v6
761 ; CHECK-PWR8-NEXT: xxmrglw vs1, v5, v4
762 ; CHECK-PWR8-NEXT: xxmrgld v2, vs0, vs1
763 ; CHECK-PWR8-NEXT: blr
764 ;
765 ; CHECK-PWR7-LABEL: sub_absv_8_ext:
766 ; CHECK-PWR7: # %bb.0: # %entry
767 ; CHECK-PWR7-NEXT: stdu r1, -512(r1)
768 ; CHECK-PWR7-NEXT: .cfi_def_cfa_offset 512
769 ; CHECK-PWR7-NEXT: .cfi_offset r14, -144
770 ; CHECK-PWR7-NEXT: .cfi_offset r15, -136
771 ; CHECK-PWR7-NEXT: .cfi_offset r16, -128
772 ; CHECK-PWR7-NEXT: .cfi_offset r17, -120
773 ; CHECK-PWR7-NEXT: .cfi_offset r18, -112
774 ; CHECK-PWR7-NEXT: .cfi_offset r19, -104
775 ; CHECK-PWR7-NEXT: .cfi_offset r20, -96
776 ; CHECK-PWR7-NEXT: .cfi_offset r21, -88
777 ; CHECK-PWR7-NEXT: .cfi_offset r22, -80
778 ; CHECK-PWR7-NEXT: .cfi_offset r23, -72
779 ; CHECK-PWR7-NEXT: .cfi_offset r24, -64
780 ; CHECK-PWR7-NEXT: .cfi_offset r25, -56
781 ; CHECK-PWR7-NEXT: .cfi_offset r26, -48
782 ; CHECK-PWR7-NEXT: .cfi_offset r27, -40
783 ; CHECK-PWR7-NEXT: .cfi_offset r28, -32
784 ; CHECK-PWR7-NEXT: .cfi_offset r29, -24
785 ; CHECK-PWR7-NEXT: .cfi_offset r30, -16
786 ; CHECK-PWR7-NEXT: .cfi_offset r31, -8
787 ; CHECK-PWR7-NEXT: .cfi_offset r2, -152
788 ; CHECK-PWR7-NEXT: addi r3, r1, 320
789 ; CHECK-PWR7-NEXT: std r14, 368(r1) # 8-byte Folded Spill
790 ; CHECK-PWR7-NEXT: std r15, 376(r1) # 8-byte Folded Spill
791 ; CHECK-PWR7-NEXT: std r16, 384(r1) # 8-byte Folded Spill
792 ; CHECK-PWR7-NEXT: std r17, 392(r1) # 8-byte Folded Spill
793 ; CHECK-PWR7-NEXT: std r18, 400(r1) # 8-byte Folded Spill
794 ; CHECK-PWR7-NEXT: std r19, 408(r1) # 8-byte Folded Spill
795 ; CHECK-PWR7-NEXT: std r20, 416(r1) # 8-byte Folded Spill
796 ; CHECK-PWR7-NEXT: std r21, 424(r1) # 8-byte Folded Spill
797 ; CHECK-PWR7-NEXT: std r22, 432(r1) # 8-byte Folded Spill
798 ; CHECK-PWR7-NEXT: std r23, 440(r1) # 8-byte Folded Spill
799 ; CHECK-PWR7-NEXT: std r24, 448(r1) # 8-byte Folded Spill
800 ; CHECK-PWR7-NEXT: std r25, 456(r1) # 8-byte Folded Spill
801 ; CHECK-PWR7-NEXT: std r26, 464(r1) # 8-byte Folded Spill
802 ; CHECK-PWR7-NEXT: std r27, 472(r1) # 8-byte Folded Spill
803 ; CHECK-PWR7-NEXT: std r28, 480(r1) # 8-byte Folded Spill
804 ; CHECK-PWR7-NEXT: std r29, 488(r1) # 8-byte Folded Spill
805 ; CHECK-PWR7-NEXT: std r30, 496(r1) # 8-byte Folded Spill
806 ; CHECK-PWR7-NEXT: std r31, 504(r1) # 8-byte Folded Spill
807 ; CHECK-PWR7-NEXT: std r2, 360(r1) # 8-byte Folded Spill
808 ; CHECK-PWR7-NEXT: stxvw4x v2, 0, r3
809 ; CHECK-PWR7-NEXT: lbz r3, 320(r1)
810 ; CHECK-PWR7-NEXT: addi r4, r1, 336
811 ; CHECK-PWR7-NEXT: stw r3, 60(r1) # 4-byte Folded Spill
812 ; CHECK-PWR7-NEXT: stxvw4x v3, 0, r4
813 ; CHECK-PWR7-NEXT: lbz r15, 334(r1)
814 ; CHECK-PWR7-NEXT: lbz r14, 350(r1)
815 ; CHECK-PWR7-NEXT: lbz r31, 335(r1)
816 ; CHECK-PWR7-NEXT: lbz r2, 351(r1)
817 ; CHECK-PWR7-NEXT: sub r15, r15, r14
818 ; CHECK-PWR7-NEXT: sub r14, r31, r2
819 ; CHECK-PWR7-NEXT: srawi r2, r14, 31
820 ; CHECK-PWR7-NEXT: xor r14, r14, r2
821 ; CHECK-PWR7-NEXT: lbz r3, 333(r1)
822 ; CHECK-PWR7-NEXT: lbz r19, 331(r1)
823 ; CHECK-PWR7-NEXT: lbz r18, 347(r1)
824 ; CHECK-PWR7-NEXT: sub r19, r19, r18
825 ; CHECK-PWR7-NEXT: lbz r17, 332(r1)
826 ; CHECK-PWR7-NEXT: lbz r16, 348(r1)
827 ; CHECK-PWR7-NEXT: sub r17, r17, r16
828 ; CHECK-PWR7-NEXT: lbz r23, 329(r1)
829 ; CHECK-PWR7-NEXT: sub r14, r14, r2
830 ; CHECK-PWR7-NEXT: lbz r2, 349(r1)
831 ; CHECK-PWR7-NEXT: lbz r22, 345(r1)
832 ; CHECK-PWR7-NEXT: lbz r4, 336(r1)
833 ; CHECK-PWR7-NEXT: lbz r5, 321(r1)
834 ; CHECK-PWR7-NEXT: lbz r6, 337(r1)
835 ; CHECK-PWR7-NEXT: lbz r7, 322(r1)
836 ; CHECK-PWR7-NEXT: lbz r8, 338(r1)
837 ; CHECK-PWR7-NEXT: lbz r9, 323(r1)
838 ; CHECK-PWR7-NEXT: lbz r10, 339(r1)
839 ; CHECK-PWR7-NEXT: lbz r11, 324(r1)
840 ; CHECK-PWR7-NEXT: lbz r12, 340(r1)
841 ; CHECK-PWR7-NEXT: lbz r0, 325(r1)
842 ; CHECK-PWR7-NEXT: lbz r30, 341(r1)
843 ; CHECK-PWR7-NEXT: lbz r29, 326(r1)
844 ; CHECK-PWR7-NEXT: lbz r28, 342(r1)
845 ; CHECK-PWR7-NEXT: lbz r27, 327(r1)
846 ; CHECK-PWR7-NEXT: lbz r26, 343(r1)
847 ; CHECK-PWR7-NEXT: sub r3, r3, r2
848 ; CHECK-PWR7-NEXT: lbz r25, 328(r1)
849 ; CHECK-PWR7-NEXT: lbz r24, 344(r1)
850 ; CHECK-PWR7-NEXT: lbz r21, 330(r1)
851 ; CHECK-PWR7-NEXT: lbz r20, 346(r1)
852 ; CHECK-PWR7-NEXT: sub r5, r5, r6
853 ; CHECK-PWR7-NEXT: srawi r18, r3, 31
854 ; CHECK-PWR7-NEXT: sub r7, r7, r8
855 ; CHECK-PWR7-NEXT: sub r9, r9, r10
856 ; CHECK-PWR7-NEXT: sub r11, r11, r12
857 ; CHECK-PWR7-NEXT: sub r0, r0, r30
858 ; CHECK-PWR7-NEXT: sub r29, r29, r28
859 ; CHECK-PWR7-NEXT: sub r27, r27, r26
860 ; CHECK-PWR7-NEXT: sub r25, r25, r24
861 ; CHECK-PWR7-NEXT: srawi r31, r15, 31
862 ; CHECK-PWR7-NEXT: ld r2, 360(r1) # 8-byte Folded Reload
863 ; CHECK-PWR7-NEXT: xor r3, r3, r18
864 ; CHECK-PWR7-NEXT: srawi r6, r5, 31
865 ; CHECK-PWR7-NEXT: srawi r8, r7, 31
866 ; CHECK-PWR7-NEXT: srawi r10, r9, 31
867 ; CHECK-PWR7-NEXT: srawi r12, r11, 31
868 ; CHECK-PWR7-NEXT: srawi r30, r0, 31
869 ; CHECK-PWR7-NEXT: sub r3, r3, r18
870 ; CHECK-PWR7-NEXT: srawi r18, r19, 31
871 ; CHECK-PWR7-NEXT: srawi r28, r29, 31
872 ; CHECK-PWR7-NEXT: ld r16, 384(r1) # 8-byte Folded Reload
873 ; CHECK-PWR7-NEXT: sldi r3, r3, 56
874 ; CHECK-PWR7-NEXT: srawi r26, r27, 31
875 ; CHECK-PWR7-NEXT: srawi r24, r25, 31
876 ; CHECK-PWR7-NEXT: xor r19, r19, r18
877 ; CHECK-PWR7-NEXT: xor r15, r15, r31
878 ; CHECK-PWR7-NEXT: xor r5, r5, r6
879 ; CHECK-PWR7-NEXT: std r3, 272(r1)
880 ; CHECK-PWR7-NEXT: std r3, 280(r1)
881 ; CHECK-PWR7-NEXT: srawi r3, r17, 31
882 ; CHECK-PWR7-NEXT: sub r19, r19, r18
883 ; CHECK-PWR7-NEXT: xor r7, r7, r8
884 ; CHECK-PWR7-NEXT: sub r15, r15, r31
885 ; CHECK-PWR7-NEXT: xor r17, r17, r3
886 ; CHECK-PWR7-NEXT: xor r9, r9, r10
887 ; CHECK-PWR7-NEXT: xor r11, r11, r12
888 ; CHECK-PWR7-NEXT: xor r0, r0, r30
889 ; CHECK-PWR7-NEXT: xor r29, r29, r28
890 ; CHECK-PWR7-NEXT: xor r27, r27, r26
891 ; CHECK-PWR7-NEXT: sub r3, r17, r3
892 ; CHECK-PWR7-NEXT: xor r25, r25, r24
893 ; CHECK-PWR7-NEXT: sub r25, r25, r24
894 ; CHECK-PWR7-NEXT: sub r27, r27, r26
895 ; CHECK-PWR7-NEXT: sub r29, r29, r28
896 ; CHECK-PWR7-NEXT: sldi r3, r3, 56
897 ; CHECK-PWR7-NEXT: sub r0, r0, r30
898 ; CHECK-PWR7-NEXT: sub r11, r11, r12
899 ; CHECK-PWR7-NEXT: sub r9, r9, r10
900 ; CHECK-PWR7-NEXT: sub r7, r7, r8
901 ; CHECK-PWR7-NEXT: sub r5, r5, r6
902 ; CHECK-PWR7-NEXT: sldi r14, r14, 56
903 ; CHECK-PWR7-NEXT: sldi r15, r15, 56
904 ; CHECK-PWR7-NEXT: ld r31, 504(r1) # 8-byte Folded Reload
905 ; CHECK-PWR7-NEXT: std r3, 256(r1)
906 ; CHECK-PWR7-NEXT: std r3, 264(r1)
907 ; CHECK-PWR7-NEXT: sldi r3, r19, 56
908 ; CHECK-PWR7-NEXT: sldi r25, r25, 56
909 ; CHECK-PWR7-NEXT: sldi r27, r27, 56
910 ; CHECK-PWR7-NEXT: std r3, 240(r1)
911 ; CHECK-PWR7-NEXT: std r3, 248(r1)
912 ; CHECK-PWR7-NEXT: sub r3, r23, r22
913 ; CHECK-PWR7-NEXT: srawi r23, r3, 31
914 ; CHECK-PWR7-NEXT: sub r22, r21, r20
915 ; CHECK-PWR7-NEXT: srawi r21, r22, 31
916 ; CHECK-PWR7-NEXT: sldi r29, r29, 56
917 ; CHECK-PWR7-NEXT: sldi r0, r0, 56
918 ; CHECK-PWR7-NEXT: sldi r11, r11, 56
919 ; CHECK-PWR7-NEXT: xor r3, r3, r23
920 ; CHECK-PWR7-NEXT: xor r22, r22, r21
921 ; CHECK-PWR7-NEXT: sldi r9, r9, 56
922 ; CHECK-PWR7-NEXT: sldi r7, r7, 56
923 ; CHECK-PWR7-NEXT: sldi r5, r5, 56
924 ; CHECK-PWR7-NEXT: ld r30, 496(r1) # 8-byte Folded Reload
925 ; CHECK-PWR7-NEXT: ld r28, 480(r1) # 8-byte Folded Reload
926 ; CHECK-PWR7-NEXT: sub r3, r3, r23
927 ; CHECK-PWR7-NEXT: sub r22, r22, r21
928 ; CHECK-PWR7-NEXT: std r14, 304(r1)
929 ; CHECK-PWR7-NEXT: ld r26, 464(r1) # 8-byte Folded Reload
930 ; CHECK-PWR7-NEXT: sldi r3, r3, 56
931 ; CHECK-PWR7-NEXT: sldi r22, r22, 56
932 ; CHECK-PWR7-NEXT: ld r24, 448(r1) # 8-byte Folded Reload
933 ; CHECK-PWR7-NEXT: ld r23, 440(r1) # 8-byte Folded Reload
934 ; CHECK-PWR7-NEXT: std r14, 312(r1)
935 ; CHECK-PWR7-NEXT: std r15, 288(r1)
936 ; CHECK-PWR7-NEXT: std r3, 208(r1)
937 ; CHECK-PWR7-NEXT: std r3, 216(r1)
938 ; CHECK-PWR7-NEXT: lwz r3, 60(r1) # 4-byte Folded Reload
939 ; CHECK-PWR7-NEXT: std r15, 296(r1)
940 ; CHECK-PWR7-NEXT: ld r21, 424(r1) # 8-byte Folded Reload
941 ; CHECK-PWR7-NEXT: ld r20, 416(r1) # 8-byte Folded Reload
942 ; CHECK-PWR7-NEXT: std r22, 224(r1)
943 ; CHECK-PWR7-NEXT: std r22, 232(r1)
944 ; CHECK-PWR7-NEXT: sub r4, r3, r4
945 ; CHECK-PWR7-NEXT: std r25, 192(r1)
946 ; CHECK-PWR7-NEXT: ld r22, 432(r1) # 8-byte Folded Reload
947 ; CHECK-PWR7-NEXT: ld r19, 408(r1) # 8-byte Folded Reload
948 ; CHECK-PWR7-NEXT: srawi r3, r4, 31
949 ; CHECK-PWR7-NEXT: std r25, 200(r1)
950 ; CHECK-PWR7-NEXT: ld r25, 456(r1) # 8-byte Folded Reload
951 ; CHECK-PWR7-NEXT: std r27, 176(r1)
952 ; CHECK-PWR7-NEXT: std r27, 184(r1)
953 ; CHECK-PWR7-NEXT: xor r4, r4, r3
954 ; CHECK-PWR7-NEXT: std r29, 160(r1)
955 ; CHECK-PWR7-NEXT: ld r27, 472(r1) # 8-byte Folded Reload
956 ; CHECK-PWR7-NEXT: std r29, 168(r1)
957 ; CHECK-PWR7-NEXT: std r0, 144(r1)
958 ; CHECK-PWR7-NEXT: sub r3, r4, r3
959 ; CHECK-PWR7-NEXT: std r0, 152(r1)
960 ; CHECK-PWR7-NEXT: ld r29, 488(r1) # 8-byte Folded Reload
961 ; CHECK-PWR7-NEXT: ld r18, 400(r1) # 8-byte Folded Reload
962 ; CHECK-PWR7-NEXT: sldi r3, r3, 56
963 ; CHECK-PWR7-NEXT: std r11, 128(r1)
964 ; CHECK-PWR7-NEXT: ld r17, 392(r1) # 8-byte Folded Reload
965 ; CHECK-PWR7-NEXT: std r11, 136(r1)
966 ; CHECK-PWR7-NEXT: std r9, 112(r1)
967 ; CHECK-PWR7-NEXT: std r3, 64(r1)
968 ; CHECK-PWR7-NEXT: std r3, 72(r1)
969 ; CHECK-PWR7-NEXT: addi r3, r1, 304
970 ; CHECK-PWR7-NEXT: std r9, 120(r1)
971 ; CHECK-PWR7-NEXT: ld r15, 376(r1) # 8-byte Folded Reload
972 ; CHECK-PWR7-NEXT: std r7, 96(r1)
973 ; CHECK-PWR7-NEXT: std r7, 104(r1)
974 ; CHECK-PWR7-NEXT: std r5, 80(r1)
975 ; CHECK-PWR7-NEXT: std r5, 88(r1)
976 ; CHECK-PWR7-NEXT: lxvw4x v2, 0, r3
977 ; CHECK-PWR7-NEXT: addi r3, r1, 288
978 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
979 ; CHECK-PWR7-NEXT: addi r3, r1, 272
980 ; CHECK-PWR7-NEXT: ld r14, 368(r1) # 8-byte Folded Reload
981 ; CHECK-PWR7-NEXT: vmrghb v2, v3, v2
982 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
983 ; CHECK-PWR7-NEXT: addi r3, r1, 256
984 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
985 ; CHECK-PWR7-NEXT: addi r3, r1, 240
986 ; CHECK-PWR7-NEXT: vmrghb v3, v4, v3
987 ; CHECK-PWR7-NEXT: vmrghh v2, v3, v2
988 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
989 ; CHECK-PWR7-NEXT: addi r3, r1, 224
990 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
991 ; CHECK-PWR7-NEXT: addi r3, r1, 208
992 ; CHECK-PWR7-NEXT: vmrghb v3, v4, v3
993 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
994 ; CHECK-PWR7-NEXT: addi r3, r1, 192
995 ; CHECK-PWR7-NEXT: lxvw4x v5, 0, r3
996 ; CHECK-PWR7-NEXT: addi r3, r1, 176
997 ; CHECK-PWR7-NEXT: vmrghb v4, v5, v4
998 ; CHECK-PWR7-NEXT: vmrghh v3, v4, v3
999 ; CHECK-PWR7-NEXT: xxmrghw vs0, v3, v2
1000 ; CHECK-PWR7-NEXT: lxvw4x v2, 0, r3
1001 ; CHECK-PWR7-NEXT: addi r3, r1, 160
1002 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
1003 ; CHECK-PWR7-NEXT: addi r3, r1, 144
1004 ; CHECK-PWR7-NEXT: vmrghb v2, v3, v2
1005 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
1006 ; CHECK-PWR7-NEXT: addi r3, r1, 128
1007 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1008 ; CHECK-PWR7-NEXT: vmrghb v3, v4, v3
1009 ; CHECK-PWR7-NEXT: addi r3, r1, 112
1010 ; CHECK-PWR7-NEXT: vmrghh v2, v3, v2
1011 ; CHECK-PWR7-NEXT: lxvw4x v3, 0, r3
1012 ; CHECK-PWR7-NEXT: addi r3, r1, 96
1013 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1014 ; CHECK-PWR7-NEXT: addi r3, r1, 80
1015 ; CHECK-PWR7-NEXT: vmrghb v3, v4, v3
1016 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1017 ; CHECK-PWR7-NEXT: addi r3, r1, 64
1018 ; CHECK-PWR7-NEXT: lxvw4x v5, 0, r3
1019 ; CHECK-PWR7-NEXT: vmrghb v4, v5, v4
1020 ; CHECK-PWR7-NEXT: vmrghh v3, v4, v3
1021 ; CHECK-PWR7-NEXT: xxmrghw vs1, v3, v2
1022 ; CHECK-PWR7-NEXT: xxmrghd v2, vs1, vs0
1023 ; CHECK-PWR7-NEXT: addi r1, r1, 512
1024 ; CHECK-PWR7-NEXT: blr
1025 entry:
1026 %vecext = extractelement <16 x i8> %a, i32 0
1027 %conv = zext i8 %vecext to i32
1028 %vecext1 = extractelement <16 x i8> %b, i32 0
1029 %conv2 = zext i8 %vecext1 to i32
1030 %sub = sub nsw i32 %conv, %conv2
1031 %ispos = icmp sgt i32 %sub, -1
1032 %neg = sub nsw i32 0, %sub
1033 %0 = select i1 %ispos, i32 %sub, i32 %neg
1034 %conv3 = trunc i32 %0 to i8
1035 %vecins = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv3, i32 0
1036 %vecext4 = extractelement <16 x i8> %a, i32 1
1037 %conv5 = zext i8 %vecext4 to i32
1038 %vecext6 = extractelement <16 x i8> %b, i32 1
1039 %conv7 = zext i8 %vecext6 to i32
1040 %sub8 = sub nsw i32 %conv5, %conv7
1041 %ispos171 = icmp sgt i32 %sub8, -1
1042 %neg172 = sub nsw i32 0, %sub8
1043 %1 = select i1 %ispos171, i32 %sub8, i32 %neg172
1044 %conv10 = trunc i32 %1 to i8
1045 %vecins11 = insertelement <16 x i8> %vecins, i8 %conv10, i32 1
1046 %vecext12 = extractelement <16 x i8> %a, i32 2
1047 %conv13 = zext i8 %vecext12 to i32
1048 %vecext14 = extractelement <16 x i8> %b, i32 2
1049 %conv15 = zext i8 %vecext14 to i32
1050 %sub16 = sub nsw i32 %conv13, %conv15
1051 %ispos173 = icmp sgt i32 %sub16, -1
1052 %neg174 = sub nsw i32 0, %sub16
1053 %2 = select i1 %ispos173, i32 %sub16, i32 %neg174
1054 %conv18 = trunc i32 %2 to i8
1055 %vecins19 = insertelement <16 x i8> %vecins11, i8 %conv18, i32 2
1056 %vecext20 = extractelement <16 x i8> %a, i32 3
1057 %conv21 = zext i8 %vecext20 to i32
1058 %vecext22 = extractelement <16 x i8> %b, i32 3
1059 %conv23 = zext i8 %vecext22 to i32
1060 %sub24 = sub nsw i32 %conv21, %conv23
1061 %ispos175 = icmp sgt i32 %sub24, -1
1062 %neg176 = sub nsw i32 0, %sub24
1063 %3 = select i1 %ispos175, i32 %sub24, i32 %neg176
1064 %conv26 = trunc i32 %3 to i8
1065 %vecins27 = insertelement <16 x i8> %vecins19, i8 %conv26, i32 3
1066 %vecext28 = extractelement <16 x i8> %a, i32 4
1067 %conv29 = zext i8 %vecext28 to i32
1068 %vecext30 = extractelement <16 x i8> %b, i32 4
1069 %conv31 = zext i8 %vecext30 to i32
1070 %sub32 = sub nsw i32 %conv29, %conv31
1071 %ispos177 = icmp sgt i32 %sub32, -1
1072 %neg178 = sub nsw i32 0, %sub32
1073 %4 = select i1 %ispos177, i32 %sub32, i32 %neg178
1074 %conv34 = trunc i32 %4 to i8
1075 %vecins35 = insertelement <16 x i8> %vecins27, i8 %conv34, i32 4
1076 %vecext36 = extractelement <16 x i8> %a, i32 5
1077 %conv37 = zext i8 %vecext36 to i32
1078 %vecext38 = extractelement <16 x i8> %b, i32 5
1079 %conv39 = zext i8 %vecext38 to i32
1080 %sub40 = sub nsw i32 %conv37, %conv39
1081 %ispos179 = icmp sgt i32 %sub40, -1
1082 %neg180 = sub nsw i32 0, %sub40
1083 %5 = select i1 %ispos179, i32 %sub40, i32 %neg180
1084 %conv42 = trunc i32 %5 to i8
1085 %vecins43 = insertelement <16 x i8> %vecins35, i8 %conv42, i32 5
1086 %vecext44 = extractelement <16 x i8> %a, i32 6
1087 %conv45 = zext i8 %vecext44 to i32
1088 %vecext46 = extractelement <16 x i8> %b, i32 6
1089 %conv47 = zext i8 %vecext46 to i32
1090 %sub48 = sub nsw i32 %conv45, %conv47
1091 %ispos181 = icmp sgt i32 %sub48, -1
1092 %neg182 = sub nsw i32 0, %sub48
1093 %6 = select i1 %ispos181, i32 %sub48, i32 %neg182
1094 %conv50 = trunc i32 %6 to i8
1095 %vecins51 = insertelement <16 x i8> %vecins43, i8 %conv50, i32 6
1096 %vecext52 = extractelement <16 x i8> %a, i32 7
1097 %conv53 = zext i8 %vecext52 to i32
1098 %vecext54 = extractelement <16 x i8> %b, i32 7
1099 %conv55 = zext i8 %vecext54 to i32
1100 %sub56 = sub nsw i32 %conv53, %conv55
1101 %ispos183 = icmp sgt i32 %sub56, -1
1102 %neg184 = sub nsw i32 0, %sub56
1103 %7 = select i1 %ispos183, i32 %sub56, i32 %neg184
1104 %conv58 = trunc i32 %7 to i8
1105 %vecins59 = insertelement <16 x i8> %vecins51, i8 %conv58, i32 7
1106 %vecext60 = extractelement <16 x i8> %a, i32 8
1107 %conv61 = zext i8 %vecext60 to i32
1108 %vecext62 = extractelement <16 x i8> %b, i32 8
1109 %conv63 = zext i8 %vecext62 to i32
1110 %sub64 = sub nsw i32 %conv61, %conv63
1111 %ispos185 = icmp sgt i32 %sub64, -1
1112 %neg186 = sub nsw i32 0, %sub64
1113 %8 = select i1 %ispos185, i32 %sub64, i32 %neg186
1114 %conv66 = trunc i32 %8 to i8
1115 %vecins67 = insertelement <16 x i8> %vecins59, i8 %conv66, i32 8
1116 %vecext68 = extractelement <16 x i8> %a, i32 9
1117 %conv69 = zext i8 %vecext68 to i32
1118 %vecext70 = extractelement <16 x i8> %b, i32 9
1119 %conv71 = zext i8 %vecext70 to i32
1120 %sub72 = sub nsw i32 %conv69, %conv71
1121 %ispos187 = icmp sgt i32 %sub72, -1
1122 %neg188 = sub nsw i32 0, %sub72
1123 %9 = select i1 %ispos187, i32 %sub72, i32 %neg188
1124 %conv74 = trunc i32 %9 to i8
1125 %vecins75 = insertelement <16 x i8> %vecins67, i8 %conv74, i32 9
1126 %vecext76 = extractelement <16 x i8> %a, i32 10
1127 %conv77 = zext i8 %vecext76 to i32
1128 %vecext78 = extractelement <16 x i8> %b, i32 10
1129 %conv79 = zext i8 %vecext78 to i32
1130 %sub80 = sub nsw i32 %conv77, %conv79
1131 %ispos189 = icmp sgt i32 %sub80, -1
1132 %neg190 = sub nsw i32 0, %sub80
1133 %10 = select i1 %ispos189, i32 %sub80, i32 %neg190
1134 %conv82 = trunc i32 %10 to i8
1135 %vecins83 = insertelement <16 x i8> %vecins75, i8 %conv82, i32 10
1136 %vecext84 = extractelement <16 x i8> %a, i32 11
1137 %conv85 = zext i8 %vecext84 to i32
1138 %vecext86 = extractelement <16 x i8> %b, i32 11
1139 %conv87 = zext i8 %vecext86 to i32
1140 %sub88 = sub nsw i32 %conv85, %conv87
1141 %ispos191 = icmp sgt i32 %sub88, -1
1142 %neg192 = sub nsw i32 0, %sub88
1143 %11 = select i1 %ispos191, i32 %sub88, i32 %neg192
1144 %conv90 = trunc i32 %11 to i8
1145 %vecins91 = insertelement <16 x i8> %vecins83, i8 %conv90, i32 11
1146 %vecext92 = extractelement <16 x i8> %a, i32 12
1147 %conv93 = zext i8 %vecext92 to i32
1148 %vecext94 = extractelement <16 x i8> %b, i32 12
1149 %conv95 = zext i8 %vecext94 to i32
1150 %sub96 = sub nsw i32 %conv93, %conv95
1151 %ispos193 = icmp sgt i32 %sub96, -1
1152 %neg194 = sub nsw i32 0, %sub96
1153 %12 = select i1 %ispos193, i32 %sub96, i32 %neg194
1154 %conv98 = trunc i32 %12 to i8
1155 %vecins99 = insertelement <16 x i8> %vecins91, i8 %conv98, i32 12
1156 %vecext100 = extractelement <16 x i8> %a, i32 13
1157 %conv101 = zext i8 %vecext100 to i32
1158 %vecext102 = extractelement <16 x i8> %b, i32 13
1159 %conv103 = zext i8 %vecext102 to i32
1160 %sub104 = sub nsw i32 %conv101, %conv103
1161 %ispos195 = icmp sgt i32 %sub104, -1
1162 %neg196 = sub nsw i32 0, %sub104
1163 %13 = select i1 %ispos195, i32 %sub104, i32 %neg196
1164 %conv106 = trunc i32 %13 to i8
1165 %vecins107 = insertelement <16 x i8> %vecins99, i8 %conv106, i32 13
1166 %vecext108 = extractelement <16 x i8> %a, i32 14
1167 %conv109 = zext i8 %vecext108 to i32
1168 %vecext110 = extractelement <16 x i8> %b, i32 14
1169 %conv111 = zext i8 %vecext110 to i32
1170 %sub112 = sub nsw i32 %conv109, %conv111
1171 %ispos197 = icmp sgt i32 %sub112, -1
1172 %neg198 = sub nsw i32 0, %sub112
1173 %14 = select i1 %ispos197, i32 %sub112, i32 %neg198
1174 %conv114 = trunc i32 %14 to i8
1175 %vecins115 = insertelement <16 x i8> %vecins107, i8 %conv114, i32 14
1176 %vecext116 = extractelement <16 x i8> %a, i32 15
1177 %conv117 = zext i8 %vecext116 to i32
1178 %vecext118 = extractelement <16 x i8> %b, i32 15
1179 %conv119 = zext i8 %vecext118 to i32
1180 %sub120 = sub nsw i32 %conv117, %conv119
1181 %ispos199 = icmp sgt i32 %sub120, -1
1182 %neg200 = sub nsw i32 0, %sub120
1183 %15 = select i1 %ispos199, i32 %sub120, i32 %neg200
1184 %conv122 = trunc i32 %15 to i8
1185 %vecins123 = insertelement <16 x i8> %vecins115, i8 %conv122, i32 15
1186 ret <16 x i8> %vecins123
1187 }
1189 define <4 x i32> @sub_absv_vec_32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr {
1190 ; CHECK-PWR9-LABEL: sub_absv_vec_32:
1191 ; CHECK-PWR9: # %bb.0: # %entry
1192 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1193 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1194 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1195 ; CHECK-PWR9-NEXT: blr
1196 ;
1197 ; CHECK-PWR78-LABEL: sub_absv_vec_32:
1198 ; CHECK-PWR78: # %bb.0: # %entry
1199 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v3
1200 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
1201 ; CHECK-PWR78-NEXT: vsubuwm v3, v3, v2
1202 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
1203 ; CHECK-PWR78-NEXT: blr
1204 entry:
1205 %sub = sub nsw <4 x i32> %a, %b
1206 %sub.i = sub <4 x i32> zeroinitializer, %sub
1207 %0 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %sub, <4 x i32> %sub.i)
1208 ret <4 x i32> %0
1209 }
1211 define <8 x i16> @sub_absv_vec_16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr {
1212 ; CHECK-LABEL: sub_absv_vec_16:
1213 ; CHECK: # %bb.0: # %entry
1214 ; CHECK-NEXT: vsubuhm v2, v2, v3
1215 ; CHECK-NEXT: xxlxor v3, v3, v3
1216 ; CHECK-NEXT: vsubuhm v3, v3, v2
1217 ; CHECK-NEXT: vmaxsh v2, v2, v3
1218 ; CHECK-NEXT: blr
1219 entry:
1220 %sub = sub nsw <8 x i16> %a, %b
1221 %sub.i = sub <8 x i16> zeroinitializer, %sub
1222 %0 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %sub, <8 x i16> %sub.i)
1223 ret <8 x i16> %0
1224 }
1226 define <16 x i8> @sub_absv_vec_8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr {
1227 ; CHECK-LABEL: sub_absv_vec_8:
1228 ; CHECK: # %bb.0: # %entry
1229 ; CHECK-NEXT: vsububm v2, v2, v3
1230 ; CHECK-NEXT: xxlxor v3, v3, v3
1231 ; CHECK-NEXT: vsububm v3, v3, v2
1232 ; CHECK-NEXT: vmaxsb v2, v2, v3
1233 ; CHECK-NEXT: blr
1234 entry:
1235 %sub = sub nsw <16 x i8> %a, %b
1236 %sub.i = sub <16 x i8> zeroinitializer, %sub
1237 %0 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %sub, <16 x i8> %sub.i)
1238 ret <16 x i8> %0
1239 }
1241 define <4 x i32> @zext_sub_absd32(<4 x i16>, <4 x i16>) local_unnamed_addr {
1242 ; CHECK-PWR9-LE-LABEL: zext_sub_absd32:
1243 ; CHECK-PWR9-LE: # %bb.0:
1244 ; CHECK-PWR9-LE-NEXT: vabsduh v2, v2, v3
1245 ; CHECK-PWR9-LE-NEXT: xxlxor v3, v3, v3
1246 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2
1247 ; CHECK-PWR9-LE-NEXT: blr
1248 ;
1249 ; CHECK-PWR9-BE-LABEL: zext_sub_absd32:
1250 ; CHECK-PWR9-BE: # %bb.0:
1251 ; CHECK-PWR9-BE-NEXT: vabsduh v2, v2, v3
1252 ; CHECK-PWR9-BE-NEXT: xxlxor v3, v3, v3
1253 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2
1254 ; CHECK-PWR9-BE-NEXT: blr
1255 ;
1256 ; CHECK-PWR8-LABEL: zext_sub_absd32:
1257 ; CHECK-PWR8: # %bb.0:
1258 ; CHECK-PWR8-NEXT: xxlxor v4, v4, v4
1259 ; CHECK-PWR8-NEXT: vmrglh v2, v4, v2
1260 ; CHECK-PWR8-NEXT: vmrglh v3, v4, v3
1261 ; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3
1262 ; CHECK-PWR8-NEXT: vsubuwm v3, v4, v2
1263 ; CHECK-PWR8-NEXT: vmaxsw v2, v2, v3
1264 ; CHECK-PWR8-NEXT: blr
1265 ;
1266 ; CHECK-PWR7-LABEL: zext_sub_absd32:
1267 ; CHECK-PWR7: # %bb.0:
1268 ; CHECK-PWR7-NEXT: addis r3, r2, .LCPI13_0@toc@ha
1269 ; CHECK-PWR7-NEXT: xxlxor v5, v5, v5
1270 ; CHECK-PWR7-NEXT: addi r3, r3, .LCPI13_0@toc@l
1271 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1272 ; CHECK-PWR7-NEXT: vperm v2, v5, v2, v4
1273 ; CHECK-PWR7-NEXT: vperm v3, v5, v3, v4
1274 ; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3
1275 ; CHECK-PWR7-NEXT: vsubuwm v3, v5, v2
1276 ; CHECK-PWR7-NEXT: vmaxsw v2, v2, v3
1277 ; CHECK-PWR7-NEXT: blr
1278 %3 = zext <4 x i16> %0 to <4 x i32>
1279 %4 = zext <4 x i16> %1 to <4 x i32>
1280 %5 = sub <4 x i32> %3, %4
1281 %6 = sub <4 x i32> zeroinitializer, %5
1282 %7 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> %6)
1283 ret <4 x i32> %7
1284 }
1286 define <8 x i16> @zext_sub_absd16(<8 x i8>, <8 x i8>) local_unnamed_addr {
1287 ; CHECK-PWR9-LE-LABEL: zext_sub_absd16:
1288 ; CHECK-PWR9-LE: # %bb.0:
1289 ; CHECK-PWR9-LE-NEXT: vabsdub v2, v2, v3
1290 ; CHECK-PWR9-LE-NEXT: xxlxor v3, v3, v3
1291 ; CHECK-PWR9-LE-NEXT: vmrglb v2, v3, v2
1292 ; CHECK-PWR9-LE-NEXT: blr
1293 ;
1294 ; CHECK-PWR9-BE-LABEL: zext_sub_absd16:
1295 ; CHECK-PWR9-BE: # %bb.0:
1296 ; CHECK-PWR9-BE-NEXT: vabsdub v2, v2, v3
1297 ; CHECK-PWR9-BE-NEXT: xxlxor v3, v3, v3
1298 ; CHECK-PWR9-BE-NEXT: vmrghb v2, v3, v2
1299 ; CHECK-PWR9-BE-NEXT: blr
1300 ;
1301 ; CHECK-PWR8-LABEL: zext_sub_absd16:
1302 ; CHECK-PWR8: # %bb.0:
1303 ; CHECK-PWR8-NEXT: xxlxor v4, v4, v4
1304 ; CHECK-PWR8-NEXT: vmrglb v2, v4, v2
1305 ; CHECK-PWR8-NEXT: vmrglb v3, v4, v3
1306 ; CHECK-PWR8-NEXT: vsubuhm v2, v2, v3
1307 ; CHECK-PWR8-NEXT: vsubuhm v3, v4, v2
1308 ; CHECK-PWR8-NEXT: vmaxsh v2, v2, v3
1309 ; CHECK-PWR8-NEXT: blr
1310 ;
1311 ; CHECK-PWR7-LABEL: zext_sub_absd16:
1312 ; CHECK-PWR7: # %bb.0:
1313 ; CHECK-PWR7-NEXT: addis r3, r2, .LCPI14_0@toc@ha
1314 ; CHECK-PWR7-NEXT: xxlxor v5, v5, v5
1315 ; CHECK-PWR7-NEXT: addi r3, r3, .LCPI14_0@toc@l
1316 ; CHECK-PWR7-NEXT: lxvw4x v4, 0, r3
1317 ; CHECK-PWR7-NEXT: vperm v2, v5, v2, v4
1318 ; CHECK-PWR7-NEXT: vperm v3, v5, v3, v4
1319 ; CHECK-PWR7-NEXT: vsubuhm v2, v2, v3
1320 ; CHECK-PWR7-NEXT: vsubuhm v3, v5, v2
1321 ; CHECK-PWR7-NEXT: vmaxsh v2, v2, v3
1322 ; CHECK-PWR7-NEXT: blr
1323 %3 = zext <8 x i8> %0 to <8 x i16>
1324 %4 = zext <8 x i8> %1 to <8 x i16>
1325 %5 = sub <8 x i16> %3, %4
1326 %6 = sub <8 x i16> zeroinitializer, %5
1327 %7 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> %6)
1328 ret <8 x i16> %7
1329 }
1331 define <16 x i8> @zext_sub_absd8(<16 x i4>, <16 x i4>) local_unnamed_addr {
1332 ; CHECK-PWR9-LABEL: zext_sub_absd8:
1333 ; CHECK-PWR9: # %bb.0:
1334 ; CHECK-PWR9-NEXT: xxspltib vs0, 15
1335 ; CHECK-PWR9-NEXT: xxland v3, v3, vs0
1336 ; CHECK-PWR9-NEXT: xxland v2, v2, vs0
1337 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1338 ; CHECK-PWR9-NEXT: blr
1339 ;
1340 ; CHECK-PWR78-LABEL: zext_sub_absd8:
1341 ; CHECK-PWR78: # %bb.0:
1342 ; CHECK-PWR78-NEXT: vspltisb v4, 15
1343 ; CHECK-PWR78-NEXT: xxland v2, v2, v4
1344 ; CHECK-PWR78-NEXT: xxland v3, v3, v4
1345 ; CHECK-PWR78-NEXT: vsububm v2, v2, v3
1346 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
1347 ; CHECK-PWR78-NEXT: vsububm v3, v3, v2
1348 ; CHECK-PWR78-NEXT: vmaxsb v2, v2, v3
1349 ; CHECK-PWR78-NEXT: blr
1350 %3 = zext <16 x i4> %0 to <16 x i8>
1351 %4 = zext <16 x i4> %1 to <16 x i8>
1352 %5 = sub <16 x i8> %3, %4
1353 %6 = sub <16 x i8> zeroinitializer, %5
1354 %7 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %5, <16 x i8> %6)
1355 ret <16 x i8> %7
1356 }
1358 define <4 x i32> @sext_sub_absd32(<4 x i16>, <4 x i16>) local_unnamed_addr {
1359 ; CHECK-PWR9-LE-LABEL: sext_sub_absd32:
1360 ; CHECK-PWR9-LE: # %bb.0:
1361 ; CHECK-PWR9-LE-NEXT: vminsh v4, v2, v3
1362 ; CHECK-PWR9-LE-NEXT: vmaxsh v2, v2, v3
1363 ; CHECK-PWR9-LE-NEXT: xxlxor v3, v3, v3
1364 ; CHECK-PWR9-LE-NEXT: vsubuhm v2, v2, v4
1365 ; CHECK-PWR9-LE-NEXT: vmrglh v2, v3, v2
1366 ; CHECK-PWR9-LE-NEXT: blr
1367 ;
1368 ; CHECK-PWR9-BE-LABEL: sext_sub_absd32:
1369 ; CHECK-PWR9-BE: # %bb.0:
1370 ; CHECK-PWR9-BE-NEXT: vminsh v4, v2, v3
1371 ; CHECK-PWR9-BE-NEXT: vmaxsh v2, v2, v3
1372 ; CHECK-PWR9-BE-NEXT: xxlxor v3, v3, v3
1373 ; CHECK-PWR9-BE-NEXT: vsubuhm v2, v2, v4
1374 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2
1375 ; CHECK-PWR9-BE-NEXT: blr
1376 ;
1377 ; CHECK-PWR8-LABEL: sext_sub_absd32:
1378 ; CHECK-PWR8: # %bb.0:
1379 ; CHECK-PWR8-NEXT: vspltisw v4, 8
1380 ; CHECK-PWR8-NEXT: vmrglh v2, v2, v2
1381 ; CHECK-PWR8-NEXT: vadduwm v4, v4, v4
1382 ; CHECK-PWR8-NEXT: vmrglh v3, v3, v3
1383 ; CHECK-PWR8-NEXT: vslw v2, v2, v4
1384 ; CHECK-PWR8-NEXT: vslw v3, v3, v4
1385 ; CHECK-PWR8-NEXT: vsraw v2, v2, v4
1386 ; CHECK-PWR8-NEXT: vsraw v3, v3, v4
1387 ; CHECK-PWR8-NEXT: vsubuwm v2, v2, v3
1388 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
1389 ; CHECK-PWR8-NEXT: vsubuwm v3, v3, v2
1390 ; CHECK-PWR8-NEXT: vmaxsw v2, v2, v3
1391 ; CHECK-PWR8-NEXT: blr
1392 ;
1393 ; CHECK-PWR7-LABEL: sext_sub_absd32:
1394 ; CHECK-PWR7: # %bb.0:
1395 ; CHECK-PWR7-NEXT: vspltisw v4, 8
1396 ; CHECK-PWR7-NEXT: vmrghh v2, v2, v2
1397 ; CHECK-PWR7-NEXT: vmrghh v3, v3, v3
1398 ; CHECK-PWR7-NEXT: vadduwm v4, v4, v4
1399 ; CHECK-PWR7-NEXT: vslw v2, v2, v4
1400 ; CHECK-PWR7-NEXT: vslw v3, v3, v4
1401 ; CHECK-PWR7-NEXT: vsraw v2, v2, v4
1402 ; CHECK-PWR7-NEXT: vsraw v3, v3, v4
1403 ; CHECK-PWR7-NEXT: vsubuwm v2, v2, v3
1404 ; CHECK-PWR7-NEXT: xxlxor v3, v3, v3
1405 ; CHECK-PWR7-NEXT: vsubuwm v3, v3, v2
1406 ; CHECK-PWR7-NEXT: vmaxsw v2, v2, v3
1407 ; CHECK-PWR7-NEXT: blr
1408 %3 = sext <4 x i16> %0 to <4 x i32>
1409 %4 = sext <4 x i16> %1 to <4 x i32>
1410 %5 = sub <4 x i32> %3, %4
1411 %6 = sub <4 x i32> zeroinitializer, %5
1412 %7 = tail call <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32> %5, <4 x i32> %6)
1413 ret <4 x i32> %7
1414 }
1416 define <8 x i16> @sext_sub_absd16(<8 x i8>, <8 x i8>) local_unnamed_addr {
1417 ; CHECK-PWR9-LE-LABEL: sext_sub_absd16:
1418 ; CHECK-PWR9-LE: # %bb.0:
1419 ; CHECK-PWR9-LE-NEXT: vminsb v4, v2, v3
1420 ; CHECK-PWR9-LE-NEXT: vmaxsb v2, v2, v3
1421 ; CHECK-PWR9-LE-NEXT: xxlxor v3, v3, v3
1422 ; CHECK-PWR9-LE-NEXT: vsububm v2, v2, v4
1423 ; CHECK-PWR9-LE-NEXT: vmrglb v2, v3, v2
1424 ; CHECK-PWR9-LE-NEXT: blr
1425 ;
1426 ; CHECK-PWR9-BE-LABEL: sext_sub_absd16:
1427 ; CHECK-PWR9-BE: # %bb.0:
1428 ; CHECK-PWR9-BE-NEXT: vminsb v4, v2, v3
1429 ; CHECK-PWR9-BE-NEXT: vmaxsb v2, v2, v3
1430 ; CHECK-PWR9-BE-NEXT: xxlxor v3, v3, v3
1431 ; CHECK-PWR9-BE-NEXT: vsububm v2, v2, v4
1432 ; CHECK-PWR9-BE-NEXT: vmrghb v2, v3, v2
1433 ; CHECK-PWR9-BE-NEXT: blr
1434 ;
1435 ; CHECK-PWR8-LABEL: sext_sub_absd16:
1436 ; CHECK-PWR8: # %bb.0:
1437 ; CHECK-PWR8-NEXT: vmrglb v2, v2, v2
1438 ; CHECK-PWR8-NEXT: vspltish v4, 8
1439 ; CHECK-PWR8-NEXT: vslh v2, v2, v4
1440 ; CHECK-PWR8-NEXT: vmrglb v3, v3, v3
1441 ; CHECK-PWR8-NEXT: vslh v3, v3, v4
1442 ; CHECK-PWR8-NEXT: vsrah v2, v2, v4
1443 ; CHECK-PWR8-NEXT: vsrah v3, v3, v4
1444 ; CHECK-PWR8-NEXT: vsubuhm v2, v2, v3
1445 ; CHECK-PWR8-NEXT: xxlxor v3, v3, v3
1446 ; CHECK-PWR8-NEXT: vsubuhm v3, v3, v2
1447 ; CHECK-PWR8-NEXT: vmaxsh v2, v2, v3
1448 ; CHECK-PWR8-NEXT: blr
1449 ;
1450 ; CHECK-PWR7-LABEL: sext_sub_absd16:
1451 ; CHECK-PWR7: # %bb.0:
1452 ; CHECK-PWR7-NEXT: vspltish v4, 8
1453 ; CHECK-PWR7-NEXT: vmrghb v2, v2, v2
1454 ; CHECK-PWR7-NEXT: vmrghb v3, v3, v3
1455 ; CHECK-PWR7-NEXT: vslh v2, v2, v4
1456 ; CHECK-PWR7-NEXT: vslh v3, v3, v4
1457 ; CHECK-PWR7-NEXT: vsrah v2, v2, v4
1458 ; CHECK-PWR7-NEXT: vsrah v3, v3, v4
1459 ; CHECK-PWR7-NEXT: vsubuhm v2, v2, v3
1460 ; CHECK-PWR7-NEXT: xxlxor v3, v3, v3
1461 ; CHECK-PWR7-NEXT: vsubuhm v3, v3, v2
1462 ; CHECK-PWR7-NEXT: vmaxsh v2, v2, v3
1463 ; CHECK-PWR7-NEXT: blr
1464 %3 = sext <8 x i8> %0 to <8 x i16>
1465 %4 = sext <8 x i8> %1 to <8 x i16>
1466 %5 = sub <8 x i16> %3, %4
1467 %6 = sub <8 x i16> zeroinitializer, %5
1468 %7 = tail call <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16> %5, <8 x i16> %6)
1469 ret <8 x i16> %7
1470 }
1472 define <16 x i8> @sext_sub_absd8(<16 x i4>, <16 x i4>) local_unnamed_addr {
1473 ; CHECK-PWR9-LABEL: sext_sub_absd8:
1474 ; CHECK-PWR9: # %bb.0:
1475 ; CHECK-PWR9-NEXT: xxspltib v4, 4
1476 ; CHECK-PWR9-NEXT: vslb v3, v3, v4
1477 ; CHECK-PWR9-NEXT: vslb v2, v2, v4
1478 ; CHECK-PWR9-NEXT: vsrab v3, v3, v4
1479 ; CHECK-PWR9-NEXT: vsrab v2, v2, v4
1480 ; CHECK-PWR9-NEXT: vminsb v4, v2, v3
1481 ; CHECK-PWR9-NEXT: vmaxsb v2, v2, v3
1482 ; CHECK-PWR9-NEXT: vsububm v2, v2, v4
1483 ; CHECK-PWR9-NEXT: blr
1484 ;
1485 ; CHECK-PWR78-LABEL: sext_sub_absd8:
1486 ; CHECK-PWR78: # %bb.0:
1487 ; CHECK-PWR78-NEXT: vspltisb v4, 4
1488 ; CHECK-PWR78-NEXT: vslb v2, v2, v4
1489 ; CHECK-PWR78-NEXT: vslb v3, v3, v4
1490 ; CHECK-PWR78-NEXT: vsrab v2, v2, v4
1491 ; CHECK-PWR78-NEXT: vsrab v3, v3, v4
1492 ; CHECK-PWR78-NEXT: vsububm v2, v2, v3
1493 ; CHECK-PWR78-NEXT: xxlxor v3, v3, v3
1494 ; CHECK-PWR78-NEXT: vsububm v3, v3, v2
1495 ; CHECK-PWR78-NEXT: vmaxsb v2, v2, v3
1496 ; CHECK-PWR78-NEXT: blr
1497 %3 = sext <16 x i4> %0 to <16 x i8>
1498 %4 = sext <16 x i4> %1 to <16 x i8>
1499 %5 = sub <16 x i8> %3, %4
1500 %6 = sub <16 x i8> zeroinitializer, %5
1501 %7 = tail call <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8> %5, <16 x i8> %6)
1502 ret <16 x i8> %7
1503 }
1505 ; To verify vabsdu* exploitation for ucmp + sub + select sequence
1507 define <4 x i32> @absd_int32_ugt(<4 x i32>, <4 x i32>) {
1508 ; CHECK-PWR9-LABEL: absd_int32_ugt:
1509 ; CHECK-PWR9: # %bb.0:
1510 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1511 ; CHECK-PWR9-NEXT: blr
1512 ;
1513 ; CHECK-PWR78-LABEL: absd_int32_ugt:
1514 ; CHECK-PWR78: # %bb.0:
1515 ; CHECK-PWR78-NEXT: vminuw v4, v2, v3
1516 ; CHECK-PWR78-NEXT: vmaxuw v2, v2, v3
1517 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4
1518 ; CHECK-PWR78-NEXT: blr
1519 %3 = icmp ugt <4 x i32> %0, %1
1520 %4 = sub <4 x i32> %0, %1
1521 %5 = sub <4 x i32> %1, %0
1522 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1523 ret <4 x i32> %6
1524 }
1526 define <4 x i32> @absd_int32_uge(<4 x i32>, <4 x i32>) {
1527 ; CHECK-PWR9-LABEL: absd_int32_uge:
1528 ; CHECK-PWR9: # %bb.0:
1529 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1530 ; CHECK-PWR9-NEXT: blr
1531 ;
1532 ; CHECK-PWR78-LABEL: absd_int32_uge:
1533 ; CHECK-PWR78: # %bb.0:
1534 ; CHECK-PWR78-NEXT: vminuw v4, v2, v3
1535 ; CHECK-PWR78-NEXT: vmaxuw v2, v2, v3
1536 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4
1537 ; CHECK-PWR78-NEXT: blr
1538 %3 = icmp uge <4 x i32> %0, %1
1539 %4 = sub <4 x i32> %0, %1
1540 %5 = sub <4 x i32> %1, %0
1541 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1542 ret <4 x i32> %6
1543 }
1545 define <4 x i32> @absd_int32_ult(<4 x i32>, <4 x i32>) {
1546 ; CHECK-PWR9-LABEL: absd_int32_ult:
1547 ; CHECK-PWR9: # %bb.0:
1548 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1549 ; CHECK-PWR9-NEXT: blr
1550 ;
1551 ; CHECK-PWR78-LABEL: absd_int32_ult:
1552 ; CHECK-PWR78: # %bb.0:
1553 ; CHECK-PWR78-NEXT: vminuw v4, v2, v3
1554 ; CHECK-PWR78-NEXT: vmaxuw v2, v2, v3
1555 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4
1556 ; CHECK-PWR78-NEXT: blr
1557 %3 = icmp ult <4 x i32> %0, %1
1558 %4 = sub <4 x i32> %0, %1
1559 %5 = sub <4 x i32> %1, %0
1560 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1561 ret <4 x i32> %6
1562 }
1564 define <4 x i32> @absd_int32_ule(<4 x i32>, <4 x i32>) {
1565 ; CHECK-PWR9-LABEL: absd_int32_ule:
1566 ; CHECK-PWR9: # %bb.0:
1567 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1568 ; CHECK-PWR9-NEXT: blr
1569 ;
1570 ; CHECK-PWR78-LABEL: absd_int32_ule:
1571 ; CHECK-PWR78: # %bb.0:
1572 ; CHECK-PWR78-NEXT: vminuw v4, v2, v3
1573 ; CHECK-PWR78-NEXT: vmaxuw v2, v2, v3
1574 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4
1575 ; CHECK-PWR78-NEXT: blr
1576 %3 = icmp ule <4 x i32> %0, %1
1577 %4 = sub <4 x i32> %0, %1
1578 %5 = sub <4 x i32> %1, %0
1579 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1580 ret <4 x i32> %6
1581 }
1583 define <8 x i16> @absd_int16_ugt(<8 x i16>, <8 x i16>) {
1584 ; CHECK-PWR9-LABEL: absd_int16_ugt:
1585 ; CHECK-PWR9: # %bb.0:
1586 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1587 ; CHECK-PWR9-NEXT: blr
1588 ;
1589 ; CHECK-PWR78-LABEL: absd_int16_ugt:
1590 ; CHECK-PWR78: # %bb.0:
1591 ; CHECK-PWR78-NEXT: vminuh v4, v2, v3
1592 ; CHECK-PWR78-NEXT: vmaxuh v2, v2, v3
1593 ; CHECK-PWR78-NEXT: vsubuhm v2, v2, v4
1594 ; CHECK-PWR78-NEXT: blr
1595 %3 = icmp ugt <8 x i16> %0, %1
1596 %4 = sub <8 x i16> %0, %1
1597 %5 = sub <8 x i16> %1, %0
1598 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1599 ret <8 x i16> %6
1600 }
1602 define <8 x i16> @absd_int16_uge(<8 x i16>, <8 x i16>) {
1603 ; CHECK-PWR9-LABEL: absd_int16_uge:
1604 ; CHECK-PWR9: # %bb.0:
1605 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1606 ; CHECK-PWR9-NEXT: blr
1607 ;
1608 ; CHECK-PWR78-LABEL: absd_int16_uge:
1609 ; CHECK-PWR78: # %bb.0:
1610 ; CHECK-PWR78-NEXT: vminuh v4, v2, v3
1611 ; CHECK-PWR78-NEXT: vmaxuh v2, v2, v3
1612 ; CHECK-PWR78-NEXT: vsubuhm v2, v2, v4
1613 ; CHECK-PWR78-NEXT: blr
1614 %3 = icmp uge <8 x i16> %0, %1
1615 %4 = sub <8 x i16> %0, %1
1616 %5 = sub <8 x i16> %1, %0
1617 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1618 ret <8 x i16> %6
1619 }
1621 define <8 x i16> @absd_int16_ult(<8 x i16>, <8 x i16>) {
1622 ; CHECK-PWR9-LABEL: absd_int16_ult:
1623 ; CHECK-PWR9: # %bb.0:
1624 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1625 ; CHECK-PWR9-NEXT: blr
1626 ;
1627 ; CHECK-PWR78-LABEL: absd_int16_ult:
1628 ; CHECK-PWR78: # %bb.0:
1629 ; CHECK-PWR78-NEXT: vminuh v4, v2, v3
1630 ; CHECK-PWR78-NEXT: vmaxuh v2, v2, v3
1631 ; CHECK-PWR78-NEXT: vsubuhm v2, v2, v4
1632 ; CHECK-PWR78-NEXT: blr
1633 %3 = icmp ult <8 x i16> %0, %1
1634 %4 = sub <8 x i16> %0, %1
1635 %5 = sub <8 x i16> %1, %0
1636 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1637 ret <8 x i16> %6
1638 }
1640 define <8 x i16> @absd_int16_ule(<8 x i16>, <8 x i16>) {
1641 ; CHECK-PWR9-LABEL: absd_int16_ule:
1642 ; CHECK-PWR9: # %bb.0:
1643 ; CHECK-PWR9-NEXT: vabsduh v2, v2, v3
1644 ; CHECK-PWR9-NEXT: blr
1645 ;
1646 ; CHECK-PWR78-LABEL: absd_int16_ule:
1647 ; CHECK-PWR78: # %bb.0:
1648 ; CHECK-PWR78-NEXT: vminuh v4, v2, v3
1649 ; CHECK-PWR78-NEXT: vmaxuh v2, v2, v3
1650 ; CHECK-PWR78-NEXT: vsubuhm v2, v2, v4
1651 ; CHECK-PWR78-NEXT: blr
1652 %3 = icmp ule <8 x i16> %0, %1
1653 %4 = sub <8 x i16> %0, %1
1654 %5 = sub <8 x i16> %1, %0
1655 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1656 ret <8 x i16> %6
1657 }
1659 define <16 x i8> @absd_int8_ugt(<16 x i8>, <16 x i8>) {
1660 ; CHECK-PWR9-LABEL: absd_int8_ugt:
1661 ; CHECK-PWR9: # %bb.0:
1662 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1663 ; CHECK-PWR9-NEXT: blr
1664 ;
1665 ; CHECK-PWR78-LABEL: absd_int8_ugt:
1666 ; CHECK-PWR78: # %bb.0:
1667 ; CHECK-PWR78-NEXT: vminub v4, v2, v3
1668 ; CHECK-PWR78-NEXT: vmaxub v2, v2, v3
1669 ; CHECK-PWR78-NEXT: vsububm v2, v2, v4
1670 ; CHECK-PWR78-NEXT: blr
1671 %3 = icmp ugt <16 x i8> %0, %1
1672 %4 = sub <16 x i8> %0, %1
1673 %5 = sub <16 x i8> %1, %0
1674 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1675 ret <16 x i8> %6
1676 }
1678 define <16 x i8> @absd_int8_uge(<16 x i8>, <16 x i8>) {
1679 ; CHECK-PWR9-LABEL: absd_int8_uge:
1680 ; CHECK-PWR9: # %bb.0:
1681 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1682 ; CHECK-PWR9-NEXT: blr
1683 ;
1684 ; CHECK-PWR78-LABEL: absd_int8_uge:
1685 ; CHECK-PWR78: # %bb.0:
1686 ; CHECK-PWR78-NEXT: vminub v4, v2, v3
1687 ; CHECK-PWR78-NEXT: vmaxub v2, v2, v3
1688 ; CHECK-PWR78-NEXT: vsububm v2, v2, v4
1689 ; CHECK-PWR78-NEXT: blr
1690 %3 = icmp uge <16 x i8> %0, %1
1691 %4 = sub <16 x i8> %0, %1
1692 %5 = sub <16 x i8> %1, %0
1693 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1694 ret <16 x i8> %6
1695 }
1697 define <16 x i8> @absd_int8_ult(<16 x i8>, <16 x i8>) {
1698 ; CHECK-PWR9-LABEL: absd_int8_ult:
1699 ; CHECK-PWR9: # %bb.0:
1700 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1701 ; CHECK-PWR9-NEXT: blr
1702 ;
1703 ; CHECK-PWR78-LABEL: absd_int8_ult:
1704 ; CHECK-PWR78: # %bb.0:
1705 ; CHECK-PWR78-NEXT: vminub v4, v2, v3
1706 ; CHECK-PWR78-NEXT: vmaxub v2, v2, v3
1707 ; CHECK-PWR78-NEXT: vsububm v2, v2, v4
1708 ; CHECK-PWR78-NEXT: blr
1709 %3 = icmp ult <16 x i8> %0, %1
1710 %4 = sub <16 x i8> %0, %1
1711 %5 = sub <16 x i8> %1, %0
1712 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1713 ret <16 x i8> %6
1714 }
1716 define <16 x i8> @absd_int8_ule(<16 x i8>, <16 x i8>) {
1717 ; CHECK-PWR9-LABEL: absd_int8_ule:
1718 ; CHECK-PWR9: # %bb.0:
1719 ; CHECK-PWR9-NEXT: vabsdub v2, v2, v3
1720 ; CHECK-PWR9-NEXT: blr
1721 ;
1722 ; CHECK-PWR78-LABEL: absd_int8_ule:
1723 ; CHECK-PWR78: # %bb.0:
1724 ; CHECK-PWR78-NEXT: vminub v4, v2, v3
1725 ; CHECK-PWR78-NEXT: vmaxub v2, v2, v3
1726 ; CHECK-PWR78-NEXT: vsububm v2, v2, v4
1727 ; CHECK-PWR78-NEXT: blr
1728 %3 = icmp ule <16 x i8> %0, %1
1729 %4 = sub <16 x i8> %0, %1
1730 %5 = sub <16 x i8> %1, %0
1731 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1732 ret <16 x i8> %6
1733 }
1735 ; Tests for ABDS icmp + sub + select sequence
1737 define <4 x i32> @absd_int32_sgt(<4 x i32>, <4 x i32>) {
1738 ; CHECK-PWR9-LABEL: absd_int32_sgt:
1739 ; CHECK-PWR9: # %bb.0:
1740 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1741 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1742 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1743 ; CHECK-PWR9-NEXT: blr
1744 ;
1745 ; CHECK-PWR78-LABEL: absd_int32_sgt:
1746 ; CHECK-PWR78: # %bb.0:
1747 ; CHECK-PWR78-NEXT: vminsw v4, v2, v3
1748 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
1749 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4
1750 ; CHECK-PWR78-NEXT: blr
1751 %3 = icmp sgt <4 x i32> %0, %1
1752 %4 = sub <4 x i32> %0, %1
1753 %5 = sub <4 x i32> %1, %0
1754 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1755 ret <4 x i32> %6
1756 }
1758 define <4 x i32> @absd_int32_sge(<4 x i32>, <4 x i32>) {
1759 ; CHECK-PWR9-LABEL: absd_int32_sge:
1760 ; CHECK-PWR9: # %bb.0:
1761 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1762 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1763 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1764 ; CHECK-PWR9-NEXT: blr
1765 ;
1766 ; CHECK-PWR78-LABEL: absd_int32_sge:
1767 ; CHECK-PWR78: # %bb.0:
1768 ; CHECK-PWR78-NEXT: vminsw v4, v2, v3
1769 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
1770 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4
1771 ; CHECK-PWR78-NEXT: blr
1772 %3 = icmp sge <4 x i32> %0, %1
1773 %4 = sub <4 x i32> %0, %1
1774 %5 = sub <4 x i32> %1, %0
1775 %6 = select <4 x i1> %3, <4 x i32> %4, <4 x i32> %5
1776 ret <4 x i32> %6
1777 }
1779 define <4 x i32> @absd_int32_slt(<4 x i32>, <4 x i32>) {
1780 ; CHECK-PWR9-LABEL: absd_int32_slt:
1781 ; CHECK-PWR9: # %bb.0:
1782 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1783 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1784 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1785 ; CHECK-PWR9-NEXT: blr
1786 ;
1787 ; CHECK-PWR78-LABEL: absd_int32_slt:
1788 ; CHECK-PWR78: # %bb.0:
1789 ; CHECK-PWR78-NEXT: vminsw v4, v2, v3
1790 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
1791 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4
1792 ; CHECK-PWR78-NEXT: blr
1793 %3 = icmp slt <4 x i32> %0, %1
1794 %4 = sub <4 x i32> %0, %1
1795 %5 = sub <4 x i32> %1, %0
1796 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1797 ret <4 x i32> %6
1798 }
1800 define <4 x i32> @absd_int32_sle(<4 x i32>, <4 x i32>) {
1801 ; CHECK-PWR9-LABEL: absd_int32_sle:
1802 ; CHECK-PWR9: # %bb.0:
1803 ; CHECK-PWR9-NEXT: xvnegsp v3, v3
1804 ; CHECK-PWR9-NEXT: xvnegsp v2, v2
1805 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1806 ; CHECK-PWR9-NEXT: blr
1807 ;
1808 ; CHECK-PWR78-LABEL: absd_int32_sle:
1809 ; CHECK-PWR78: # %bb.0:
1810 ; CHECK-PWR78-NEXT: vminsw v4, v2, v3
1811 ; CHECK-PWR78-NEXT: vmaxsw v2, v2, v3
1812 ; CHECK-PWR78-NEXT: vsubuwm v2, v2, v4
1813 ; CHECK-PWR78-NEXT: blr
1814 %3 = icmp sle <4 x i32> %0, %1
1815 %4 = sub <4 x i32> %0, %1
1816 %5 = sub <4 x i32> %1, %0
1817 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1818 ret <4 x i32> %6
1819 }
1821 define <8 x i16> @absd_int16_sgt(<8 x i16>, <8 x i16>) {
1822 ; CHECK-LABEL: absd_int16_sgt:
1823 ; CHECK: # %bb.0:
1824 ; CHECK-NEXT: vminsh v4, v2, v3
1825 ; CHECK-NEXT: vmaxsh v2, v2, v3
1826 ; CHECK-NEXT: vsubuhm v2, v2, v4
1827 ; CHECK-NEXT: blr
1828 %3 = icmp sgt <8 x i16> %0, %1
1829 %4 = sub <8 x i16> %0, %1
1830 %5 = sub <8 x i16> %1, %0
1831 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1832 ret <8 x i16> %6
1833 }
1835 define <8 x i16> @absd_int16_sge(<8 x i16>, <8 x i16>) {
1836 ; CHECK-LABEL: absd_int16_sge:
1837 ; CHECK: # %bb.0:
1838 ; CHECK-NEXT: vminsh v4, v2, v3
1839 ; CHECK-NEXT: vmaxsh v2, v2, v3
1840 ; CHECK-NEXT: vsubuhm v2, v2, v4
1841 ; CHECK-NEXT: blr
1842 %3 = icmp sge <8 x i16> %0, %1
1843 %4 = sub <8 x i16> %0, %1
1844 %5 = sub <8 x i16> %1, %0
1845 %6 = select <8 x i1> %3, <8 x i16> %4, <8 x i16> %5
1846 ret <8 x i16> %6
1847 }
1849 define <8 x i16> @absd_int16_slt(<8 x i16>, <8 x i16>) {
1850 ; CHECK-LABEL: absd_int16_slt:
1851 ; CHECK: # %bb.0:
1852 ; CHECK-NEXT: vminsh v4, v2, v3
1853 ; CHECK-NEXT: vmaxsh v2, v2, v3
1854 ; CHECK-NEXT: vsubuhm v2, v2, v4
1855 ; CHECK-NEXT: blr
1856 %3 = icmp slt <8 x i16> %0, %1
1857 %4 = sub <8 x i16> %0, %1
1858 %5 = sub <8 x i16> %1, %0
1859 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1860 ret <8 x i16> %6
1861 }
1863 define <8 x i16> @absd_int16_sle(<8 x i16>, <8 x i16>) {
1864 ; CHECK-LABEL: absd_int16_sle:
1865 ; CHECK: # %bb.0:
1866 ; CHECK-NEXT: vminsh v4, v2, v3
1867 ; CHECK-NEXT: vmaxsh v2, v2, v3
1868 ; CHECK-NEXT: vsubuhm v2, v2, v4
1869 ; CHECK-NEXT: blr
1870 %3 = icmp sle <8 x i16> %0, %1
1871 %4 = sub <8 x i16> %0, %1
1872 %5 = sub <8 x i16> %1, %0
1873 %6 = select <8 x i1> %3, <8 x i16> %5, <8 x i16> %4
1874 ret <8 x i16> %6
1875 }
1877 define <16 x i8> @absd_int8_sgt(<16 x i8>, <16 x i8>) {
1878 ; CHECK-LABEL: absd_int8_sgt:
1879 ; CHECK: # %bb.0:
1880 ; CHECK-NEXT: vminsb v4, v2, v3
1881 ; CHECK-NEXT: vmaxsb v2, v2, v3
1882 ; CHECK-NEXT: vsububm v2, v2, v4
1883 ; CHECK-NEXT: blr
1884 %3 = icmp sgt <16 x i8> %0, %1
1885 %4 = sub <16 x i8> %0, %1
1886 %5 = sub <16 x i8> %1, %0
1887 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1888 ret <16 x i8> %6
1889 }
1891 define <16 x i8> @absd_int8_sge(<16 x i8>, <16 x i8>) {
1892 ; CHECK-LABEL: absd_int8_sge:
1893 ; CHECK: # %bb.0:
1894 ; CHECK-NEXT: vminsb v4, v2, v3
1895 ; CHECK-NEXT: vmaxsb v2, v2, v3
1896 ; CHECK-NEXT: vsububm v2, v2, v4
1897 ; CHECK-NEXT: blr
1898 %3 = icmp sge <16 x i8> %0, %1
1899 %4 = sub <16 x i8> %0, %1
1900 %5 = sub <16 x i8> %1, %0
1901 %6 = select <16 x i1> %3, <16 x i8> %4, <16 x i8> %5
1902 ret <16 x i8> %6
1903 }
1905 define <16 x i8> @absd_int8_slt(<16 x i8>, <16 x i8>) {
1906 ; CHECK-LABEL: absd_int8_slt:
1907 ; CHECK: # %bb.0:
1908 ; CHECK-NEXT: vminsb v4, v2, v3
1909 ; CHECK-NEXT: vmaxsb v2, v2, v3
1910 ; CHECK-NEXT: vsububm v2, v2, v4
1911 ; CHECK-NEXT: blr
1912 %3 = icmp slt <16 x i8> %0, %1
1913 %4 = sub <16 x i8> %0, %1
1914 %5 = sub <16 x i8> %1, %0
1915 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1916 ret <16 x i8> %6
1917 }
1919 define <16 x i8> @absd_int8_sle(<16 x i8>, <16 x i8>) {
1920 ; CHECK-LABEL: absd_int8_sle:
1921 ; CHECK: # %bb.0:
1922 ; CHECK-NEXT: vminsb v4, v2, v3
1923 ; CHECK-NEXT: vmaxsb v2, v2, v3
1924 ; CHECK-NEXT: vsububm v2, v2, v4
1925 ; CHECK-NEXT: blr
1926 %3 = icmp sle <16 x i8> %0, %1
1927 %4 = sub <16 x i8> %0, %1
1928 %5 = sub <16 x i8> %1, %0
1929 %6 = select <16 x i1> %3, <16 x i8> %5, <16 x i8> %4
1930 ret <16 x i8> %6
1931 }
1933 ; some cases we are unable to optimize
1934 ; check whether goes beyond the scope
1935 define <4 x i32> @absd_int32_ugt_opp(<4 x i32>, <4 x i32>) {
1936 ; CHECK-PWR9-LABEL: absd_int32_ugt_opp:
1937 ; CHECK-PWR9: # %bb.0:
1938 ; CHECK-PWR9-NEXT: vabsduw v2, v2, v3
1939 ; CHECK-PWR9-NEXT: vnegw v2, v2
1940 ; CHECK-PWR9-NEXT: blr
1941 ;
1942 ; CHECK-PWR78-LABEL: absd_int32_ugt_opp:
1943 ; CHECK-PWR78: # %bb.0:
1944 ; CHECK-PWR78-NEXT: vcmpgtuw v4, v2, v3
1945 ; CHECK-PWR78-NEXT: vsubuwm v5, v2, v3
1946 ; CHECK-PWR78-NEXT: vsubuwm v2, v3, v2
1947 ; CHECK-PWR78-NEXT: xxsel v2, v5, v2, v4
1948 ; CHECK-PWR78-NEXT: blr
1949 %3 = icmp ugt <4 x i32> %0, %1
1950 %4 = sub <4 x i32> %0, %1
1951 %5 = sub <4 x i32> %1, %0
1952 %6 = select <4 x i1> %3, <4 x i32> %5, <4 x i32> %4
1953 ret <4 x i32> %6
1954 }
1956 define <2 x i64> @absd_int64_ugt(<2 x i64>, <2 x i64>) {
1957 ; CHECK-PWR9-LABEL: absd_int64_ugt:
1958 ; CHECK-PWR9: # %bb.0:
1959 ; CHECK-PWR9-NEXT: vminud v4, v2, v3
1960 ; CHECK-PWR9-NEXT: vmaxud v2, v2, v3
1961 ; CHECK-PWR9-NEXT: vsubudm v2, v2, v4
1962 ; CHECK-PWR9-NEXT: blr
1963 ;
1964 ; CHECK-PWR8-LABEL: absd_int64_ugt:
1965 ; CHECK-PWR8: # %bb.0:
1966 ; CHECK-PWR8-NEXT: vminud v4, v2, v3
1967 ; CHECK-PWR8-NEXT: vmaxud v2, v2, v3
1968 ; CHECK-PWR8-NEXT: vsubudm v2, v2, v4
1969 ; CHECK-PWR8-NEXT: blr
1970 ;
1971 ; CHECK-PWR7-LABEL: absd_int64_ugt:
1972 ; CHECK-PWR7: # %bb.0:
1973 ; CHECK-PWR7-NEXT: addi r3, r1, -96
1974 ; CHECK-PWR7-NEXT: stxvd2x v2, 0, r3
1975 ; CHECK-PWR7-NEXT: addi r3, r1, -80
1976 ; CHECK-PWR7-NEXT: stxvd2x v3, 0, r3
1977 ; CHECK-PWR7-NEXT: ld r3, -88(r1)
1978 ; CHECK-PWR7-NEXT: ld r4, -72(r1)
1979 ; CHECK-PWR7-NEXT: ld r6, -80(r1)
1980 ; CHECK-PWR7-NEXT: sub r5, r3, r4
1981 ; CHECK-PWR7-NEXT: cmpld r3, r4
1982 ; CHECK-PWR7-NEXT: li r3, 0
1983 ; CHECK-PWR7-NEXT: li r4, -1
1984 ; CHECK-PWR7-NEXT: std r5, -56(r1)
1985 ; CHECK-PWR7-NEXT: ld r5, -96(r1)
1986 ; CHECK-PWR7-NEXT: sub r7, r5, r6
1987 ; CHECK-PWR7-NEXT: std r7, -64(r1)
1988 ; CHECK-PWR7-NEXT: iselgt r7, r4, r3
1989 ; CHECK-PWR7-NEXT: cmpld r5, r6
1990 ; CHECK-PWR7-NEXT: std r7, -40(r1)
1991 ; CHECK-PWR7-NEXT: iselgt r3, r4, r3
1992 ; CHECK-PWR7-NEXT: addi r4, r1, -64
1993 ; CHECK-PWR7-NEXT: std r3, -48(r1)
1994 ; CHECK-PWR7-NEXT: lxvw4x vs0, 0, r4
1995 ; CHECK-PWR7-NEXT: addi r4, r1, -48
1996 ; CHECK-PWR7-NEXT: lxvw4x vs1, 0, r4
1997 ; CHECK-PWR7-NEXT: addi r4, r1, -32
1998 ; CHECK-PWR7-NEXT: xxlxor vs0, vs0, vs1
1999 ; CHECK-PWR7-NEXT: stxvw4x vs0, 0, r4
2000 ; CHECK-PWR7-NEXT: ld r4, -24(r1)
2001 ; CHECK-PWR7-NEXT: sub r4, r7, r4
2002 ; CHECK-PWR7-NEXT: std r4, -8(r1)
2003 ; CHECK-PWR7-NEXT: ld r4, -32(r1)
2004 ; CHECK-PWR7-NEXT: sub r3, r3, r4
2005 ; CHECK-PWR7-NEXT: std r3, -16(r1)
2006 ; CHECK-PWR7-NEXT: addi r3, r1, -16
2007 ; CHECK-PWR7-NEXT: lxvd2x v2, 0, r3
2008 ; CHECK-PWR7-NEXT: blr
2009 %3 = icmp ugt <2 x i64> %0, %1
2010 %4 = sub <2 x i64> %0, %1
2011 %5 = sub <2 x i64> %1, %0
2012 %6 = select <2 x i1> %3, <2 x i64> %4, <2 x i64> %5
2013 ret <2 x i64> %6
2014 }
2016 declare <4 x i32> @llvm.ppc.altivec.vmaxsw(<4 x i32>, <4 x i32>)
2018 declare <8 x i16> @llvm.ppc.altivec.vmaxsh(<8 x i16>, <8 x i16>)
2020 declare <16 x i8> @llvm.ppc.altivec.vmaxsb(<16 x i8>, <16 x i8>)