| blob | 20dcb8ccf4908a924f5bf8c4afbe7fc378e8b06e |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr8 < %s | FileCheck %s
4 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
5 ; RUN: < %s -vec-extabi | FileCheck %s
7 %class.PB2 = type { [1 x i32], ptr }
8 %class.PB1 = type { [1 x i32], i64, i64, i32 }
10 ; Function Attrs: norecurse nounwind readonly
11 define zeroext i1 @test1(ptr %s_a, ptr %s_b) local_unnamed_addr #0 {
12 ; CHECK-LABEL: test1:
13 ; CHECK: # %bb.0: # %entry
14 ; CHECK-NEXT: lwz 3, 0(3)
15 ; CHECK-NEXT: lwz 4, 0(4)
16 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
17 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
18 ; CHECK-NEXT: sub 3, 3, 4
19 ; CHECK-NEXT: rldicl 3, 3, 1, 63
20 ; CHECK-NEXT: blr
21 entry:
22 %0 = load i32, ptr %s_a, align 8, !tbaa !1
23 %and.i = and i32 %0, 8
24 %1 = load i32, ptr %s_b, align 8, !tbaa !1
25 %and.i4 = and i32 %1, 8
26 %cmp.i5 = icmp ult i32 %and.i, %and.i4
27 ret i1 %cmp.i5
28 }
30 ; Function Attrs: norecurse nounwind readonly
31 define zeroext i1 @test2(ptr %s_a, ptr %s_b) local_unnamed_addr #0 {
32 ; CHECK-LABEL: test2:
33 ; CHECK: # %bb.0: # %entry
34 ; CHECK-NEXT: lwz 3, 0(3)
35 ; CHECK-NEXT: lwz 4, 0(4)
36 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
37 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
38 ; CHECK-NEXT: sub 3, 4, 3
39 ; CHECK-NEXT: not 3, 3
40 ; CHECK-NEXT: rldicl 3, 3, 1, 63
41 ; CHECK-NEXT: blr
42 entry:
43 %0 = load i32, ptr %s_a, align 8, !tbaa !1
44 %and.i = and i32 %0, 8
45 %1 = load i32, ptr %s_b, align 8, !tbaa !1
46 %and.i4 = and i32 %1, 8
47 %cmp.i5 = icmp ule i32 %and.i, %and.i4
48 ret i1 %cmp.i5
49 }
51 ; Function Attrs: norecurse nounwind readonly
52 define zeroext i1 @test3(ptr %s_a, ptr %s_b) local_unnamed_addr #0 {
53 ; CHECK-LABEL: test3:
54 ; CHECK: # %bb.0: # %entry
55 ; CHECK-NEXT: lwz 3, 0(3)
56 ; CHECK-NEXT: lwz 4, 0(4)
57 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
58 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
59 ; CHECK-NEXT: sub 3, 4, 3
60 ; CHECK-NEXT: rldicl 3, 3, 1, 63
61 ; CHECK-NEXT: blr
62 entry:
63 %0 = load i32, ptr %s_a, align 8, !tbaa !1
64 %and.i = and i32 %0, 8
65 %1 = load i32, ptr %s_b, align 8, !tbaa !1
66 %and.i4 = and i32 %1, 8
67 %cmp.i5 = icmp ugt i32 %and.i, %and.i4
68 ret i1 %cmp.i5
69 }
71 ; Function Attrs: norecurse nounwind readonly
72 define zeroext i1 @test4(ptr %s_a, ptr %s_b) local_unnamed_addr #0 {
73 ; CHECK-LABEL: test4:
74 ; CHECK: # %bb.0: # %entry
75 ; CHECK-NEXT: lwz 3, 0(3)
76 ; CHECK-NEXT: lwz 4, 0(4)
77 ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28
78 ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28
79 ; CHECK-NEXT: sub 3, 3, 4
80 ; CHECK-NEXT: not 3, 3
81 ; CHECK-NEXT: rldicl 3, 3, 1, 63
82 ; CHECK-NEXT: blr
83 entry:
84 %0 = load i32, ptr %s_a, align 8, !tbaa !1
85 %and.i = and i32 %0, 8
86 %1 = load i32, ptr %s_b, align 8, !tbaa !1
87 %and.i4 = and i32 %1, 8
88 %cmp.i5 = icmp uge i32 %and.i, %and.i4
89 ret i1 %cmp.i5
90 }
92 define zeroext i1 @test5(i64 %a) {
93 ; CHECK-LABEL: test5:
94 ; CHECK: # %bb.0: # %entry
95 ; CHECK-NEXT: li 4, -1
96 ; CHECK-NEXT: addis 3, 3, -32768
97 ; CHECK-NEXT: rldic 4, 4, 32, 0
98 ; CHECK-NEXT: subc 4, 3, 4
99 ; CHECK-NEXT: subfe 3, 3, 3
100 ; CHECK-NEXT: neg 3, 3
101 ; CHECK-NEXT: blr
102 entry:
103 %0 = add i64 %a, -2147483648
104 %cmp = icmp ult i64 %0, -4294967296
105 ret i1 %cmp
106 }
108 define zeroext i1 @test6(i64 %a) {
109 ; CHECK-LABEL: test6:
110 ; CHECK: # %bb.0: # %entry
111 ; CHECK-NEXT: addi 3, 3, -32768
112 ; CHECK-NEXT: lis 4, -1
113 ; CHECK-NEXT: subc 4, 3, 4
114 ; CHECK-NEXT: subfe 3, 3, 3
115 ; CHECK-NEXT: neg 3, 3
116 ; CHECK-NEXT: blr
117 entry:
118 %0 = add i64 %a, -32768
119 %cmp = icmp ult i64 %0, -65536
120 ret i1 %cmp
121 }
123 define zeroext i1 @test7(i64 %a) {
124 ; CHECK-LABEL: test7:
125 ; CHECK: # %bb.0: # %entry
126 ; CHECK-NEXT: addi 3, 3, -128
127 ; CHECK-NEXT: li 4, -256
128 ; CHECK-NEXT: subc 4, 3, 4
129 ; CHECK-NEXT: subfe 3, 3, 3
130 ; CHECK-NEXT: neg 3, 3
131 ; CHECK-NEXT: blr
132 entry:
133 %0 = add i64 %a, -128
134 %cmp = icmp ult i64 %0, -256
135 ret i1 %cmp
136 }
138 define zeroext i1 @test8(i32 %a) {
139 ; CHECK-LABEL: test8:
140 ; CHECK: # %bb.0: # %entry
141 ; CHECK-NEXT: addi 3, 3, -32768
142 ; CHECK-NEXT: lis 4, -1
143 ; CHECK-NEXT: rlwinm 3, 3, 16, 16, 31
144 ; CHECK-NEXT: ori 4, 4, 1
145 ; CHECK-NEXT: add 3, 3, 4
146 ; CHECK-NEXT: rldicl 3, 3, 1, 63
147 ; CHECK-NEXT: blr
148 entry:
149 %0 = add i32 %a, -32768
150 %cmp = icmp ult i32 %0, -65536
151 ret i1 %cmp
152 }
154 define zeroext i1 @test9(i32 %a) {
155 ; CHECK-LABEL: test9:
156 ; CHECK: # %bb.0: # %entry
157 ; CHECK-NEXT: lis 4, -256
158 ; CHECK-NEXT: addi 3, 3, -128
159 ; CHECK-NEXT: ori 4, 4, 1
160 ; CHECK-NEXT: clrldi 3, 3, 32
161 ; CHECK-NEXT: rldic 4, 4, 8, 0
162 ; CHECK-NEXT: add 3, 3, 4
163 ; CHECK-NEXT: rldicl 3, 3, 1, 63
164 ; CHECK-NEXT: blr
165 entry:
166 %0 = add i32 %a, -128
167 %cmp = icmp ult i32 %0, -256
168 ret i1 %cmp
169 }
171 define zeroext i1 @test10(i16 %a) {
172 ; CHECK-LABEL: test10:
173 ; CHECK: # %bb.0: # %entry
174 ; CHECK-NEXT: addi 3, 3, -128
175 ; CHECK-NEXT: lis 4, -1
176 ; CHECK-NEXT: clrlwi 3, 3, 16
177 ; CHECK-NEXT: ori 4, 4, 256
178 ; CHECK-NEXT: add 3, 3, 4
179 ; CHECK-NEXT: rldicl 3, 3, 1, 63
180 ; CHECK-NEXT: blr
181 entry:
182 %0 = add i16 %a, -128
183 %cmp = icmp ult i16 %0, -256
184 ret i1 %cmp
185 }
187 !1 = !{!2, !2, i64 0}
188 !2 = !{!"int", !3, i64 0}
189 !3 = !{!"omnipotent char", !4, i64 0}
190 !4 = !{!"Simple C++ TBAA"}