| blob | 6c848ecf0fffdb92a3bbc657888c23f9ba87611b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2 ; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s --check-prefixes=RV32I
4 ; RUN: llc -mtriple=riscv32 -global-isel -mattr=+zbb -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s --check-prefixes=RV32ZBB
6 ; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
7 ; RUN: | FileCheck %s --check-prefixes=RV64I
8 ; RUN: llc -mtriple=riscv64 -global-isel -mattr=+zbb -verify-machineinstrs < %s \
9 ; RUN: | FileCheck %s --check-prefixes=RV64ZBB
11 define i32 @expanded_neg_abs32(i32 %x) {
12 ; RV32I-LABEL: expanded_neg_abs32:
13 ; RV32I: # %bb.0:
14 ; RV32I-NEXT: neg a1, a0
15 ; RV32I-NEXT: blt a0, a1, .LBB0_2
16 ; RV32I-NEXT: # %bb.1:
17 ; RV32I-NEXT: mv a1, a0
18 ; RV32I-NEXT: .LBB0_2:
19 ; RV32I-NEXT: neg a0, a1
20 ; RV32I-NEXT: ret
21 ;
22 ; RV32ZBB-LABEL: expanded_neg_abs32:
23 ; RV32ZBB: # %bb.0:
24 ; RV32ZBB-NEXT: neg a1, a0
25 ; RV32ZBB-NEXT: min a0, a0, a1
26 ; RV32ZBB-NEXT: ret
27 ;
28 ; RV64I-LABEL: expanded_neg_abs32:
29 ; RV64I: # %bb.0:
30 ; RV64I-NEXT: neg a1, a0
31 ; RV64I-NEXT: sext.w a2, a1
32 ; RV64I-NEXT: sext.w a3, a0
33 ; RV64I-NEXT: blt a3, a2, .LBB0_2
34 ; RV64I-NEXT: # %bb.1:
35 ; RV64I-NEXT: mv a1, a0
36 ; RV64I-NEXT: .LBB0_2:
37 ; RV64I-NEXT: neg a0, a1
38 ; RV64I-NEXT: ret
39 ;
40 ; RV64ZBB-LABEL: expanded_neg_abs32:
41 ; RV64ZBB: # %bb.0:
42 ; RV64ZBB-NEXT: negw a1, a0
43 ; RV64ZBB-NEXT: sext.w a0, a0
44 ; RV64ZBB-NEXT: max a0, a1, a0
45 ; RV64ZBB-NEXT: neg a0, a0
46 ; RV64ZBB-NEXT: ret
47 %n = sub i32 0, %x
48 %t = call i32 @llvm.smax.i32(i32 %n, i32 %x)
49 %r = sub i32 0, %t
50 ret i32 %r
51 }
53 define i32 @expanded_neg_abs32_unsigned(i32 %x) {
54 ; RV32I-LABEL: expanded_neg_abs32_unsigned:
55 ; RV32I: # %bb.0:
56 ; RV32I-NEXT: neg a1, a0
57 ; RV32I-NEXT: bltu a0, a1, .LBB1_2
58 ; RV32I-NEXT: # %bb.1:
59 ; RV32I-NEXT: mv a1, a0
60 ; RV32I-NEXT: .LBB1_2:
61 ; RV32I-NEXT: neg a0, a1
62 ; RV32I-NEXT: ret
63 ;
64 ; RV32ZBB-LABEL: expanded_neg_abs32_unsigned:
65 ; RV32ZBB: # %bb.0:
66 ; RV32ZBB-NEXT: neg a1, a0
67 ; RV32ZBB-NEXT: minu a0, a0, a1
68 ; RV32ZBB-NEXT: ret
69 ;
70 ; RV64I-LABEL: expanded_neg_abs32_unsigned:
71 ; RV64I: # %bb.0:
72 ; RV64I-NEXT: neg a1, a0
73 ; RV64I-NEXT: sext.w a2, a1
74 ; RV64I-NEXT: sext.w a3, a0
75 ; RV64I-NEXT: bltu a3, a2, .LBB1_2
76 ; RV64I-NEXT: # %bb.1:
77 ; RV64I-NEXT: mv a1, a0
78 ; RV64I-NEXT: .LBB1_2:
79 ; RV64I-NEXT: neg a0, a1
80 ; RV64I-NEXT: ret
81 ;
82 ; RV64ZBB-LABEL: expanded_neg_abs32_unsigned:
83 ; RV64ZBB: # %bb.0:
84 ; RV64ZBB-NEXT: negw a1, a0
85 ; RV64ZBB-NEXT: sext.w a0, a0
86 ; RV64ZBB-NEXT: maxu a0, a1, a0
87 ; RV64ZBB-NEXT: neg a0, a0
88 ; RV64ZBB-NEXT: ret
89 %n = sub i32 0, %x
90 %t = call i32 @llvm.umax.i32(i32 %n, i32 %x)
91 %r = sub i32 0, %t
92 ret i32 %r
93 }
95 define i64 @expanded_neg_abs64(i64 %x) {
96 ; RV32I-LABEL: expanded_neg_abs64:
97 ; RV32I: # %bb.0:
98 ; RV32I-NEXT: snez a2, a0
99 ; RV32I-NEXT: neg a3, a1
100 ; RV32I-NEXT: sub a2, a3, a2
101 ; RV32I-NEXT: neg a3, a0
102 ; RV32I-NEXT: beq a2, a1, .LBB2_2
103 ; RV32I-NEXT: # %bb.1:
104 ; RV32I-NEXT: slt a4, a1, a2
105 ; RV32I-NEXT: beqz a4, .LBB2_3
106 ; RV32I-NEXT: j .LBB2_4
107 ; RV32I-NEXT: .LBB2_2:
108 ; RV32I-NEXT: sltu a4, a0, a3
109 ; RV32I-NEXT: bnez a4, .LBB2_4
110 ; RV32I-NEXT: .LBB2_3:
111 ; RV32I-NEXT: mv a3, a0
112 ; RV32I-NEXT: mv a2, a1
113 ; RV32I-NEXT: .LBB2_4:
114 ; RV32I-NEXT: neg a0, a3
115 ; RV32I-NEXT: snez a1, a3
116 ; RV32I-NEXT: neg a2, a2
117 ; RV32I-NEXT: sub a1, a2, a1
118 ; RV32I-NEXT: ret
119 ;
120 ; RV32ZBB-LABEL: expanded_neg_abs64:
121 ; RV32ZBB: # %bb.0:
122 ; RV32ZBB-NEXT: snez a2, a0
123 ; RV32ZBB-NEXT: neg a3, a1
124 ; RV32ZBB-NEXT: sub a2, a3, a2
125 ; RV32ZBB-NEXT: neg a3, a0
126 ; RV32ZBB-NEXT: beq a2, a1, .LBB2_2
127 ; RV32ZBB-NEXT: # %bb.1:
128 ; RV32ZBB-NEXT: slt a4, a1, a2
129 ; RV32ZBB-NEXT: beqz a4, .LBB2_3
130 ; RV32ZBB-NEXT: j .LBB2_4
131 ; RV32ZBB-NEXT: .LBB2_2:
132 ; RV32ZBB-NEXT: sltu a4, a0, a3
133 ; RV32ZBB-NEXT: bnez a4, .LBB2_4
134 ; RV32ZBB-NEXT: .LBB2_3:
135 ; RV32ZBB-NEXT: mv a3, a0
136 ; RV32ZBB-NEXT: mv a2, a1
137 ; RV32ZBB-NEXT: .LBB2_4:
138 ; RV32ZBB-NEXT: neg a0, a3
139 ; RV32ZBB-NEXT: snez a1, a3
140 ; RV32ZBB-NEXT: neg a2, a2
141 ; RV32ZBB-NEXT: sub a1, a2, a1
142 ; RV32ZBB-NEXT: ret
143 ;
144 ; RV64I-LABEL: expanded_neg_abs64:
145 ; RV64I: # %bb.0:
146 ; RV64I-NEXT: neg a1, a0
147 ; RV64I-NEXT: blt a0, a1, .LBB2_2
148 ; RV64I-NEXT: # %bb.1:
149 ; RV64I-NEXT: mv a1, a0
150 ; RV64I-NEXT: .LBB2_2:
151 ; RV64I-NEXT: neg a0, a1
152 ; RV64I-NEXT: ret
153 ;
154 ; RV64ZBB-LABEL: expanded_neg_abs64:
155 ; RV64ZBB: # %bb.0:
156 ; RV64ZBB-NEXT: neg a1, a0
157 ; RV64ZBB-NEXT: min a0, a0, a1
158 ; RV64ZBB-NEXT: ret
159 %n = sub i64 0, %x
160 %t = call i64 @llvm.smax.i64(i64 %n, i64 %x)
161 %r = sub i64 0, %t
162 ret i64 %r
163 }
165 define i64 @expanded_neg_abs64_unsigned(i64 %x) {
166 ; RV32I-LABEL: expanded_neg_abs64_unsigned:
167 ; RV32I: # %bb.0:
168 ; RV32I-NEXT: snez a2, a0
169 ; RV32I-NEXT: neg a3, a1
170 ; RV32I-NEXT: sub a2, a3, a2
171 ; RV32I-NEXT: neg a3, a0
172 ; RV32I-NEXT: beq a2, a1, .LBB3_2
173 ; RV32I-NEXT: # %bb.1:
174 ; RV32I-NEXT: sltu a4, a1, a2
175 ; RV32I-NEXT: beqz a4, .LBB3_3
176 ; RV32I-NEXT: j .LBB3_4
177 ; RV32I-NEXT: .LBB3_2:
178 ; RV32I-NEXT: sltu a4, a0, a3
179 ; RV32I-NEXT: bnez a4, .LBB3_4
180 ; RV32I-NEXT: .LBB3_3:
181 ; RV32I-NEXT: mv a3, a0
182 ; RV32I-NEXT: mv a2, a1
183 ; RV32I-NEXT: .LBB3_4:
184 ; RV32I-NEXT: neg a0, a3
185 ; RV32I-NEXT: snez a1, a3
186 ; RV32I-NEXT: neg a2, a2
187 ; RV32I-NEXT: sub a1, a2, a1
188 ; RV32I-NEXT: ret
189 ;
190 ; RV32ZBB-LABEL: expanded_neg_abs64_unsigned:
191 ; RV32ZBB: # %bb.0:
192 ; RV32ZBB-NEXT: snez a2, a0
193 ; RV32ZBB-NEXT: neg a3, a1
194 ; RV32ZBB-NEXT: sub a2, a3, a2
195 ; RV32ZBB-NEXT: neg a3, a0
196 ; RV32ZBB-NEXT: beq a2, a1, .LBB3_2
197 ; RV32ZBB-NEXT: # %bb.1:
198 ; RV32ZBB-NEXT: sltu a4, a1, a2
199 ; RV32ZBB-NEXT: beqz a4, .LBB3_3
200 ; RV32ZBB-NEXT: j .LBB3_4
201 ; RV32ZBB-NEXT: .LBB3_2:
202 ; RV32ZBB-NEXT: sltu a4, a0, a3
203 ; RV32ZBB-NEXT: bnez a4, .LBB3_4
204 ; RV32ZBB-NEXT: .LBB3_3:
205 ; RV32ZBB-NEXT: mv a3, a0
206 ; RV32ZBB-NEXT: mv a2, a1
207 ; RV32ZBB-NEXT: .LBB3_4:
208 ; RV32ZBB-NEXT: neg a0, a3
209 ; RV32ZBB-NEXT: snez a1, a3
210 ; RV32ZBB-NEXT: neg a2, a2
211 ; RV32ZBB-NEXT: sub a1, a2, a1
212 ; RV32ZBB-NEXT: ret
213 ;
214 ; RV64I-LABEL: expanded_neg_abs64_unsigned:
215 ; RV64I: # %bb.0:
216 ; RV64I-NEXT: neg a1, a0
217 ; RV64I-NEXT: bltu a0, a1, .LBB3_2
218 ; RV64I-NEXT: # %bb.1:
219 ; RV64I-NEXT: mv a1, a0
220 ; RV64I-NEXT: .LBB3_2:
221 ; RV64I-NEXT: neg a0, a1
222 ; RV64I-NEXT: ret
223 ;
224 ; RV64ZBB-LABEL: expanded_neg_abs64_unsigned:
225 ; RV64ZBB: # %bb.0:
226 ; RV64ZBB-NEXT: neg a1, a0
227 ; RV64ZBB-NEXT: minu a0, a0, a1
228 ; RV64ZBB-NEXT: ret
229 %n = sub i64 0, %x
230 %t = call i64 @llvm.umax.i64(i64 %n, i64 %x)
231 %r = sub i64 0, %t
232 ret i64 %r
233 }
235 define i32 @expanded_neg_inv_abs32(i32 %x) {
236 ; RV32I-LABEL: expanded_neg_inv_abs32:
237 ; RV32I: # %bb.0:
238 ; RV32I-NEXT: neg a1, a0
239 ; RV32I-NEXT: blt a1, a0, .LBB4_2
240 ; RV32I-NEXT: # %bb.1:
241 ; RV32I-NEXT: mv a1, a0
242 ; RV32I-NEXT: .LBB4_2:
243 ; RV32I-NEXT: neg a0, a1
244 ; RV32I-NEXT: ret
245 ;
246 ; RV32ZBB-LABEL: expanded_neg_inv_abs32:
247 ; RV32ZBB: # %bb.0:
248 ; RV32ZBB-NEXT: neg a1, a0
249 ; RV32ZBB-NEXT: max a0, a0, a1
250 ; RV32ZBB-NEXT: ret
251 ;
252 ; RV64I-LABEL: expanded_neg_inv_abs32:
253 ; RV64I: # %bb.0:
254 ; RV64I-NEXT: neg a1, a0
255 ; RV64I-NEXT: sext.w a2, a1
256 ; RV64I-NEXT: sext.w a3, a0
257 ; RV64I-NEXT: blt a2, a3, .LBB4_2
258 ; RV64I-NEXT: # %bb.1:
259 ; RV64I-NEXT: mv a1, a0
260 ; RV64I-NEXT: .LBB4_2:
261 ; RV64I-NEXT: neg a0, a1
262 ; RV64I-NEXT: ret
263 ;
264 ; RV64ZBB-LABEL: expanded_neg_inv_abs32:
265 ; RV64ZBB: # %bb.0:
266 ; RV64ZBB-NEXT: negw a1, a0
267 ; RV64ZBB-NEXT: sext.w a0, a0
268 ; RV64ZBB-NEXT: min a0, a1, a0
269 ; RV64ZBB-NEXT: neg a0, a0
270 ; RV64ZBB-NEXT: ret
271 %n = sub i32 0, %x
272 %t = call i32 @llvm.smin.i32(i32 %n, i32 %x)
273 %r = sub i32 0, %t
274 ret i32 %r
275 }
277 define i32 @expanded_neg_inv_abs32_unsigned(i32 %x) {
278 ; RV32I-LABEL: expanded_neg_inv_abs32_unsigned:
279 ; RV32I: # %bb.0:
280 ; RV32I-NEXT: neg a1, a0
281 ; RV32I-NEXT: bltu a1, a0, .LBB5_2
282 ; RV32I-NEXT: # %bb.1:
283 ; RV32I-NEXT: mv a1, a0
284 ; RV32I-NEXT: .LBB5_2:
285 ; RV32I-NEXT: neg a0, a1
286 ; RV32I-NEXT: ret
287 ;
288 ; RV32ZBB-LABEL: expanded_neg_inv_abs32_unsigned:
289 ; RV32ZBB: # %bb.0:
290 ; RV32ZBB-NEXT: neg a1, a0
291 ; RV32ZBB-NEXT: maxu a0, a0, a1
292 ; RV32ZBB-NEXT: ret
293 ;
294 ; RV64I-LABEL: expanded_neg_inv_abs32_unsigned:
295 ; RV64I: # %bb.0:
296 ; RV64I-NEXT: neg a1, a0
297 ; RV64I-NEXT: sext.w a2, a1
298 ; RV64I-NEXT: sext.w a3, a0
299 ; RV64I-NEXT: bltu a2, a3, .LBB5_2
300 ; RV64I-NEXT: # %bb.1:
301 ; RV64I-NEXT: mv a1, a0
302 ; RV64I-NEXT: .LBB5_2:
303 ; RV64I-NEXT: neg a0, a1
304 ; RV64I-NEXT: ret
305 ;
306 ; RV64ZBB-LABEL: expanded_neg_inv_abs32_unsigned:
307 ; RV64ZBB: # %bb.0:
308 ; RV64ZBB-NEXT: negw a1, a0
309 ; RV64ZBB-NEXT: sext.w a0, a0
310 ; RV64ZBB-NEXT: minu a0, a1, a0
311 ; RV64ZBB-NEXT: neg a0, a0
312 ; RV64ZBB-NEXT: ret
313 %n = sub i32 0, %x
314 %t = call i32 @llvm.umin.i32(i32 %n, i32 %x)
315 %r = sub i32 0, %t
316 ret i32 %r
317 }
319 define i64 @expanded_neg_inv_abs64(i64 %x) {
320 ; RV32I-LABEL: expanded_neg_inv_abs64:
321 ; RV32I: # %bb.0:
322 ; RV32I-NEXT: snez a2, a0
323 ; RV32I-NEXT: neg a3, a1
324 ; RV32I-NEXT: sub a2, a3, a2
325 ; RV32I-NEXT: neg a3, a0
326 ; RV32I-NEXT: beq a2, a1, .LBB6_2
327 ; RV32I-NEXT: # %bb.1:
328 ; RV32I-NEXT: slt a4, a2, a1
329 ; RV32I-NEXT: beqz a4, .LBB6_3
330 ; RV32I-NEXT: j .LBB6_4
331 ; RV32I-NEXT: .LBB6_2:
332 ; RV32I-NEXT: sltu a4, a3, a0
333 ; RV32I-NEXT: bnez a4, .LBB6_4
334 ; RV32I-NEXT: .LBB6_3:
335 ; RV32I-NEXT: mv a3, a0
336 ; RV32I-NEXT: mv a2, a1
337 ; RV32I-NEXT: .LBB6_4:
338 ; RV32I-NEXT: neg a0, a3
339 ; RV32I-NEXT: snez a1, a3
340 ; RV32I-NEXT: neg a2, a2
341 ; RV32I-NEXT: sub a1, a2, a1
342 ; RV32I-NEXT: ret
343 ;
344 ; RV32ZBB-LABEL: expanded_neg_inv_abs64:
345 ; RV32ZBB: # %bb.0:
346 ; RV32ZBB-NEXT: snez a2, a0
347 ; RV32ZBB-NEXT: neg a3, a1
348 ; RV32ZBB-NEXT: sub a2, a3, a2
349 ; RV32ZBB-NEXT: neg a3, a0
350 ; RV32ZBB-NEXT: beq a2, a1, .LBB6_2
351 ; RV32ZBB-NEXT: # %bb.1:
352 ; RV32ZBB-NEXT: slt a4, a2, a1
353 ; RV32ZBB-NEXT: beqz a4, .LBB6_3
354 ; RV32ZBB-NEXT: j .LBB6_4
355 ; RV32ZBB-NEXT: .LBB6_2:
356 ; RV32ZBB-NEXT: sltu a4, a3, a0
357 ; RV32ZBB-NEXT: bnez a4, .LBB6_4
358 ; RV32ZBB-NEXT: .LBB6_3:
359 ; RV32ZBB-NEXT: mv a3, a0
360 ; RV32ZBB-NEXT: mv a2, a1
361 ; RV32ZBB-NEXT: .LBB6_4:
362 ; RV32ZBB-NEXT: neg a0, a3
363 ; RV32ZBB-NEXT: snez a1, a3
364 ; RV32ZBB-NEXT: neg a2, a2
365 ; RV32ZBB-NEXT: sub a1, a2, a1
366 ; RV32ZBB-NEXT: ret
367 ;
368 ; RV64I-LABEL: expanded_neg_inv_abs64:
369 ; RV64I: # %bb.0:
370 ; RV64I-NEXT: neg a1, a0
371 ; RV64I-NEXT: blt a1, a0, .LBB6_2
372 ; RV64I-NEXT: # %bb.1:
373 ; RV64I-NEXT: mv a1, a0
374 ; RV64I-NEXT: .LBB6_2:
375 ; RV64I-NEXT: neg a0, a1
376 ; RV64I-NEXT: ret
377 ;
378 ; RV64ZBB-LABEL: expanded_neg_inv_abs64:
379 ; RV64ZBB: # %bb.0:
380 ; RV64ZBB-NEXT: neg a1, a0
381 ; RV64ZBB-NEXT: max a0, a0, a1
382 ; RV64ZBB-NEXT: ret
383 %n = sub i64 0, %x
384 %t = call i64 @llvm.smin.i64(i64 %n, i64 %x)
385 %r = sub i64 0, %t
386 ret i64 %r
387 }
389 define i64 @expanded_neg_inv_abs64_unsigned(i64 %x) {
390 ; RV32I-LABEL: expanded_neg_inv_abs64_unsigned:
391 ; RV32I: # %bb.0:
392 ; RV32I-NEXT: snez a2, a0
393 ; RV32I-NEXT: neg a3, a1
394 ; RV32I-NEXT: sub a2, a3, a2
395 ; RV32I-NEXT: neg a3, a0
396 ; RV32I-NEXT: beq a2, a1, .LBB7_2
397 ; RV32I-NEXT: # %bb.1:
398 ; RV32I-NEXT: sltu a4, a2, a1
399 ; RV32I-NEXT: beqz a4, .LBB7_3
400 ; RV32I-NEXT: j .LBB7_4
401 ; RV32I-NEXT: .LBB7_2:
402 ; RV32I-NEXT: sltu a4, a3, a0
403 ; RV32I-NEXT: bnez a4, .LBB7_4
404 ; RV32I-NEXT: .LBB7_3:
405 ; RV32I-NEXT: mv a3, a0
406 ; RV32I-NEXT: mv a2, a1
407 ; RV32I-NEXT: .LBB7_4:
408 ; RV32I-NEXT: neg a0, a3
409 ; RV32I-NEXT: snez a1, a3
410 ; RV32I-NEXT: neg a2, a2
411 ; RV32I-NEXT: sub a1, a2, a1
412 ; RV32I-NEXT: ret
413 ;
414 ; RV32ZBB-LABEL: expanded_neg_inv_abs64_unsigned:
415 ; RV32ZBB: # %bb.0:
416 ; RV32ZBB-NEXT: snez a2, a0
417 ; RV32ZBB-NEXT: neg a3, a1
418 ; RV32ZBB-NEXT: sub a2, a3, a2
419 ; RV32ZBB-NEXT: neg a3, a0
420 ; RV32ZBB-NEXT: beq a2, a1, .LBB7_2
421 ; RV32ZBB-NEXT: # %bb.1:
422 ; RV32ZBB-NEXT: sltu a4, a2, a1
423 ; RV32ZBB-NEXT: beqz a4, .LBB7_3
424 ; RV32ZBB-NEXT: j .LBB7_4
425 ; RV32ZBB-NEXT: .LBB7_2:
426 ; RV32ZBB-NEXT: sltu a4, a3, a0
427 ; RV32ZBB-NEXT: bnez a4, .LBB7_4
428 ; RV32ZBB-NEXT: .LBB7_3:
429 ; RV32ZBB-NEXT: mv a3, a0
430 ; RV32ZBB-NEXT: mv a2, a1
431 ; RV32ZBB-NEXT: .LBB7_4:
432 ; RV32ZBB-NEXT: neg a0, a3
433 ; RV32ZBB-NEXT: snez a1, a3
434 ; RV32ZBB-NEXT: neg a2, a2
435 ; RV32ZBB-NEXT: sub a1, a2, a1
436 ; RV32ZBB-NEXT: ret
437 ;
438 ; RV64I-LABEL: expanded_neg_inv_abs64_unsigned:
439 ; RV64I: # %bb.0:
440 ; RV64I-NEXT: neg a1, a0
441 ; RV64I-NEXT: bltu a1, a0, .LBB7_2
442 ; RV64I-NEXT: # %bb.1:
443 ; RV64I-NEXT: mv a1, a0
444 ; RV64I-NEXT: .LBB7_2:
445 ; RV64I-NEXT: neg a0, a1
446 ; RV64I-NEXT: ret
447 ;
448 ; RV64ZBB-LABEL: expanded_neg_inv_abs64_unsigned:
449 ; RV64ZBB: # %bb.0:
450 ; RV64ZBB-NEXT: neg a1, a0
451 ; RV64ZBB-NEXT: maxu a0, a0, a1
452 ; RV64ZBB-NEXT: ret
453 %n = sub i64 0, %x
454 %t = call i64 @llvm.umin.i64(i64 %n, i64 %x)
455 %r = sub i64 0, %t
456 ret i64 %r
457 }