| blob | e64e7866103ffff0d9f45407d9320e907d77682c |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
3 # RUN: | FileCheck %s --check-prefixes=CHECK,RV32I
4 # RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o -\
5 # RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB
7 ---
8 name: abs_i8
9 body: |
10 bb.0.entry:
11 ; RV32I-LABEL: name: abs_i8
12 ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
13 ; RV32I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
14 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
15 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
16 ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C1]](s32)
17 ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
18 ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[ASHR]], [[C]](s32)
19 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASSERT_ZEXT]], [[ASHR1]]
20 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR1]]
21 ; RV32I-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
22 ; RV32I-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[XOR]], [[C2]]
23 ; RV32I-NEXT: $x10 = COPY [[AND]](s32)
24 ; RV32I-NEXT: PseudoRET implicit $x10
25 ;
26 ; RV32ZBB-LABEL: name: abs_i8
27 ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
28 ; RV32ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 8
29 ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ASSERT_ZEXT]], 8
30 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
31 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[SEXT_INREG]]
32 ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SUB]]
33 ; RV32ZBB-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
34 ; RV32ZBB-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[SMAX]], [[C1]]
35 ; RV32ZBB-NEXT: $x10 = COPY [[AND]](s32)
36 ; RV32ZBB-NEXT: PseudoRET implicit $x10
37 %1:_(s32) = COPY $x10
38 %2:_(s32) = G_ASSERT_ZEXT %1, 8
39 %0:_(s8) = G_TRUNC %2(s32)
40 %3:_(s8) = G_ABS %0
41 %4:_(s32) = G_ZEXT %3(s8)
42 $x10 = COPY %4(s32)
43 PseudoRET implicit $x10
44 ...
45 ---
46 name: abs_i16
47 body: |
48 bb.0.entry:
49 ; RV32I-LABEL: name: abs_i16
50 ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
51 ; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
52 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
53 ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[ASSERT_SEXT]], [[C]](s32)
54 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ASSERT_SEXT]], [[ASHR]]
55 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
56 ; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
57 ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[XOR]], [[C1]](s32)
58 ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]](s32)
59 ; RV32I-NEXT: $x10 = COPY [[ASHR1]](s32)
60 ; RV32I-NEXT: PseudoRET implicit $x10
61 ;
62 ; RV32ZBB-LABEL: name: abs_i16
63 ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
64 ; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
65 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
66 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[ASSERT_SEXT]]
67 ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[ASSERT_SEXT]], [[SUB]]
68 ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SMAX]], 16
69 ; RV32ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s32)
70 ; RV32ZBB-NEXT: PseudoRET implicit $x10
71 %1:_(s32) = COPY $x10
72 %2:_(s32) = G_ASSERT_SEXT %1, 16
73 %0:_(s16) = G_TRUNC %2(s32)
74 %3:_(s16) = G_ABS %0
75 %4:_(s32) = G_SEXT %3(s16)
76 $x10 = COPY %4(s32)
77 PseudoRET implicit $x10
78 ...
79 ---
80 name: abs_i32
81 body: |
82 bb.0.entry:
83 ; RV32I-LABEL: name: abs_i32
84 ; RV32I: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
85 ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
86 ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
87 ; RV32I-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]
88 ; RV32I-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
89 ; RV32I-NEXT: $x10 = COPY [[XOR]](s32)
90 ; RV32I-NEXT: PseudoRET implicit $x10
91 ;
92 ; RV32ZBB-LABEL: name: abs_i32
93 ; RV32ZBB: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
94 ; RV32ZBB-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
95 ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C]], [[COPY]]
96 ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[COPY]], [[SUB]]
97 ; RV32ZBB-NEXT: $x10 = COPY [[SMAX]](s32)
98 ; RV32ZBB-NEXT: PseudoRET implicit $x10
99 %0:_(s32) = COPY $x10
100 %1:_(s32) = G_ABS %0
101 $x10 = COPY %1(s32)
102 PseudoRET implicit $x10
103 ...
104 ---
105 name: abs_i64
106 body: |
107 bb.0.entry:
108 ; CHECK-LABEL: name: abs_i64
109 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
110 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
111 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
112 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY1]], [[C]](s32)
113 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]
114 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[ADD]](s32), [[ASHR]]
115 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
116 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY1]], [[ASHR]]
117 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ADD1]], [[ICMP]]
118 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ADD2]](s32)
119 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[ASHR]]
120 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[COPY3]], [[ASHR]]
121 ; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
122 ; CHECK-NEXT: $x11 = COPY [[XOR1]](s32)
123 ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
124 %1:_(s32) = COPY $x10
125 %2:_(s32) = COPY $x11
126 %0:_(s64) = G_MERGE_VALUES %1(s32), %2(s32)
127 %3:_(s64) = G_ABS %0
128 %4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3(s64)
129 $x10 = COPY %4(s32)
130 $x11 = COPY %5(s32)
131 PseudoRET implicit $x10, implicit $x11
132 ...