| blob | 78a2227b84a3af447cbf43e670d6cc76ab34c211 |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
3 # RUN: | FileCheck %s --check-prefix=RV64I
4 # RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o - \
5 # RUN: | FileCheck %s --check-prefix=RV64ZBB
7 ---
8 name: abs_i8
9 body: |
10 bb.0.entry:
11 ; RV64I-LABEL: name: abs_i8
12 ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
13 ; RV64I-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8
14 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
15 ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
16 ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[ASSERT_ZEXT]], [[C1]](s64)
17 ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64)
18 ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[ASHR]], [[C]](s64)
19 ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_ZEXT]], [[ASHR1]]
20 ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR1]]
21 ; RV64I-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
22 ; RV64I-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[XOR]], [[C2]]
23 ; RV64I-NEXT: $x10 = COPY [[AND]](s64)
24 ; RV64I-NEXT: PseudoRET implicit $x10
25 ;
26 ; RV64ZBB-LABEL: name: abs_i8
27 ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
28 ; RV64ZBB-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s64) = G_ASSERT_ZEXT [[COPY]], 8
29 ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ASSERT_ZEXT]], 8
30 ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
31 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[SEXT_INREG]]
32 ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[SEXT_INREG]], [[SUB]]
33 ; RV64ZBB-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
34 ; RV64ZBB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[SMAX]], [[C1]]
35 ; RV64ZBB-NEXT: $x10 = COPY [[AND]](s64)
36 ; RV64ZBB-NEXT: PseudoRET implicit $x10
37 %1:_(s64) = COPY $x10
38 %2:_(s64) = G_ASSERT_ZEXT %1, 8
39 %0:_(s8) = G_TRUNC %2(s64)
40 %3:_(s8) = G_ABS %0
41 %4:_(s64) = G_ZEXT %3(s8)
42 $x10 = COPY %4(s64)
43 PseudoRET implicit $x10
44 ...
45 ---
46 name: abs_i16
47 body: |
48 bb.0.entry:
49 ; RV64I-LABEL: name: abs_i16
50 ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
51 ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16
52 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15
53 ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[C]](s64)
54 ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]]
55 ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]]
56 ; RV64I-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
57 ; RV64I-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[XOR]], [[C1]](s64)
58 ; RV64I-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C1]](s64)
59 ; RV64I-NEXT: $x10 = COPY [[ASHR1]](s64)
60 ; RV64I-NEXT: PseudoRET implicit $x10
61 ;
62 ; RV64ZBB-LABEL: name: abs_i16
63 ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
64 ; RV64ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 16
65 ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
66 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[ASSERT_SEXT]]
67 ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASSERT_SEXT]], [[SUB]]
68 ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 16
69 ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
70 ; RV64ZBB-NEXT: PseudoRET implicit $x10
71 %1:_(s64) = COPY $x10
72 %2:_(s64) = G_ASSERT_SEXT %1, 16
73 %0:_(s16) = G_TRUNC %2(s64)
74 %3:_(s16) = G_ABS %0
75 %4:_(s64) = G_SEXT %3(s16)
76 $x10 = COPY %4(s64)
77 PseudoRET implicit $x10
78 ...
79 ---
80 name: abs_i32
81 body: |
82 bb.0.entry:
83 ; RV64I-LABEL: name: abs_i32
84 ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
85 ; RV64I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
86 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
87 ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[C]](s64)
88 ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]]
89 ; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
90 ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SEXT_INREG]], [[ASHR]]
91 ; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32
92 ; RV64I-NEXT: $x10 = COPY [[SEXT_INREG1]](s64)
93 ; RV64I-NEXT: PseudoRET implicit $x10
94 ;
95 ; RV64ZBB-LABEL: name: abs_i32
96 ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
97 ; RV64ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s64) = G_ASSERT_SEXT [[COPY]], 32
98 ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
99 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[ASSERT_SEXT]]
100 ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[ASSERT_SEXT]], [[SUB]]
101 ; RV64ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[SMAX]], 32
102 ; RV64ZBB-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
103 ; RV64ZBB-NEXT: PseudoRET implicit $x10
104 %1:_(s64) = COPY $x10
105 %2:_(s64) = G_ASSERT_SEXT %1, 32
106 %0:_(s32) = G_TRUNC %2(s64)
107 %3:_(s32) = G_ABS %0
108 %4:_(s64) = G_SEXT %3(s32)
109 $x10 = COPY %4(s64)
110 PseudoRET implicit $x10
111 ...
112 ---
113 name: abs_i64
114 body: |
115 bb.0.entry:
116 ; RV64I-LABEL: name: abs_i64
117 ; RV64I: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
118 ; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
119 ; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
120 ; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ASHR]]
121 ; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]]
122 ; RV64I-NEXT: $x10 = COPY [[XOR]](s64)
123 ; RV64I-NEXT: PseudoRET implicit $x10
124 ;
125 ; RV64ZBB-LABEL: name: abs_i64
126 ; RV64ZBB: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
127 ; RV64ZBB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
128 ; RV64ZBB-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[C]], [[COPY]]
129 ; RV64ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s64) = G_SMAX [[COPY]], [[SUB]]
130 ; RV64ZBB-NEXT: $x10 = COPY [[SMAX]](s64)
131 ; RV64ZBB-NEXT: PseudoRET implicit $x10
132 %0:_(s64) = COPY $x10
133 %1:_(s64) = G_ABS %0
134 $x10 = COPY %1(s64)
135 PseudoRET implicit $x10
136 ...