| blob | 70fbda47a14a14fb9febc97ec75177c606047fa0 |
1 ; RUN: llc -mtriple=riscv32 -mattr=help 2>&1 | FileCheck %s
2 ; RUN: llc -mtriple=riscv64 -mattr=help 2>&1 | FileCheck %s
4 ; CHECK: Available features for this target:
5 ; CHECK: 32bit - Implements RV32.
6 ; CHECK: 64bit - Implements RV64.
7 ; CHECK: a - 'A' (Atomic Instructions).
8 ; CHECK: auipc-addi-fusion - Enable AUIPC+ADDI macrofusion.
9 ; CHECK: b - 'B' (the collection of the Zba, Zbb, Zbs extensions).
10 ; CHECK: c - 'C' (Compressed Instructions).
11 ; CHECK: conditional-cmv-fusion - Enable branch+c.mv fusion.
12 ; CHECK: d - 'D' (Double-Precision Floating-Point).
13 ; CHECK: disable-latency-sched-heuristic - Disable latency scheduling heuristic.
14 ; CHECK: dlen-factor-2 - Vector unit DLEN(data path width) is half of VLEN.
15 ; CHECK: e - 'E' (Embedded Instruction Set with 16 GPRs).
16 ; CHECK: experimental - Experimental intrinsics.
17 ; CHECK: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
18 ; CHECK: experimental-sdext - 'Sdext' (External debugger).
19 ; CHECK: experimental-sdtrig - 'Sdtrig' (Debugger triggers).
20 ; CHECK: experimental-smctr - 'Smctr' (Control Transfer Records Machine Level).
21 ; CHECK: experimental-ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).
22 ; CHECK: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
23 ; CHECK: experimental-xqcia - 'Xqcia' (Qualcomm uC Arithmetic Extension).
24 ; CHECK: experimental-xqcics - 'Xqcics' (Qualcomm uC Conditional Select Extension).
25 ; CHECK: experimental-xqcicsr - 'Xqcicsr' (Qualcomm uC CSR Extension).
26 ; CHECK: experimental-xqcilsm - 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension).
27 ; CHECK: experimental-xqcisls - 'Xqcisls' (Qualcomm uC Scaled Load Store Extension).
28 ; CHECK: experimental-zalasr - 'Zalasr' (Load-Acquire and Store-Release Instructions).
29 ; CHECK: experimental-zicfilp - 'Zicfilp' (Landing pad).
30 ; CHECK: experimental-zicfiss - 'Zicfiss' (Shadow stack).
31 ; CHECK: experimental-zvbc32e - 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements).
32 ; CHECK: experimental-zvkgs - 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography).
33 ; CHECK: f - 'F' (Single-Precision Floating-Point).
34 ; CHECK: forced-atomics - Assume that lock-free native-width atomics are available.
35 ; CHECK: h - 'H' (Hypervisor).
36 ; CHECK: i - 'I' (Base Integer Instruction Set).
37 ; CHECK: ld-add-fusion - Enable LD+ADD macrofusion.
38 ; CHECK: lui-addi-fusion - Enable LUI+ADDI macro fusion.
39 ; CHECK: m - 'M' (Integer Multiplication and Division).
40 ; CHECK: mips-p8700 - MIPS p8700 processor.
41 ; CHECK: no-default-unroll - Disable default unroll preference..
42 ; CHECK: no-rvc-hints - Disable RVC Hint Instructions..
43 ; CHECK: no-sink-splat-operands - Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions.
44 ; CHECK: no-trailing-seq-cst-fence - Disable trailing fence for seq-cst store..
45 ; CHECK: optimized-nf2-segment-load-store - vlseg2eN.v and vsseg2eN.v areimplemented as a wide memory op and shuffle.
46 ; CHECK: optimized-nf3-segment-load-store - vlseg3eN.v and vsseg3eN.v areimplemented as a wide memory op and shuffle.
47 ; CHECK: optimized-nf4-segment-load-store - vlseg4eN.v and vsseg4eN.v areimplemented as a wide memory op and shuffle.
48 ; CHECK: optimized-nf5-segment-load-store - vlseg5eN.v and vsseg5eN.v areimplemented as a wide memory op and shuffle.
49 ; CHECK: optimized-nf6-segment-load-store - vlseg6eN.v and vsseg6eN.v areimplemented as a wide memory op and shuffle.
50 ; CHECK: optimized-nf7-segment-load-store - vlseg7eN.v and vsseg7eN.v areimplemented as a wide memory op and shuffle.
51 ; CHECK: optimized-nf8-segment-load-store - vlseg8eN.v and vsseg8eN.v areimplemented as a wide memory op and shuffle.
52 ; CHECK: optimized-zero-stride-load - Optimized (perform fewer memory operations)zero-stride vector load.
53 ; CHECK: predictable-select-expensive - Prefer likely predicted branches over selects.
54 ; CHECK: prefer-w-inst - Prefer instructions with W suffix.
55 ; CHECK: relax - Enable Linker relaxation..
56 ; CHECK: reserve-x1 - Reserve X1.
57 ; CHECK: reserve-x10 - Reserve X10.
58 ; CHECK: reserve-x11 - Reserve X11.
59 ; CHECK: reserve-x12 - Reserve X12.
60 ; CHECK: reserve-x13 - Reserve X13.
61 ; CHECK: reserve-x14 - Reserve X14.
62 ; CHECK: reserve-x15 - Reserve X15.
63 ; CHECK: reserve-x16 - Reserve X16.
64 ; CHECK: reserve-x17 - Reserve X17.
65 ; CHECK: reserve-x18 - Reserve X18.
66 ; CHECK: reserve-x19 - Reserve X19.
67 ; CHECK: reserve-x2 - Reserve X2.
68 ; CHECK: reserve-x20 - Reserve X20.
69 ; CHECK: reserve-x21 - Reserve X21.
70 ; CHECK: reserve-x22 - Reserve X22.
71 ; CHECK: reserve-x23 - Reserve X23.
72 ; CHECK: reserve-x24 - Reserve X24.
73 ; CHECK: reserve-x25 - Reserve X25.
74 ; CHECK: reserve-x26 - Reserve X26.
75 ; CHECK: reserve-x27 - Reserve X27.
76 ; CHECK: reserve-x28 - Reserve X28.
77 ; CHECK: reserve-x29 - Reserve X29.
78 ; CHECK: reserve-x3 - Reserve X3.
79 ; CHECK: reserve-x30 - Reserve X30.
80 ; CHECK: reserve-x31 - Reserve X31.
81 ; CHECK: reserve-x4 - Reserve X4.
82 ; CHECK: reserve-x5 - Reserve X5.
83 ; CHECK: reserve-x6 - Reserve X6.
84 ; CHECK: reserve-x7 - Reserve X7.
85 ; CHECK: reserve-x8 - Reserve X8.
86 ; CHECK: reserve-x9 - Reserve X9.
87 ; CHECK: rva20s64 - RISC-V rva20s64 profile.
88 ; CHECK: rva20u64 - RISC-V rva20u64 profile.
89 ; CHECK: rva22s64 - RISC-V rva22s64 profile.
90 ; CHECK: rva22u64 - RISC-V rva22u64 profile.
91 ; CHECK: rva23s64 - RISC-V rva23s64 profile.
92 ; CHECK: rva23u64 - RISC-V rva23u64 profile.
93 ; CHECK: rvb23s64 - RISC-V rvb23s64 profile.
94 ; CHECK: rvb23u64 - RISC-V rvb23u64 profile.
95 ; CHECK: rvi20u32 - RISC-V rvi20u32 profile.
96 ; CHECK: rvi20u64 - RISC-V rvi20u64 profile.
97 ; CHECK: save-restore - Enable save/restore..
98 ; CHECK: sha - 'Sha' (Augmented Hypervisor).
99 ; CHECK: shcounterenw - 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero).
100 ; CHECK: shgatpa - 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare).
101 ; CHECK: shifted-zextw-fusion - Enable SLLI+SRLI to be fused when computing (shifted) word zero extension.
102 ; CHECK: short-forward-branch-opt - Enable short forward branch optimization.
103 ; CHECK: shtvala - 'Shtvala' (htval provides all needed values).
104 ; CHECK: shvsatpa - 'Shvsatpa' (vsatp supports all modes supported by satp).
105 ; CHECK: shvstvala - 'Shvstvala' (vstval provides all needed values).
106 ; CHECK: shvstvecd - 'Shvstvecd' (vstvec supports Direct mode).
107 ; CHECK: sifive7 - SiFive 7-Series processors.
108 ; CHECK: smaia - 'Smaia' (Advanced Interrupt Architecture Machine Level).
109 ; CHECK: smcdeleg - 'Smcdeleg' (Counter Delegation Machine Level).
110 ; CHECK: smcsrind - 'Smcsrind' (Indirect CSR Access Machine Level).
111 ; CHECK: smdbltrp - 'Smdbltrp' (Double Trap Machine Level).
112 ; CHECK: smepmp - 'Smepmp' (Enhanced Physical Memory Protection).
113 ; CHECK: smmpm - 'Smmpm' (Machine-level Pointer Masking for M-mode).
114 ; CHECK: smnpm - 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode).
115 ; CHECK: smrnmi - 'Smrnmi' (Resumable Non-Maskable Interrupts).
116 ; CHECK: smstateen - 'Smstateen' (Machine-mode view of the state-enable extension).
117 ; CHECK: ssaia - 'Ssaia' (Advanced Interrupt Architecture Supervisor Level).
118 ; CHECK: ssccfg - 'Ssccfg' (Counter Configuration Supervisor Level).
119 ; CHECK: ssccptr - 'Ssccptr' (Main memory supports page table reads).
120 ; CHECK: sscofpmf - 'Sscofpmf' (Count Overflow and Mode-Based Filtering).
121 ; CHECK: sscounterenw - 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero).
122 ; CHECK: sscsrind - 'Sscsrind' (Indirect CSR Access Supervisor Level).
123 ; CHECK: ssdbltrp - 'Ssdbltrp' (Double Trap Supervisor Level).
124 ; CHECK: ssnpm - 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode).
125 ; CHECK: sspm - 'Sspm' (Indicates Supervisor-mode Pointer Masking).
126 ; CHECK: ssqosid - 'Ssqosid' (Quality-of-Service (QoS) Identifiers).
127 ; CHECK: ssstateen - 'Ssstateen' (Supervisor-mode view of the state-enable extension).
128 ; CHECK: ssstrict - 'Ssstrict' (No non-conforming extensions are present).
129 ; CHECK: sstc - 'Sstc' (Supervisor-mode timer interrupts).
130 ; CHECK: sstvala - 'Sstvala' (stval provides all needed values).
131 ; CHECK: sstvecd - 'Sstvecd' (stvec supports Direct mode).
132 ; CHECK: ssu64xl - 'Ssu64xl' (UXLEN=64 supported).
133 ; CHECK: supm - 'Supm' (Indicates User-mode Pointer Masking).
134 ; CHECK: svade - 'Svade' (Raise exceptions on improper A/D bits).
135 ; CHECK: svadu - 'Svadu' (Hardware A/D updates).
136 ; CHECK: svbare - 'Svbare' (satp mode Bare supported).
137 ; CHECK: svinval - 'Svinval' (Fine-Grained Address-Translation Cache Invalidation).
138 ; CHECK: svnapot - 'Svnapot' (NAPOT Translation Contiguity).
139 ; CHECK: svpbmt - 'Svpbmt' (Page-Based Memory Types).
140 ; CHECK: svvptc - 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid).
141 ; CHECK: tagged-globals - Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits.
142 ; CHECK: unaligned-scalar-mem - Has reasonably performant unaligned scalar loads and stores.
143 ; CHECK: unaligned-vector-mem - Has reasonably performant unaligned vector loads and stores.
144 ; CHECK: use-postra-scheduler - Schedule again after register allocation.
145 ; CHECK: v - 'V' (Vector Extension for Application Processors).
146 ; CHECK: ventana-veyron - Ventana Veyron-Series processors.
147 ; CHECK: vxrm-pipeline-flush - VXRM writes causes pipeline flush.
148 ; CHECK: xcvalu - 'XCValu' (CORE-V ALU Operations).
149 ; CHECK: xcvbi - 'XCVbi' (CORE-V Immediate Branching).
150 ; CHECK: xcvbitmanip - 'XCVbitmanip' (CORE-V Bit Manipulation).
151 ; CHECK: xcvelw - 'XCVelw' (CORE-V Event Load Word).
152 ; CHECK: xcvmac - 'XCVmac' (CORE-V Multiply-Accumulate).
153 ; CHECK: xcvmem - 'XCVmem' (CORE-V Post-incrementing Load & Store).
154 ; CHECK: xcvsimd - 'XCVsimd' (CORE-V SIMD ALU).
155 ; CHECK: xsfcease - 'XSfcease' (SiFive sf.cease Instruction).
156 ; CHECK: xsfvcp - 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions).
157 ; CHECK: xsfvfnrclipxfqf - 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions).
158 ; CHECK: xsfvfwmaccqqq - 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4)).
159 ; CHECK: xsfvqmaccdod - 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)).
160 ; CHECK: xsfvqmaccqoq - 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)).
161 ; CHECK: xsifivecdiscarddlone - 'XSiFivecdiscarddlone' (SiFive sf.cdiscard.d.l1 Instruction).
162 ; CHECK: xsifivecflushdlone - 'XSiFivecflushdlone' (SiFive sf.cflush.d.l1 Instruction).
163 ; CHECK: xtheadba - 'XTHeadBa' (T-Head address calculation instructions).
164 ; CHECK: xtheadbb - 'XTHeadBb' (T-Head basic bit-manipulation instructions).
165 ; CHECK: xtheadbs - 'XTHeadBs' (T-Head single-bit instructions).
166 ; CHECK: xtheadcmo - 'XTHeadCmo' (T-Head cache management instructions).
167 ; CHECK: xtheadcondmov - 'XTHeadCondMov' (T-Head conditional move instructions).
168 ; CHECK: xtheadfmemidx - 'XTHeadFMemIdx' (T-Head FP Indexed Memory Operations).
169 ; CHECK: xtheadmac - 'XTHeadMac' (T-Head Multiply-Accumulate Instructions).
170 ; CHECK: xtheadmemidx - 'XTHeadMemIdx' (T-Head Indexed Memory Operations).
171 ; CHECK: xtheadmempair - 'XTHeadMemPair' (T-Head two-GPR Memory Operations).
172 ; CHECK: xtheadsync - 'XTHeadSync' (T-Head multicore synchronization instructions).
173 ; CHECK: xtheadvdot - 'XTHeadVdot' (T-Head Vector Extensions for Dot).
174 ; CHECK: xventanacondops - 'XVentanaCondOps' (Ventana Conditional Ops).
175 ; CHECK: xwchc - 'Xwchc' (WCH/QingKe additional compressed opcodes).
176 ; CHECK: za128rs - 'Za128rs' (Reservation Set Size of at Most 128 Bytes).
177 ; CHECK: za64rs - 'Za64rs' (Reservation Set Size of at Most 64 Bytes).
178 ; CHECK: zaamo - 'Zaamo' (Atomic Memory Operations).
179 ; CHECK: zabha - 'Zabha' (Byte and Halfword Atomic Memory Operations).
180 ; CHECK: zacas - 'Zacas' (Atomic Compare-And-Swap Instructions).
181 ; CHECK: zalrsc - 'Zalrsc' (Load-Reserved/Store-Conditional).
182 ; CHECK: zama16b - 'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs).
183 ; CHECK: zawrs - 'Zawrs' (Wait on Reservation Set).
184 ; CHECK: zba - 'Zba' (Address Generation Instructions).
185 ; CHECK: zbb - 'Zbb' (Basic Bit-Manipulation).
186 ; CHECK: zbc - 'Zbc' (Carry-Less Multiplication).
187 ; CHECK: zbkb - 'Zbkb' (Bitmanip instructions for Cryptography).
188 ; CHECK: zbkc - 'Zbkc' (Carry-less multiply instructions for Cryptography).
189 ; CHECK: zbkx - 'Zbkx' (Crossbar permutation instructions).
190 ; CHECK: zbs - 'Zbs' (Single-Bit Instructions).
191 ; CHECK: zca - 'Zca' (part of the C extension, excluding compressed floating point loads/stores).
192 ; CHECK: zcb - 'Zcb' (Compressed basic bit manipulation instructions).
193 ; CHECK: zcd - 'Zcd' (Compressed Double-Precision Floating-Point Instructions).
194 ; CHECK: zce - 'Zce' (Compressed extensions for microcontrollers).
195 ; CHECK: zcf - 'Zcf' (Compressed Single-Precision Floating-Point Instructions).
196 ; CHECK: zcmop - 'Zcmop' (Compressed May-Be-Operations).
197 ; CHECK: zcmp - 'Zcmp' (sequenced instructions for code-size reduction).
198 ; CHECK: zcmt - 'Zcmt' (table jump instructions for code-size reduction).
199 ; CHECK: zdinx - 'Zdinx' (Double in Integer).
200 ; CHECK: zexth-fusion - Enable SLLI+SRLI to be fused to zero extension of halfword.
201 ; CHECK: zextw-fusion - Enable SLLI+SRLI to be fused to zero extension of word.
202 ; CHECK: zfa - 'Zfa' (Additional Floating-Point).
203 ; CHECK: zfbfmin - 'Zfbfmin' (Scalar BF16 Converts).
204 ; CHECK: zfh - 'Zfh' (Half-Precision Floating-Point).
205 ; CHECK: zfhmin - 'Zfhmin' (Half-Precision Floating-Point Minimal).
206 ; CHECK: zfinx - 'Zfinx' (Float in Integer).
207 ; CHECK: zhinx - 'Zhinx' (Half Float in Integer).
208 ; CHECK: zhinxmin - 'Zhinxmin' (Half Float in Integer Minimal).
209 ; CHECK: zic64b - 'Zic64b' (Cache Block Size Is 64 Bytes).
210 ; CHECK: zicbom - 'Zicbom' (Cache-Block Management Instructions).
211 ; CHECK: zicbop - 'Zicbop' (Cache-Block Prefetch Instructions).
212 ; CHECK: zicboz - 'Zicboz' (Cache-Block Zero Instructions).
213 ; CHECK: ziccamoa - 'Ziccamoa' (Main Memory Supports All Atomics in A).
214 ; CHECK: ziccif - 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement).
215 ; CHECK: zicclsm - 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores).
216 ; CHECK: ziccrse - 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences).
217 ; CHECK: zicntr - 'Zicntr' (Base Counters and Timers).
218 ; CHECK: zicond - 'Zicond' (Integer Conditional Operations).
219 ; CHECK: zicsr - 'Zicsr' (CSRs).
220 ; CHECK: zifencei - 'Zifencei' (fence.i).
221 ; CHECK: zihintntl - 'Zihintntl' (Non-Temporal Locality Hints).
222 ; CHECK: zihintpause - 'Zihintpause' (Pause Hint).
223 ; CHECK: zihpm - 'Zihpm' (Hardware Performance Counters).
224 ; CHECK: zimop - 'Zimop' (May-Be-Operations).
225 ; CHECK: zk - 'Zk' (Standard scalar cryptography extension).
226 ; CHECK: zkn - 'Zkn' (NIST Algorithm Suite).
227 ; CHECK: zknd - 'Zknd' (NIST Suite: AES Decryption).
228 ; CHECK: zkne - 'Zkne' (NIST Suite: AES Encryption).
229 ; CHECK: zknh - 'Zknh' (NIST Suite: Hash Function Instructions).
230 ; CHECK: zkr - 'Zkr' (Entropy Source Extension).
231 ; CHECK: zks - 'Zks' (ShangMi Algorithm Suite).
232 ; CHECK: zksed - 'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions).
233 ; CHECK: zksh - 'Zksh' (ShangMi Suite: SM3 Hash Function Instructions).
234 ; CHECK: zkt - 'Zkt' (Data Independent Execution Latency).
235 ; CHECK: zmmul - 'Zmmul' (Integer Multiplication).
236 ; CHECK: ztso - 'Ztso' (Memory Model - Total Store Order).
237 ; CHECK: zvbb - 'Zvbb' (Vector basic bit-manipulation instructions).
238 ; CHECK: zvbc - 'Zvbc' (Vector Carryless Multiplication).
239 ; CHECK: zve32f - 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension).
240 ; CHECK: zve32x - 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW).
241 ; CHECK: zve64d - 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension).
242 ; CHECK: zve64f - 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension).
243 ; CHECK: zve64x - 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW).
244 ; CHECK: zvfbfmin - 'Zvfbfmin' (Vector BF16 Converts).
245 ; CHECK: zvfbfwma - 'Zvfbfwma' (Vector BF16 widening mul-add).
246 ; CHECK: zvfh - 'Zvfh' (Vector Half-Precision Floating-Point).
247 ; CHECK: zvfhmin - 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal).
248 ; CHECK: zvkb - 'Zvkb' (Vector Bit-manipulation used in Cryptography).
249 ; CHECK: zvkg - 'Zvkg' (Vector GCM instructions for Cryptography).
250 ; CHECK: zvkn - 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt').
251 ; CHECK: zvknc - 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc').
252 ; CHECK: zvkned - 'Zvkned' (Vector AES Encryption & Decryption (Single Round)).
253 ; CHECK: zvkng - 'Zvkng' (shorthand for 'Zvkn' and 'Zvkg').
254 ; CHECK: zvknha - 'Zvknha' (Vector SHA-2 (SHA-256 only)).
255 ; CHECK: zvknhb - 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512)).
256 ; CHECK: zvks - 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt').
257 ; CHECK: zvksc - 'Zvksc' (shorthand for 'Zvks' and 'Zvbc').
258 ; CHECK: zvksed - 'Zvksed' (SM4 Block Cipher Instructions).
259 ; CHECK: zvksg - 'Zvksg' (shorthand for 'Zvks' and 'Zvkg').
260 ; CHECK: zvksh - 'Zvksh' (SM3 Hash Function Instructions).
261 ; CHECK: zvkt - 'Zvkt' (Vector Data-Independent Execution Latency).
262 ; CHECK: zvl1024b - 'Zvl1024b' (Minimum Vector Length 1024).
263 ; CHECK: zvl128b - 'Zvl128b' (Minimum Vector Length 128).
264 ; CHECK: zvl16384b - 'Zvl16384b' (Minimum Vector Length 16384).
265 ; CHECK: zvl2048b - 'Zvl2048b' (Minimum Vector Length 2048).
266 ; CHECK: zvl256b - 'Zvl256b' (Minimum Vector Length 256).
267 ; CHECK: zvl32768b - 'Zvl32768b' (Minimum Vector Length 32768).
268 ; CHECK: zvl32b - 'Zvl32b' (Minimum Vector Length 32).
269 ; CHECK: zvl4096b - 'Zvl4096b' (Minimum Vector Length 4096).
270 ; CHECK: zvl512b - 'Zvl512b' (Minimum Vector Length 512).
271 ; CHECK: zvl64b - 'Zvl64b' (Minimum Vector Length 64).
272 ; CHECK: zvl65536b - 'Zvl65536b' (Minimum Vector Length 65536).
273 ; CHECK: zvl8192b - 'Zvl8192b' (Minimum Vector Length 8192).