1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
3 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
5 ; These tests check that the scalable-vector version of this series of
6 ; instructions does not get into an infinite DAGCombine loop. This was
7 ; originally exposing an infinite loop between an 'and' of two truncates being promoted
8 ; to the larger value type, then that 'truncate' being split back up into an
9 ; 'and' of two truncates.
10 ; This didn't happen in the fixed-length test because a truncate of the
11 ; constant BUILD_VECTOR is folded into the BUILD_VECTOR itself. The truncate of
12 ; a constant SPLAT_VECTOR didn't follow suit.
14 define <2 x i16> @fixedlen(<2 x i32> %x) {
15 ; CHECK-LABEL: fixedlen:
17 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
18 ; CHECK-NEXT: vsrl.vi v8, v8, 16
19 ; CHECK-NEXT: lui a0, 1048568
20 ; CHECK-NEXT: vand.vx v8, v8, a0
21 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
22 ; CHECK-NEXT: vnsrl.wi v8, v8, 0
24 %v43 = lshr <2 x i32> %x, splat (i32 16)
25 %v44 = trunc <2 x i32> %v43 to <2 x i16>
26 %v45 = insertelement <2 x i32> poison, i32 -32768, i32 0
27 %v46 = shufflevector <2 x i32> %v45, <2 x i32> poison, <2 x i32> zeroinitializer
28 %v47 = trunc <2 x i32> %v46 to <2 x i16>
29 %v48 = and <2 x i16> %v44, %v47
33 define <vscale x 2 x i16> @scalable(<vscale x 2 x i32> %x) {
34 ; CHECK-LABEL: scalable:
36 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
37 ; CHECK-NEXT: vnsrl.wi v8, v8, 16
38 ; CHECK-NEXT: lui a0, 1048568
39 ; CHECK-NEXT: vand.vx v8, v8, a0
41 %v43 = lshr <vscale x 2 x i32> %x, splat (i32 16)
42 %v44 = trunc <vscale x 2 x i32> %v43 to <vscale x 2 x i16>
43 %v45 = insertelement <vscale x 2 x i32> poison, i32 -32768, i32 0
44 %v46 = shufflevector <vscale x 2 x i32> %v45, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
45 %v47 = trunc <vscale x 2 x i32> %v46 to <vscale x 2 x i16>
46 %v48 = and <vscale x 2 x i16> %v44, %v47
47 ret <vscale x 2 x i16> %v48