| blob | 6f515996677ee64cfc07c3bc998342069fc3ab2c |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+m -target-abi=ilp32d \
3 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
4 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+m -target-abi=lp64d \
5 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
6 ; RUN: llc -mtriple=riscv32 -mattr=+v,+zvbb,+m -target-abi=ilp32d \
7 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
8 ; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+m -target-abi=lp64d \
9 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
11 declare <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8>, i1 immarg, <vscale x 1 x i1>, i32)
13 define <vscale x 1 x i8> @vp_ctlz_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
14 ; CHECK-LABEL: vp_ctlz_nxv1i8:
15 ; CHECK: # %bb.0:
16 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
17 ; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
18 ; CHECK-NEXT: li a0, 134
19 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t
20 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
21 ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
22 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
23 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
24 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
25 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
26 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
27 ; CHECK-NEXT: li a0, 8
28 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
29 ; CHECK-NEXT: ret
30 ;
31 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i8:
32 ; CHECK-ZVBB: # %bb.0:
33 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
34 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
35 ; CHECK-ZVBB-NEXT: ret
36 %v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
37 ret <vscale x 1 x i8> %v
38 }
40 define <vscale x 1 x i8> @vp_ctlz_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
41 ; CHECK-LABEL: vp_ctlz_nxv1i8_unmasked:
42 ; CHECK: # %bb.0:
43 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
44 ; CHECK-NEXT: vzext.vf2 v9, v8
45 ; CHECK-NEXT: li a0, 134
46 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
47 ; CHECK-NEXT: vnsrl.wi v8, v8, 23
48 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
49 ; CHECK-NEXT: vnsrl.wi v8, v8, 0
50 ; CHECK-NEXT: vrsub.vx v8, v8, a0
51 ; CHECK-NEXT: li a0, 8
52 ; CHECK-NEXT: vminu.vx v8, v8, a0
53 ; CHECK-NEXT: ret
54 ;
55 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i8_unmasked:
56 ; CHECK-ZVBB: # %bb.0:
57 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
58 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
59 ; CHECK-ZVBB-NEXT: ret
60 %v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
61 ret <vscale x 1 x i8> %v
62 }
64 declare <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8>, i1 immarg, <vscale x 2 x i1>, i32)
66 define <vscale x 2 x i8> @vp_ctlz_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
67 ; CHECK-LABEL: vp_ctlz_nxv2i8:
68 ; CHECK: # %bb.0:
69 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
70 ; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
71 ; CHECK-NEXT: li a0, 134
72 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t
73 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
74 ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
75 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
76 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
77 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
78 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
79 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
80 ; CHECK-NEXT: li a0, 8
81 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
82 ; CHECK-NEXT: ret
83 ;
84 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i8:
85 ; CHECK-ZVBB: # %bb.0:
86 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
87 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
88 ; CHECK-ZVBB-NEXT: ret
89 %v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
90 ret <vscale x 2 x i8> %v
91 }
93 define <vscale x 2 x i8> @vp_ctlz_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
94 ; CHECK-LABEL: vp_ctlz_nxv2i8_unmasked:
95 ; CHECK: # %bb.0:
96 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
97 ; CHECK-NEXT: vzext.vf2 v9, v8
98 ; CHECK-NEXT: li a0, 134
99 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
100 ; CHECK-NEXT: vnsrl.wi v8, v8, 23
101 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
102 ; CHECK-NEXT: vnsrl.wi v8, v8, 0
103 ; CHECK-NEXT: vrsub.vx v8, v8, a0
104 ; CHECK-NEXT: li a0, 8
105 ; CHECK-NEXT: vminu.vx v8, v8, a0
106 ; CHECK-NEXT: ret
107 ;
108 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i8_unmasked:
109 ; CHECK-ZVBB: # %bb.0:
110 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
111 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
112 ; CHECK-ZVBB-NEXT: ret
113 %v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
114 ret <vscale x 2 x i8> %v
115 }
117 declare <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8>, i1 immarg, <vscale x 4 x i1>, i32)
119 define <vscale x 4 x i8> @vp_ctlz_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
120 ; CHECK-LABEL: vp_ctlz_nxv4i8:
121 ; CHECK: # %bb.0:
122 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
123 ; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
124 ; CHECK-NEXT: li a0, 134
125 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v9, v0.t
126 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
127 ; CHECK-NEXT: vsrl.vi v8, v10, 23, v0.t
128 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
129 ; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
130 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
131 ; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t
132 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
133 ; CHECK-NEXT: li a0, 8
134 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
135 ; CHECK-NEXT: ret
136 ;
137 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i8:
138 ; CHECK-ZVBB: # %bb.0:
139 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
140 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
141 ; CHECK-ZVBB-NEXT: ret
142 %v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
143 ret <vscale x 4 x i8> %v
144 }
146 define <vscale x 4 x i8> @vp_ctlz_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
147 ; CHECK-LABEL: vp_ctlz_nxv4i8_unmasked:
148 ; CHECK: # %bb.0:
149 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
150 ; CHECK-NEXT: vzext.vf2 v9, v8
151 ; CHECK-NEXT: li a0, 134
152 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
153 ; CHECK-NEXT: vnsrl.wi v8, v10, 23
154 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
155 ; CHECK-NEXT: vnsrl.wi v8, v8, 0
156 ; CHECK-NEXT: vrsub.vx v8, v8, a0
157 ; CHECK-NEXT: li a0, 8
158 ; CHECK-NEXT: vminu.vx v8, v8, a0
159 ; CHECK-NEXT: ret
160 ;
161 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i8_unmasked:
162 ; CHECK-ZVBB: # %bb.0:
163 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
164 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
165 ; CHECK-ZVBB-NEXT: ret
166 %v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
167 ret <vscale x 4 x i8> %v
168 }
170 declare <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8>, i1 immarg, <vscale x 8 x i1>, i32)
172 define <vscale x 8 x i8> @vp_ctlz_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
173 ; CHECK-LABEL: vp_ctlz_nxv8i8:
174 ; CHECK: # %bb.0:
175 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
176 ; CHECK-NEXT: vzext.vf2 v10, v8, v0.t
177 ; CHECK-NEXT: li a0, 134
178 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v10, v0.t
179 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
180 ; CHECK-NEXT: vsrl.vi v8, v12, 23, v0.t
181 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
182 ; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
183 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
184 ; CHECK-NEXT: vnsrl.wi v8, v12, 0, v0.t
185 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
186 ; CHECK-NEXT: li a0, 8
187 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
188 ; CHECK-NEXT: ret
189 ;
190 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i8:
191 ; CHECK-ZVBB: # %bb.0:
192 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
193 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
194 ; CHECK-ZVBB-NEXT: ret
195 %v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
196 ret <vscale x 8 x i8> %v
197 }
199 define <vscale x 8 x i8> @vp_ctlz_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
200 ; CHECK-LABEL: vp_ctlz_nxv8i8_unmasked:
201 ; CHECK: # %bb.0:
202 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
203 ; CHECK-NEXT: vzext.vf2 v10, v8
204 ; CHECK-NEXT: li a0, 134
205 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v10
206 ; CHECK-NEXT: vnsrl.wi v8, v12, 23
207 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
208 ; CHECK-NEXT: vnsrl.wi v10, v8, 0
209 ; CHECK-NEXT: vrsub.vx v8, v10, a0
210 ; CHECK-NEXT: li a0, 8
211 ; CHECK-NEXT: vminu.vx v8, v8, a0
212 ; CHECK-NEXT: ret
213 ;
214 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i8_unmasked:
215 ; CHECK-ZVBB: # %bb.0:
216 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
217 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
218 ; CHECK-ZVBB-NEXT: ret
219 %v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
220 ret <vscale x 8 x i8> %v
221 }
223 declare <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8>, i1 immarg, <vscale x 16 x i1>, i32)
225 define <vscale x 16 x i8> @vp_ctlz_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
226 ; CHECK-LABEL: vp_ctlz_nxv16i8:
227 ; CHECK: # %bb.0:
228 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
229 ; CHECK-NEXT: vzext.vf2 v12, v8, v0.t
230 ; CHECK-NEXT: li a0, 134
231 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v12, v0.t
232 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
233 ; CHECK-NEXT: vsrl.vi v8, v16, 23, v0.t
234 ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
235 ; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
236 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
237 ; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
238 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
239 ; CHECK-NEXT: li a0, 8
240 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
241 ; CHECK-NEXT: ret
242 ;
243 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i8:
244 ; CHECK-ZVBB: # %bb.0:
245 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
246 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
247 ; CHECK-ZVBB-NEXT: ret
248 %v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
249 ret <vscale x 16 x i8> %v
250 }
252 define <vscale x 16 x i8> @vp_ctlz_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
253 ; CHECK-LABEL: vp_ctlz_nxv16i8_unmasked:
254 ; CHECK: # %bb.0:
255 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
256 ; CHECK-NEXT: vzext.vf2 v12, v8
257 ; CHECK-NEXT: li a0, 134
258 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
259 ; CHECK-NEXT: vnsrl.wi v8, v16, 23
260 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
261 ; CHECK-NEXT: vnsrl.wi v12, v8, 0
262 ; CHECK-NEXT: vrsub.vx v8, v12, a0
263 ; CHECK-NEXT: li a0, 8
264 ; CHECK-NEXT: vminu.vx v8, v8, a0
265 ; CHECK-NEXT: ret
266 ;
267 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i8_unmasked:
268 ; CHECK-ZVBB: # %bb.0:
269 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
270 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
271 ; CHECK-ZVBB-NEXT: ret
272 %v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
273 ret <vscale x 16 x i8> %v
274 }
276 declare <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8>, i1 immarg, <vscale x 32 x i1>, i32)
278 define <vscale x 32 x i8> @vp_ctlz_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
279 ; CHECK-LABEL: vp_ctlz_nxv32i8:
280 ; CHECK: # %bb.0:
281 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
282 ; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
283 ; CHECK-NEXT: li a0, 85
284 ; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
285 ; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
286 ; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
287 ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
288 ; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
289 ; CHECK-NEXT: vnot.v v8, v8, v0.t
290 ; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
291 ; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
292 ; CHECK-NEXT: li a0, 51
293 ; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t
294 ; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
295 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
296 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
297 ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
298 ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
299 ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
300 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
301 ; CHECK-NEXT: ret
302 ;
303 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv32i8:
304 ; CHECK-ZVBB: # %bb.0:
305 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
306 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
307 ; CHECK-ZVBB-NEXT: ret
308 %v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
309 ret <vscale x 32 x i8> %v
310 }
312 define <vscale x 32 x i8> @vp_ctlz_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
313 ; CHECK-LABEL: vp_ctlz_nxv32i8_unmasked:
314 ; CHECK: # %bb.0:
315 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
316 ; CHECK-NEXT: vsrl.vi v12, v8, 1
317 ; CHECK-NEXT: li a0, 85
318 ; CHECK-NEXT: vor.vv v8, v8, v12
319 ; CHECK-NEXT: vsrl.vi v12, v8, 2
320 ; CHECK-NEXT: vor.vv v8, v8, v12
321 ; CHECK-NEXT: vsrl.vi v12, v8, 4
322 ; CHECK-NEXT: vor.vv v8, v8, v12
323 ; CHECK-NEXT: vnot.v v8, v8
324 ; CHECK-NEXT: vsrl.vi v12, v8, 1
325 ; CHECK-NEXT: vand.vx v12, v12, a0
326 ; CHECK-NEXT: li a0, 51
327 ; CHECK-NEXT: vsub.vv v8, v8, v12
328 ; CHECK-NEXT: vand.vx v12, v8, a0
329 ; CHECK-NEXT: vsrl.vi v8, v8, 2
330 ; CHECK-NEXT: vand.vx v8, v8, a0
331 ; CHECK-NEXT: vadd.vv v8, v12, v8
332 ; CHECK-NEXT: vsrl.vi v12, v8, 4
333 ; CHECK-NEXT: vadd.vv v8, v8, v12
334 ; CHECK-NEXT: vand.vi v8, v8, 15
335 ; CHECK-NEXT: ret
336 ;
337 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv32i8_unmasked:
338 ; CHECK-ZVBB: # %bb.0:
339 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
340 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
341 ; CHECK-ZVBB-NEXT: ret
342 %v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, i1 false, <vscale x 32 x i1> splat (i1 true), i32 %evl)
343 ret <vscale x 32 x i8> %v
344 }
346 declare <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8>, i1 immarg, <vscale x 64 x i1>, i32)
348 define <vscale x 64 x i8> @vp_ctlz_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
349 ; CHECK-LABEL: vp_ctlz_nxv64i8:
350 ; CHECK: # %bb.0:
351 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
352 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
353 ; CHECK-NEXT: li a0, 85
354 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
355 ; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t
356 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
357 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
358 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
359 ; CHECK-NEXT: vnot.v v8, v8, v0.t
360 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
361 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
362 ; CHECK-NEXT: li a0, 51
363 ; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t
364 ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
365 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
366 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
367 ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
368 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
369 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
370 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
371 ; CHECK-NEXT: ret
372 ;
373 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv64i8:
374 ; CHECK-ZVBB: # %bb.0:
375 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma
376 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
377 ; CHECK-ZVBB-NEXT: ret
378 %v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> %m, i32 %evl)
379 ret <vscale x 64 x i8> %v
380 }
382 define <vscale x 64 x i8> @vp_ctlz_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
383 ; CHECK-LABEL: vp_ctlz_nxv64i8_unmasked:
384 ; CHECK: # %bb.0:
385 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
386 ; CHECK-NEXT: vsrl.vi v16, v8, 1
387 ; CHECK-NEXT: li a0, 85
388 ; CHECK-NEXT: vor.vv v8, v8, v16
389 ; CHECK-NEXT: vsrl.vi v16, v8, 2
390 ; CHECK-NEXT: vor.vv v8, v8, v16
391 ; CHECK-NEXT: vsrl.vi v16, v8, 4
392 ; CHECK-NEXT: vor.vv v8, v8, v16
393 ; CHECK-NEXT: vnot.v v8, v8
394 ; CHECK-NEXT: vsrl.vi v16, v8, 1
395 ; CHECK-NEXT: vand.vx v16, v16, a0
396 ; CHECK-NEXT: li a0, 51
397 ; CHECK-NEXT: vsub.vv v8, v8, v16
398 ; CHECK-NEXT: vand.vx v16, v8, a0
399 ; CHECK-NEXT: vsrl.vi v8, v8, 2
400 ; CHECK-NEXT: vand.vx v8, v8, a0
401 ; CHECK-NEXT: vadd.vv v8, v16, v8
402 ; CHECK-NEXT: vsrl.vi v16, v8, 4
403 ; CHECK-NEXT: vadd.vv v8, v8, v16
404 ; CHECK-NEXT: vand.vi v8, v8, 15
405 ; CHECK-NEXT: ret
406 ;
407 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv64i8_unmasked:
408 ; CHECK-ZVBB: # %bb.0:
409 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma
410 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
411 ; CHECK-ZVBB-NEXT: ret
412 %v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, i1 false, <vscale x 64 x i1> splat (i1 true), i32 %evl)
413 ret <vscale x 64 x i8> %v
414 }
416 declare <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16>, i1 immarg, <vscale x 1 x i1>, i32)
418 define <vscale x 1 x i16> @vp_ctlz_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
419 ; CHECK-LABEL: vp_ctlz_nxv1i16:
420 ; CHECK: # %bb.0:
421 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
422 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
423 ; CHECK-NEXT: li a0, 142
424 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
425 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
426 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
427 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
428 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
429 ; CHECK-NEXT: li a0, 16
430 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
431 ; CHECK-NEXT: ret
432 ;
433 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i16:
434 ; CHECK-ZVBB: # %bb.0:
435 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
436 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
437 ; CHECK-ZVBB-NEXT: ret
438 %v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
439 ret <vscale x 1 x i16> %v
440 }
442 define <vscale x 1 x i16> @vp_ctlz_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
443 ; CHECK-LABEL: vp_ctlz_nxv1i16_unmasked:
444 ; CHECK: # %bb.0:
445 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
446 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
447 ; CHECK-NEXT: li a0, 142
448 ; CHECK-NEXT: vnsrl.wi v8, v9, 23
449 ; CHECK-NEXT: vrsub.vx v8, v8, a0
450 ; CHECK-NEXT: li a0, 16
451 ; CHECK-NEXT: vminu.vx v8, v8, a0
452 ; CHECK-NEXT: ret
453 ;
454 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i16_unmasked:
455 ; CHECK-ZVBB: # %bb.0:
456 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
457 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
458 ; CHECK-ZVBB-NEXT: ret
459 %v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
460 ret <vscale x 1 x i16> %v
461 }
463 declare <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16>, i1 immarg, <vscale x 2 x i1>, i32)
465 define <vscale x 2 x i16> @vp_ctlz_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
466 ; CHECK-LABEL: vp_ctlz_nxv2i16:
467 ; CHECK: # %bb.0:
468 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
469 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
470 ; CHECK-NEXT: li a0, 142
471 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
472 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
473 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
474 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
475 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
476 ; CHECK-NEXT: li a0, 16
477 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
478 ; CHECK-NEXT: ret
479 ;
480 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i16:
481 ; CHECK-ZVBB: # %bb.0:
482 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
483 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
484 ; CHECK-ZVBB-NEXT: ret
485 %v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
486 ret <vscale x 2 x i16> %v
487 }
489 define <vscale x 2 x i16> @vp_ctlz_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
490 ; CHECK-LABEL: vp_ctlz_nxv2i16_unmasked:
491 ; CHECK: # %bb.0:
492 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
493 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
494 ; CHECK-NEXT: li a0, 142
495 ; CHECK-NEXT: vnsrl.wi v8, v9, 23
496 ; CHECK-NEXT: vrsub.vx v8, v8, a0
497 ; CHECK-NEXT: li a0, 16
498 ; CHECK-NEXT: vminu.vx v8, v8, a0
499 ; CHECK-NEXT: ret
500 ;
501 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i16_unmasked:
502 ; CHECK-ZVBB: # %bb.0:
503 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
504 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
505 ; CHECK-ZVBB-NEXT: ret
506 %v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
507 ret <vscale x 2 x i16> %v
508 }
510 declare <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16>, i1 immarg, <vscale x 4 x i1>, i32)
512 define <vscale x 4 x i16> @vp_ctlz_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
513 ; CHECK-LABEL: vp_ctlz_nxv4i16:
514 ; CHECK: # %bb.0:
515 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
516 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8, v0.t
517 ; CHECK-NEXT: li a0, 142
518 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
519 ; CHECK-NEXT: vsrl.vi v8, v10, 23, v0.t
520 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
521 ; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
522 ; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t
523 ; CHECK-NEXT: li a0, 16
524 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
525 ; CHECK-NEXT: ret
526 ;
527 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i16:
528 ; CHECK-ZVBB: # %bb.0:
529 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
530 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
531 ; CHECK-ZVBB-NEXT: ret
532 %v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
533 ret <vscale x 4 x i16> %v
534 }
536 define <vscale x 4 x i16> @vp_ctlz_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
537 ; CHECK-LABEL: vp_ctlz_nxv4i16_unmasked:
538 ; CHECK: # %bb.0:
539 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
540 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
541 ; CHECK-NEXT: li a0, 142
542 ; CHECK-NEXT: vnsrl.wi v8, v10, 23
543 ; CHECK-NEXT: vrsub.vx v8, v8, a0
544 ; CHECK-NEXT: li a0, 16
545 ; CHECK-NEXT: vminu.vx v8, v8, a0
546 ; CHECK-NEXT: ret
547 ;
548 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i16_unmasked:
549 ; CHECK-ZVBB: # %bb.0:
550 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
551 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
552 ; CHECK-ZVBB-NEXT: ret
553 %v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
554 ret <vscale x 4 x i16> %v
555 }
557 declare <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16>, i1 immarg, <vscale x 8 x i1>, i32)
559 define <vscale x 8 x i16> @vp_ctlz_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
560 ; CHECK-LABEL: vp_ctlz_nxv8i16:
561 ; CHECK: # %bb.0:
562 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
563 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8, v0.t
564 ; CHECK-NEXT: li a0, 142
565 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
566 ; CHECK-NEXT: vsrl.vi v8, v12, 23, v0.t
567 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
568 ; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
569 ; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t
570 ; CHECK-NEXT: li a0, 16
571 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
572 ; CHECK-NEXT: ret
573 ;
574 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i16:
575 ; CHECK-ZVBB: # %bb.0:
576 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
577 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
578 ; CHECK-ZVBB-NEXT: ret
579 %v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
580 ret <vscale x 8 x i16> %v
581 }
583 define <vscale x 8 x i16> @vp_ctlz_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
584 ; CHECK-LABEL: vp_ctlz_nxv8i16_unmasked:
585 ; CHECK: # %bb.0:
586 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
587 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
588 ; CHECK-NEXT: li a0, 142
589 ; CHECK-NEXT: vnsrl.wi v8, v12, 23
590 ; CHECK-NEXT: vrsub.vx v8, v8, a0
591 ; CHECK-NEXT: li a0, 16
592 ; CHECK-NEXT: vminu.vx v8, v8, a0
593 ; CHECK-NEXT: ret
594 ;
595 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i16_unmasked:
596 ; CHECK-ZVBB: # %bb.0:
597 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
598 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
599 ; CHECK-ZVBB-NEXT: ret
600 %v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
601 ret <vscale x 8 x i16> %v
602 }
604 declare <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16>, i1 immarg, <vscale x 16 x i1>, i32)
606 define <vscale x 16 x i16> @vp_ctlz_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
607 ; CHECK-LABEL: vp_ctlz_nxv16i16:
608 ; CHECK: # %bb.0:
609 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
610 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8, v0.t
611 ; CHECK-NEXT: li a0, 142
612 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
613 ; CHECK-NEXT: vsrl.vi v8, v16, 23, v0.t
614 ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
615 ; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
616 ; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t
617 ; CHECK-NEXT: li a0, 16
618 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
619 ; CHECK-NEXT: ret
620 ;
621 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i16:
622 ; CHECK-ZVBB: # %bb.0:
623 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
624 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
625 ; CHECK-ZVBB-NEXT: ret
626 %v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
627 ret <vscale x 16 x i16> %v
628 }
630 define <vscale x 16 x i16> @vp_ctlz_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
631 ; CHECK-LABEL: vp_ctlz_nxv16i16_unmasked:
632 ; CHECK: # %bb.0:
633 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
634 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
635 ; CHECK-NEXT: li a0, 142
636 ; CHECK-NEXT: vnsrl.wi v8, v16, 23
637 ; CHECK-NEXT: vrsub.vx v8, v8, a0
638 ; CHECK-NEXT: li a0, 16
639 ; CHECK-NEXT: vminu.vx v8, v8, a0
640 ; CHECK-NEXT: ret
641 ;
642 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i16_unmasked:
643 ; CHECK-ZVBB: # %bb.0:
644 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
645 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
646 ; CHECK-ZVBB-NEXT: ret
647 %v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
648 ret <vscale x 16 x i16> %v
649 }
651 declare <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16>, i1 immarg, <vscale x 32 x i1>, i32)
653 define <vscale x 32 x i16> @vp_ctlz_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
654 ; CHECK-LABEL: vp_ctlz_nxv32i16:
655 ; CHECK: # %bb.0:
656 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
657 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
658 ; CHECK-NEXT: lui a0, 5
659 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
660 ; CHECK-NEXT: addi a0, a0, 1365
661 ; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t
662 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
663 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
664 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
665 ; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
666 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
667 ; CHECK-NEXT: vnot.v v8, v8, v0.t
668 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
669 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
670 ; CHECK-NEXT: lui a0, 3
671 ; CHECK-NEXT: addi a0, a0, 819
672 ; CHECK-NEXT: vsub.vv v16, v8, v16, v0.t
673 ; CHECK-NEXT: vand.vx v8, v16, a0, v0.t
674 ; CHECK-NEXT: vsrl.vi v16, v16, 2, v0.t
675 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
676 ; CHECK-NEXT: lui a0, 1
677 ; CHECK-NEXT: addi a0, a0, -241
678 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
679 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
680 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
681 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
682 ; CHECK-NEXT: li a0, 257
683 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
684 ; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t
685 ; CHECK-NEXT: ret
686 ;
687 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv32i16:
688 ; CHECK-ZVBB: # %bb.0:
689 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
690 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
691 ; CHECK-ZVBB-NEXT: ret
692 %v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> %m, i32 %evl)
693 ret <vscale x 32 x i16> %v
694 }
696 define <vscale x 32 x i16> @vp_ctlz_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
697 ; CHECK-LABEL: vp_ctlz_nxv32i16_unmasked:
698 ; CHECK: # %bb.0:
699 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
700 ; CHECK-NEXT: vsrl.vi v16, v8, 1
701 ; CHECK-NEXT: lui a0, 5
702 ; CHECK-NEXT: vor.vv v8, v8, v16
703 ; CHECK-NEXT: addi a0, a0, 1365
704 ; CHECK-NEXT: vsrl.vi v16, v8, 2
705 ; CHECK-NEXT: vor.vv v8, v8, v16
706 ; CHECK-NEXT: vsrl.vi v16, v8, 4
707 ; CHECK-NEXT: vor.vv v8, v8, v16
708 ; CHECK-NEXT: vsrl.vi v16, v8, 8
709 ; CHECK-NEXT: vor.vv v8, v8, v16
710 ; CHECK-NEXT: vnot.v v8, v8
711 ; CHECK-NEXT: vsrl.vi v16, v8, 1
712 ; CHECK-NEXT: vand.vx v16, v16, a0
713 ; CHECK-NEXT: lui a0, 3
714 ; CHECK-NEXT: addi a0, a0, 819
715 ; CHECK-NEXT: vsub.vv v8, v8, v16
716 ; CHECK-NEXT: vand.vx v16, v8, a0
717 ; CHECK-NEXT: vsrl.vi v8, v8, 2
718 ; CHECK-NEXT: vand.vx v8, v8, a0
719 ; CHECK-NEXT: lui a0, 1
720 ; CHECK-NEXT: addi a0, a0, -241
721 ; CHECK-NEXT: vadd.vv v8, v16, v8
722 ; CHECK-NEXT: vsrl.vi v16, v8, 4
723 ; CHECK-NEXT: vadd.vv v8, v8, v16
724 ; CHECK-NEXT: vand.vx v8, v8, a0
725 ; CHECK-NEXT: li a0, 257
726 ; CHECK-NEXT: vmul.vx v8, v8, a0
727 ; CHECK-NEXT: vsrl.vi v8, v8, 8
728 ; CHECK-NEXT: ret
729 ;
730 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv32i16_unmasked:
731 ; CHECK-ZVBB: # %bb.0:
732 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
733 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
734 ; CHECK-ZVBB-NEXT: ret
735 %v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, i1 false, <vscale x 32 x i1> splat (i1 true), i32 %evl)
736 ret <vscale x 32 x i16> %v
737 }
739 declare <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32>, i1 immarg, <vscale x 1 x i1>, i32)
741 define <vscale x 1 x i32> @vp_ctlz_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
742 ; CHECK-LABEL: vp_ctlz_nxv1i32:
743 ; CHECK: # %bb.0:
744 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
745 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
746 ; CHECK-NEXT: li a0, 52
747 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
748 ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
749 ; CHECK-NEXT: li a0, 1054
750 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
751 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
752 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
753 ; CHECK-NEXT: li a0, 32
754 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
755 ; CHECK-NEXT: ret
756 ;
757 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i32:
758 ; CHECK-ZVBB: # %bb.0:
759 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
760 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
761 ; CHECK-ZVBB-NEXT: ret
762 %v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
763 ret <vscale x 1 x i32> %v
764 }
766 define <vscale x 1 x i32> @vp_ctlz_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
767 ; CHECK-LABEL: vp_ctlz_nxv1i32_unmasked:
768 ; CHECK: # %bb.0:
769 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
770 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
771 ; CHECK-NEXT: li a0, 52
772 ; CHECK-NEXT: vnsrl.wx v8, v9, a0
773 ; CHECK-NEXT: li a0, 1054
774 ; CHECK-NEXT: vrsub.vx v8, v8, a0
775 ; CHECK-NEXT: li a0, 32
776 ; CHECK-NEXT: vminu.vx v8, v8, a0
777 ; CHECK-NEXT: ret
778 ;
779 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i32_unmasked:
780 ; CHECK-ZVBB: # %bb.0:
781 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
782 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
783 ; CHECK-ZVBB-NEXT: ret
784 %v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
785 ret <vscale x 1 x i32> %v
786 }
788 declare <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32>, i1 immarg, <vscale x 2 x i1>, i32)
790 define <vscale x 2 x i32> @vp_ctlz_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
791 ; CHECK-LABEL: vp_ctlz_nxv2i32:
792 ; CHECK: # %bb.0:
793 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
794 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8, v0.t
795 ; CHECK-NEXT: li a0, 52
796 ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
797 ; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
798 ; CHECK-NEXT: li a0, 1054
799 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
800 ; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
801 ; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t
802 ; CHECK-NEXT: li a0, 32
803 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
804 ; CHECK-NEXT: ret
805 ;
806 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i32:
807 ; CHECK-ZVBB: # %bb.0:
808 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
809 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
810 ; CHECK-ZVBB-NEXT: ret
811 %v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
812 ret <vscale x 2 x i32> %v
813 }
815 define <vscale x 2 x i32> @vp_ctlz_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
816 ; CHECK-LABEL: vp_ctlz_nxv2i32_unmasked:
817 ; CHECK: # %bb.0:
818 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
819 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
820 ; CHECK-NEXT: li a0, 52
821 ; CHECK-NEXT: vnsrl.wx v8, v10, a0
822 ; CHECK-NEXT: li a0, 1054
823 ; CHECK-NEXT: vrsub.vx v8, v8, a0
824 ; CHECK-NEXT: li a0, 32
825 ; CHECK-NEXT: vminu.vx v8, v8, a0
826 ; CHECK-NEXT: ret
827 ;
828 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i32_unmasked:
829 ; CHECK-ZVBB: # %bb.0:
830 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
831 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
832 ; CHECK-ZVBB-NEXT: ret
833 %v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
834 ret <vscale x 2 x i32> %v
835 }
837 declare <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32>, i1 immarg, <vscale x 4 x i1>, i32)
839 define <vscale x 4 x i32> @vp_ctlz_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
840 ; CHECK-LABEL: vp_ctlz_nxv4i32:
841 ; CHECK: # %bb.0:
842 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
843 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8, v0.t
844 ; CHECK-NEXT: li a0, 52
845 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
846 ; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
847 ; CHECK-NEXT: li a0, 1054
848 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
849 ; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
850 ; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t
851 ; CHECK-NEXT: li a0, 32
852 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
853 ; CHECK-NEXT: ret
854 ;
855 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i32:
856 ; CHECK-ZVBB: # %bb.0:
857 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
858 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
859 ; CHECK-ZVBB-NEXT: ret
860 %v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
861 ret <vscale x 4 x i32> %v
862 }
864 define <vscale x 4 x i32> @vp_ctlz_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
865 ; CHECK-LABEL: vp_ctlz_nxv4i32_unmasked:
866 ; CHECK: # %bb.0:
867 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
868 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
869 ; CHECK-NEXT: li a0, 52
870 ; CHECK-NEXT: vnsrl.wx v8, v12, a0
871 ; CHECK-NEXT: li a0, 1054
872 ; CHECK-NEXT: vrsub.vx v8, v8, a0
873 ; CHECK-NEXT: li a0, 32
874 ; CHECK-NEXT: vminu.vx v8, v8, a0
875 ; CHECK-NEXT: ret
876 ;
877 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i32_unmasked:
878 ; CHECK-ZVBB: # %bb.0:
879 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
880 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
881 ; CHECK-ZVBB-NEXT: ret
882 %v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
883 ret <vscale x 4 x i32> %v
884 }
886 declare <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32>, i1 immarg, <vscale x 8 x i1>, i32)
888 define <vscale x 8 x i32> @vp_ctlz_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
889 ; CHECK-LABEL: vp_ctlz_nxv8i32:
890 ; CHECK: # %bb.0:
891 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
892 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8, v0.t
893 ; CHECK-NEXT: li a0, 52
894 ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
895 ; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
896 ; CHECK-NEXT: li a0, 1054
897 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
898 ; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
899 ; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t
900 ; CHECK-NEXT: li a0, 32
901 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
902 ; CHECK-NEXT: ret
903 ;
904 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i32:
905 ; CHECK-ZVBB: # %bb.0:
906 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
907 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
908 ; CHECK-ZVBB-NEXT: ret
909 %v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
910 ret <vscale x 8 x i32> %v
911 }
913 define <vscale x 8 x i32> @vp_ctlz_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
914 ; CHECK-LABEL: vp_ctlz_nxv8i32_unmasked:
915 ; CHECK: # %bb.0:
916 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
917 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
918 ; CHECK-NEXT: li a0, 52
919 ; CHECK-NEXT: vnsrl.wx v8, v16, a0
920 ; CHECK-NEXT: li a0, 1054
921 ; CHECK-NEXT: vrsub.vx v8, v8, a0
922 ; CHECK-NEXT: li a0, 32
923 ; CHECK-NEXT: vminu.vx v8, v8, a0
924 ; CHECK-NEXT: ret
925 ;
926 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i32_unmasked:
927 ; CHECK-ZVBB: # %bb.0:
928 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
929 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
930 ; CHECK-ZVBB-NEXT: ret
931 %v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
932 ret <vscale x 8 x i32> %v
933 }
935 declare <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32>, i1 immarg, <vscale x 16 x i1>, i32)
937 define <vscale x 16 x i32> @vp_ctlz_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
938 ; CHECK-LABEL: vp_ctlz_nxv16i32:
939 ; CHECK: # %bb.0:
940 ; CHECK-NEXT: fsrmi a1, 1
941 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
942 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
943 ; CHECK-NEXT: li a0, 158
944 ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
945 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
946 ; CHECK-NEXT: li a0, 32
947 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
948 ; CHECK-NEXT: fsrm a1
949 ; CHECK-NEXT: ret
950 ;
951 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i32:
952 ; CHECK-ZVBB: # %bb.0:
953 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
954 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
955 ; CHECK-ZVBB-NEXT: ret
956 %v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
957 ret <vscale x 16 x i32> %v
958 }
960 define <vscale x 16 x i32> @vp_ctlz_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
961 ; CHECK-LABEL: vp_ctlz_nxv16i32_unmasked:
962 ; CHECK: # %bb.0:
963 ; CHECK-NEXT: fsrmi a1, 1
964 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
965 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
966 ; CHECK-NEXT: li a0, 158
967 ; CHECK-NEXT: vsrl.vi v8, v8, 23
968 ; CHECK-NEXT: vrsub.vx v8, v8, a0
969 ; CHECK-NEXT: li a0, 32
970 ; CHECK-NEXT: vminu.vx v8, v8, a0
971 ; CHECK-NEXT: fsrm a1
972 ; CHECK-NEXT: ret
973 ;
974 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i32_unmasked:
975 ; CHECK-ZVBB: # %bb.0:
976 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
977 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
978 ; CHECK-ZVBB-NEXT: ret
979 %v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
980 ret <vscale x 16 x i32> %v
981 }
983 declare <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64>, i1 immarg, <vscale x 1 x i1>, i32)
985 define <vscale x 1 x i64> @vp_ctlz_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
986 ; CHECK-LABEL: vp_ctlz_nxv1i64:
987 ; CHECK: # %bb.0:
988 ; CHECK-NEXT: fsrmi a1, 1
989 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
990 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
991 ; CHECK-NEXT: li a0, 52
992 ; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
993 ; CHECK-NEXT: li a0, 1086
994 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
995 ; CHECK-NEXT: li a0, 64
996 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
997 ; CHECK-NEXT: fsrm a1
998 ; CHECK-NEXT: ret
999 ;
1000 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i64:
1001 ; CHECK-ZVBB: # %bb.0:
1002 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1003 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1004 ; CHECK-ZVBB-NEXT: ret
1005 %v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
1006 ret <vscale x 1 x i64> %v
1007 }
1009 define <vscale x 1 x i64> @vp_ctlz_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
1010 ; CHECK-LABEL: vp_ctlz_nxv1i64_unmasked:
1011 ; CHECK: # %bb.0:
1012 ; CHECK-NEXT: fsrmi a1, 1
1013 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1014 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
1015 ; CHECK-NEXT: li a0, 52
1016 ; CHECK-NEXT: vsrl.vx v8, v8, a0
1017 ; CHECK-NEXT: li a0, 1086
1018 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1019 ; CHECK-NEXT: li a0, 64
1020 ; CHECK-NEXT: vminu.vx v8, v8, a0
1021 ; CHECK-NEXT: fsrm a1
1022 ; CHECK-NEXT: ret
1023 ;
1024 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i64_unmasked:
1025 ; CHECK-ZVBB: # %bb.0:
1026 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
1027 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1028 ; CHECK-ZVBB-NEXT: ret
1029 %v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
1030 ret <vscale x 1 x i64> %v
1031 }
1033 declare <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64>, i1 immarg, <vscale x 2 x i1>, i32)
1035 define <vscale x 2 x i64> @vp_ctlz_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1036 ; CHECK-LABEL: vp_ctlz_nxv2i64:
1037 ; CHECK: # %bb.0:
1038 ; CHECK-NEXT: fsrmi a1, 1
1039 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1040 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
1041 ; CHECK-NEXT: li a0, 52
1042 ; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
1043 ; CHECK-NEXT: li a0, 1086
1044 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1045 ; CHECK-NEXT: li a0, 64
1046 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
1047 ; CHECK-NEXT: fsrm a1
1048 ; CHECK-NEXT: ret
1049 ;
1050 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i64:
1051 ; CHECK-ZVBB: # %bb.0:
1052 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1053 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1054 ; CHECK-ZVBB-NEXT: ret
1055 %v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> %m, i32 %evl)
1056 ret <vscale x 2 x i64> %v
1057 }
1059 define <vscale x 2 x i64> @vp_ctlz_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
1060 ; CHECK-LABEL: vp_ctlz_nxv2i64_unmasked:
1061 ; CHECK: # %bb.0:
1062 ; CHECK-NEXT: fsrmi a1, 1
1063 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1064 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
1065 ; CHECK-NEXT: li a0, 52
1066 ; CHECK-NEXT: vsrl.vx v8, v8, a0
1067 ; CHECK-NEXT: li a0, 1086
1068 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1069 ; CHECK-NEXT: li a0, 64
1070 ; CHECK-NEXT: vminu.vx v8, v8, a0
1071 ; CHECK-NEXT: fsrm a1
1072 ; CHECK-NEXT: ret
1073 ;
1074 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i64_unmasked:
1075 ; CHECK-ZVBB: # %bb.0:
1076 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
1077 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1078 ; CHECK-ZVBB-NEXT: ret
1079 %v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, i1 false, <vscale x 2 x i1> splat (i1 true), i32 %evl)
1080 ret <vscale x 2 x i64> %v
1081 }
1083 declare <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64>, i1 immarg, <vscale x 4 x i1>, i32)
1085 define <vscale x 4 x i64> @vp_ctlz_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1086 ; CHECK-LABEL: vp_ctlz_nxv4i64:
1087 ; CHECK: # %bb.0:
1088 ; CHECK-NEXT: fsrmi a1, 1
1089 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1090 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
1091 ; CHECK-NEXT: li a0, 52
1092 ; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
1093 ; CHECK-NEXT: li a0, 1086
1094 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1095 ; CHECK-NEXT: li a0, 64
1096 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
1097 ; CHECK-NEXT: fsrm a1
1098 ; CHECK-NEXT: ret
1099 ;
1100 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i64:
1101 ; CHECK-ZVBB: # %bb.0:
1102 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1103 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1104 ; CHECK-ZVBB-NEXT: ret
1105 %v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> %m, i32 %evl)
1106 ret <vscale x 4 x i64> %v
1107 }
1109 define <vscale x 4 x i64> @vp_ctlz_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
1110 ; CHECK-LABEL: vp_ctlz_nxv4i64_unmasked:
1111 ; CHECK: # %bb.0:
1112 ; CHECK-NEXT: fsrmi a1, 1
1113 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1114 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
1115 ; CHECK-NEXT: li a0, 52
1116 ; CHECK-NEXT: vsrl.vx v8, v8, a0
1117 ; CHECK-NEXT: li a0, 1086
1118 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1119 ; CHECK-NEXT: li a0, 64
1120 ; CHECK-NEXT: vminu.vx v8, v8, a0
1121 ; CHECK-NEXT: fsrm a1
1122 ; CHECK-NEXT: ret
1123 ;
1124 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i64_unmasked:
1125 ; CHECK-ZVBB: # %bb.0:
1126 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
1127 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1128 ; CHECK-ZVBB-NEXT: ret
1129 %v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, i1 false, <vscale x 4 x i1> splat (i1 true), i32 %evl)
1130 ret <vscale x 4 x i64> %v
1131 }
1133 declare <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64>, i1 immarg, <vscale x 7 x i1>, i32)
1135 define <vscale x 7 x i64> @vp_ctlz_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
1136 ; CHECK-LABEL: vp_ctlz_nxv7i64:
1137 ; CHECK: # %bb.0:
1138 ; CHECK-NEXT: fsrmi a1, 1
1139 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1140 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
1141 ; CHECK-NEXT: li a0, 52
1142 ; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
1143 ; CHECK-NEXT: li a0, 1086
1144 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1145 ; CHECK-NEXT: li a0, 64
1146 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
1147 ; CHECK-NEXT: fsrm a1
1148 ; CHECK-NEXT: ret
1149 ;
1150 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv7i64:
1151 ; CHECK-ZVBB: # %bb.0:
1152 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1153 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1154 ; CHECK-ZVBB-NEXT: ret
1155 %v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> %m, i32 %evl)
1156 ret <vscale x 7 x i64> %v
1157 }
1159 define <vscale x 7 x i64> @vp_ctlz_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
1160 ; CHECK-LABEL: vp_ctlz_nxv7i64_unmasked:
1161 ; CHECK: # %bb.0:
1162 ; CHECK-NEXT: fsrmi a1, 1
1163 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1164 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
1165 ; CHECK-NEXT: li a0, 52
1166 ; CHECK-NEXT: vsrl.vx v8, v8, a0
1167 ; CHECK-NEXT: li a0, 1086
1168 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1169 ; CHECK-NEXT: li a0, 64
1170 ; CHECK-NEXT: vminu.vx v8, v8, a0
1171 ; CHECK-NEXT: fsrm a1
1172 ; CHECK-NEXT: ret
1173 ;
1174 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv7i64_unmasked:
1175 ; CHECK-ZVBB: # %bb.0:
1176 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1177 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1178 ; CHECK-ZVBB-NEXT: ret
1179 %v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, i1 false, <vscale x 7 x i1> splat (i1 true), i32 %evl)
1180 ret <vscale x 7 x i64> %v
1181 }
1183 declare <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64>, i1 immarg, <vscale x 8 x i1>, i32)
1185 define <vscale x 8 x i64> @vp_ctlz_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1186 ; CHECK-LABEL: vp_ctlz_nxv8i64:
1187 ; CHECK: # %bb.0:
1188 ; CHECK-NEXT: fsrmi a1, 1
1189 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1190 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
1191 ; CHECK-NEXT: li a0, 52
1192 ; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
1193 ; CHECK-NEXT: li a0, 1086
1194 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1195 ; CHECK-NEXT: li a0, 64
1196 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
1197 ; CHECK-NEXT: fsrm a1
1198 ; CHECK-NEXT: ret
1199 ;
1200 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i64:
1201 ; CHECK-ZVBB: # %bb.0:
1202 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1203 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1204 ; CHECK-ZVBB-NEXT: ret
1205 %v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> %m, i32 %evl)
1206 ret <vscale x 8 x i64> %v
1207 }
1209 define <vscale x 8 x i64> @vp_ctlz_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
1210 ; CHECK-LABEL: vp_ctlz_nxv8i64_unmasked:
1211 ; CHECK: # %bb.0:
1212 ; CHECK-NEXT: fsrmi a1, 1
1213 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1214 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
1215 ; CHECK-NEXT: li a0, 52
1216 ; CHECK-NEXT: vsrl.vx v8, v8, a0
1217 ; CHECK-NEXT: li a0, 1086
1218 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1219 ; CHECK-NEXT: li a0, 64
1220 ; CHECK-NEXT: vminu.vx v8, v8, a0
1221 ; CHECK-NEXT: fsrm a1
1222 ; CHECK-NEXT: ret
1223 ;
1224 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i64_unmasked:
1225 ; CHECK-ZVBB: # %bb.0:
1226 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1227 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1228 ; CHECK-ZVBB-NEXT: ret
1229 %v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, i1 false, <vscale x 8 x i1> splat (i1 true), i32 %evl)
1230 ret <vscale x 8 x i64> %v
1231 }
1233 declare <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64>, i1 immarg, <vscale x 16 x i1>, i32)
1235 define <vscale x 16 x i64> @vp_ctlz_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
1236 ; CHECK-LABEL: vp_ctlz_nxv16i64:
1237 ; CHECK: # %bb.0:
1238 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
1239 ; CHECK-NEXT: vmv1r.v v24, v0
1240 ; CHECK-NEXT: csrr a1, vlenb
1241 ; CHECK-NEXT: fsrmi a4, 1
1242 ; CHECK-NEXT: li a2, 52
1243 ; CHECK-NEXT: srli a3, a1, 3
1244 ; CHECK-NEXT: sub a5, a0, a1
1245 ; CHECK-NEXT: vslidedown.vx v0, v0, a3
1246 ; CHECK-NEXT: sltu a3, a0, a5
1247 ; CHECK-NEXT: addi a3, a3, -1
1248 ; CHECK-NEXT: and a5, a3, a5
1249 ; CHECK-NEXT: li a3, 1086
1250 ; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
1251 ; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
1252 ; CHECK-NEXT: fsrm a4
1253 ; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
1254 ; CHECK-NEXT: vrsub.vx v16, v16, a3, v0.t
1255 ; CHECK-NEXT: li a4, 64
1256 ; CHECK-NEXT: vminu.vx v16, v16, a4, v0.t
1257 ; CHECK-NEXT: bltu a0, a1, .LBB46_2
1258 ; CHECK-NEXT: # %bb.1:
1259 ; CHECK-NEXT: mv a0, a1
1260 ; CHECK-NEXT: .LBB46_2:
1261 ; CHECK-NEXT: fsrmi a1, 1
1262 ; CHECK-NEXT: vmv1r.v v0, v24
1263 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1264 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
1265 ; CHECK-NEXT: vsrl.vx v8, v8, a2, v0.t
1266 ; CHECK-NEXT: vrsub.vx v8, v8, a3, v0.t
1267 ; CHECK-NEXT: vminu.vx v8, v8, a4, v0.t
1268 ; CHECK-NEXT: fsrm a1
1269 ; CHECK-NEXT: ret
1270 ;
1271 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i64:
1272 ; CHECK-ZVBB: # %bb.0:
1273 ; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
1274 ; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
1275 ; CHECK-ZVBB-NEXT: csrr a1, vlenb
1276 ; CHECK-ZVBB-NEXT: srli a2, a1, 3
1277 ; CHECK-ZVBB-NEXT: sub a3, a0, a1
1278 ; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
1279 ; CHECK-ZVBB-NEXT: sltu a2, a0, a3
1280 ; CHECK-ZVBB-NEXT: addi a2, a2, -1
1281 ; CHECK-ZVBB-NEXT: and a2, a2, a3
1282 ; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
1283 ; CHECK-ZVBB-NEXT: vclz.v v16, v16, v0.t
1284 ; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB46_2
1285 ; CHECK-ZVBB-NEXT: # %bb.1:
1286 ; CHECK-ZVBB-NEXT: mv a0, a1
1287 ; CHECK-ZVBB-NEXT: .LBB46_2:
1288 ; CHECK-ZVBB-NEXT: vmv1r.v v0, v24
1289 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1290 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1291 ; CHECK-ZVBB-NEXT: ret
1292 %v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> %m, i32 %evl)
1293 ret <vscale x 16 x i64> %v
1294 }
1296 define <vscale x 16 x i64> @vp_ctlz_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
1297 ; CHECK-LABEL: vp_ctlz_nxv16i64_unmasked:
1298 ; CHECK: # %bb.0:
1299 ; CHECK-NEXT: csrr a1, vlenb
1300 ; CHECK-NEXT: fsrmi a4, 1
1301 ; CHECK-NEXT: li a2, 52
1302 ; CHECK-NEXT: sub a3, a0, a1
1303 ; CHECK-NEXT: sltu a5, a0, a3
1304 ; CHECK-NEXT: addi a5, a5, -1
1305 ; CHECK-NEXT: and a5, a5, a3
1306 ; CHECK-NEXT: li a3, 1086
1307 ; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma
1308 ; CHECK-NEXT: vfcvt.f.xu.v v16, v16
1309 ; CHECK-NEXT: fsrm a4
1310 ; CHECK-NEXT: vsrl.vx v16, v16, a2
1311 ; CHECK-NEXT: vrsub.vx v16, v16, a3
1312 ; CHECK-NEXT: li a4, 64
1313 ; CHECK-NEXT: vminu.vx v16, v16, a4
1314 ; CHECK-NEXT: bltu a0, a1, .LBB47_2
1315 ; CHECK-NEXT: # %bb.1:
1316 ; CHECK-NEXT: mv a0, a1
1317 ; CHECK-NEXT: .LBB47_2:
1318 ; CHECK-NEXT: fsrmi a1, 1
1319 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1320 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
1321 ; CHECK-NEXT: vsrl.vx v8, v8, a2
1322 ; CHECK-NEXT: vrsub.vx v8, v8, a3
1323 ; CHECK-NEXT: vminu.vx v8, v8, a4
1324 ; CHECK-NEXT: fsrm a1
1325 ; CHECK-NEXT: ret
1326 ;
1327 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i64_unmasked:
1328 ; CHECK-ZVBB: # %bb.0:
1329 ; CHECK-ZVBB-NEXT: csrr a1, vlenb
1330 ; CHECK-ZVBB-NEXT: sub a2, a0, a1
1331 ; CHECK-ZVBB-NEXT: sltu a3, a0, a2
1332 ; CHECK-ZVBB-NEXT: addi a3, a3, -1
1333 ; CHECK-ZVBB-NEXT: and a2, a3, a2
1334 ; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
1335 ; CHECK-ZVBB-NEXT: vclz.v v16, v16
1336 ; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB47_2
1337 ; CHECK-ZVBB-NEXT: # %bb.1:
1338 ; CHECK-ZVBB-NEXT: mv a0, a1
1339 ; CHECK-ZVBB-NEXT: .LBB47_2:
1340 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
1341 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1342 ; CHECK-ZVBB-NEXT: ret
1343 %v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, i1 false, <vscale x 16 x i1> splat (i1 true), i32 %evl)
1344 ret <vscale x 16 x i64> %v
1345 }
1347 define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1348 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i8:
1349 ; CHECK: # %bb.0:
1350 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1351 ; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
1352 ; CHECK-NEXT: li a0, 134
1353 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t
1354 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
1355 ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
1356 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
1357 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
1358 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
1359 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
1360 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1361 ; CHECK-NEXT: ret
1362 ;
1363 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i8:
1364 ; CHECK-ZVBB: # %bb.0:
1365 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
1366 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1367 ; CHECK-ZVBB-NEXT: ret
1368 %v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
1369 ret <vscale x 1 x i8> %v
1370 }
1372 define <vscale x 1 x i8> @vp_ctlz_zero_undef_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {
1373 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i8_unmasked:
1374 ; CHECK: # %bb.0:
1375 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1376 ; CHECK-NEXT: vzext.vf2 v9, v8
1377 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
1378 ; CHECK-NEXT: vnsrl.wi v8, v8, 23
1379 ; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
1380 ; CHECK-NEXT: vnsrl.wi v8, v8, 0
1381 ; CHECK-NEXT: li a0, 134
1382 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1383 ; CHECK-NEXT: ret
1384 ;
1385 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i8_unmasked:
1386 ; CHECK-ZVBB: # %bb.0:
1387 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
1388 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1389 ; CHECK-ZVBB-NEXT: ret
1390 %v = call <vscale x 1 x i8> @llvm.vp.ctlz.nxv1i8(<vscale x 1 x i8> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)
1391 ret <vscale x 1 x i8> %v
1392 }
1395 define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1396 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i8:
1397 ; CHECK: # %bb.0:
1398 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
1399 ; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
1400 ; CHECK-NEXT: li a0, 134
1401 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9, v0.t
1402 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1403 ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
1404 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1405 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
1406 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
1407 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
1408 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1409 ; CHECK-NEXT: ret
1410 ;
1411 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i8:
1412 ; CHECK-ZVBB: # %bb.0:
1413 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
1414 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1415 ; CHECK-ZVBB-NEXT: ret
1416 %v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
1417 ret <vscale x 2 x i8> %v
1418 }
1420 define <vscale x 2 x i8> @vp_ctlz_zero_undef_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {
1421 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i8_unmasked:
1422 ; CHECK: # %bb.0:
1423 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
1424 ; CHECK-NEXT: vzext.vf2 v9, v8
1425 ; CHECK-NEXT: vfwcvt.f.xu.v v8, v9
1426 ; CHECK-NEXT: vnsrl.wi v8, v8, 23
1427 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
1428 ; CHECK-NEXT: vnsrl.wi v8, v8, 0
1429 ; CHECK-NEXT: li a0, 134
1430 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1431 ; CHECK-NEXT: ret
1432 ;
1433 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i8_unmasked:
1434 ; CHECK-ZVBB: # %bb.0:
1435 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
1436 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1437 ; CHECK-ZVBB-NEXT: ret
1438 %v = call <vscale x 2 x i8> @llvm.vp.ctlz.nxv2i8(<vscale x 2 x i8> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)
1439 ret <vscale x 2 x i8> %v
1440 }
1443 define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1444 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i8:
1445 ; CHECK: # %bb.0:
1446 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
1447 ; CHECK-NEXT: vzext.vf2 v9, v8, v0.t
1448 ; CHECK-NEXT: li a0, 134
1449 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v9, v0.t
1450 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1451 ; CHECK-NEXT: vsrl.vi v8, v10, 23, v0.t
1452 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1453 ; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
1454 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
1455 ; CHECK-NEXT: vnsrl.wi v8, v10, 0, v0.t
1456 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1457 ; CHECK-NEXT: ret
1458 ;
1459 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i8:
1460 ; CHECK-ZVBB: # %bb.0:
1461 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
1462 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1463 ; CHECK-ZVBB-NEXT: ret
1464 %v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
1465 ret <vscale x 4 x i8> %v
1466 }
1468 define <vscale x 4 x i8> @vp_ctlz_zero_undef_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {
1469 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i8_unmasked:
1470 ; CHECK: # %bb.0:
1471 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
1472 ; CHECK-NEXT: vzext.vf2 v9, v8
1473 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v9
1474 ; CHECK-NEXT: vnsrl.wi v8, v10, 23
1475 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
1476 ; CHECK-NEXT: vnsrl.wi v8, v8, 0
1477 ; CHECK-NEXT: li a0, 134
1478 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1479 ; CHECK-NEXT: ret
1480 ;
1481 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i8_unmasked:
1482 ; CHECK-ZVBB: # %bb.0:
1483 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
1484 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1485 ; CHECK-ZVBB-NEXT: ret
1486 %v = call <vscale x 4 x i8> @llvm.vp.ctlz.nxv4i8(<vscale x 4 x i8> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)
1487 ret <vscale x 4 x i8> %v
1488 }
1491 define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1492 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i8:
1493 ; CHECK: # %bb.0:
1494 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
1495 ; CHECK-NEXT: vzext.vf2 v10, v8, v0.t
1496 ; CHECK-NEXT: li a0, 134
1497 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v10, v0.t
1498 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1499 ; CHECK-NEXT: vsrl.vi v8, v12, 23, v0.t
1500 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
1501 ; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
1502 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
1503 ; CHECK-NEXT: vnsrl.wi v8, v12, 0, v0.t
1504 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1505 ; CHECK-NEXT: ret
1506 ;
1507 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i8:
1508 ; CHECK-ZVBB: # %bb.0:
1509 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
1510 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1511 ; CHECK-ZVBB-NEXT: ret
1512 %v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
1513 ret <vscale x 8 x i8> %v
1514 }
1516 define <vscale x 8 x i8> @vp_ctlz_zero_undef_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {
1517 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i8_unmasked:
1518 ; CHECK: # %bb.0:
1519 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
1520 ; CHECK-NEXT: vzext.vf2 v10, v8
1521 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v10
1522 ; CHECK-NEXT: vnsrl.wi v8, v12, 23
1523 ; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
1524 ; CHECK-NEXT: vnsrl.wi v10, v8, 0
1525 ; CHECK-NEXT: li a0, 134
1526 ; CHECK-NEXT: vrsub.vx v8, v10, a0
1527 ; CHECK-NEXT: ret
1528 ;
1529 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i8_unmasked:
1530 ; CHECK-ZVBB: # %bb.0:
1531 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m1, ta, ma
1532 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1533 ; CHECK-ZVBB-NEXT: ret
1534 %v = call <vscale x 8 x i8> @llvm.vp.ctlz.nxv8i8(<vscale x 8 x i8> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)
1535 ret <vscale x 8 x i8> %v
1536 }
1539 define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
1540 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i8:
1541 ; CHECK: # %bb.0:
1542 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
1543 ; CHECK-NEXT: vzext.vf2 v12, v8, v0.t
1544 ; CHECK-NEXT: li a0, 134
1545 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v12, v0.t
1546 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
1547 ; CHECK-NEXT: vsrl.vi v8, v16, 23, v0.t
1548 ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
1549 ; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
1550 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
1551 ; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
1552 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1553 ; CHECK-NEXT: ret
1554 ;
1555 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i8:
1556 ; CHECK-ZVBB: # %bb.0:
1557 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
1558 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1559 ; CHECK-ZVBB-NEXT: ret
1560 %v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
1561 ret <vscale x 16 x i8> %v
1562 }
1564 define <vscale x 16 x i8> @vp_ctlz_zero_undef_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {
1565 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i8_unmasked:
1566 ; CHECK: # %bb.0:
1567 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
1568 ; CHECK-NEXT: vzext.vf2 v12, v8
1569 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v12
1570 ; CHECK-NEXT: vnsrl.wi v8, v16, 23
1571 ; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
1572 ; CHECK-NEXT: vnsrl.wi v12, v8, 0
1573 ; CHECK-NEXT: li a0, 134
1574 ; CHECK-NEXT: vrsub.vx v8, v12, a0
1575 ; CHECK-NEXT: ret
1576 ;
1577 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i8_unmasked:
1578 ; CHECK-ZVBB: # %bb.0:
1579 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
1580 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1581 ; CHECK-ZVBB-NEXT: ret
1582 %v = call <vscale x 16 x i8> @llvm.vp.ctlz.nxv16i8(<vscale x 16 x i8> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)
1583 ret <vscale x 16 x i8> %v
1584 }
1587 define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
1588 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i8:
1589 ; CHECK: # %bb.0:
1590 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
1591 ; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
1592 ; CHECK-NEXT: li a0, 85
1593 ; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
1594 ; CHECK-NEXT: vsrl.vi v12, v8, 2, v0.t
1595 ; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
1596 ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
1597 ; CHECK-NEXT: vor.vv v8, v8, v12, v0.t
1598 ; CHECK-NEXT: vnot.v v8, v8, v0.t
1599 ; CHECK-NEXT: vsrl.vi v12, v8, 1, v0.t
1600 ; CHECK-NEXT: vand.vx v12, v12, a0, v0.t
1601 ; CHECK-NEXT: li a0, 51
1602 ; CHECK-NEXT: vsub.vv v8, v8, v12, v0.t
1603 ; CHECK-NEXT: vand.vx v12, v8, a0, v0.t
1604 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
1605 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1606 ; CHECK-NEXT: vadd.vv v8, v12, v8, v0.t
1607 ; CHECK-NEXT: vsrl.vi v12, v8, 4, v0.t
1608 ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
1609 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
1610 ; CHECK-NEXT: ret
1611 ;
1612 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv32i8:
1613 ; CHECK-ZVBB: # %bb.0:
1614 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
1615 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1616 ; CHECK-ZVBB-NEXT: ret
1617 %v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
1618 ret <vscale x 32 x i8> %v
1619 }
1621 define <vscale x 32 x i8> @vp_ctlz_zero_undef_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {
1622 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i8_unmasked:
1623 ; CHECK: # %bb.0:
1624 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
1625 ; CHECK-NEXT: vsrl.vi v12, v8, 1
1626 ; CHECK-NEXT: li a0, 85
1627 ; CHECK-NEXT: vor.vv v8, v8, v12
1628 ; CHECK-NEXT: vsrl.vi v12, v8, 2
1629 ; CHECK-NEXT: vor.vv v8, v8, v12
1630 ; CHECK-NEXT: vsrl.vi v12, v8, 4
1631 ; CHECK-NEXT: vor.vv v8, v8, v12
1632 ; CHECK-NEXT: vnot.v v8, v8
1633 ; CHECK-NEXT: vsrl.vi v12, v8, 1
1634 ; CHECK-NEXT: vand.vx v12, v12, a0
1635 ; CHECK-NEXT: li a0, 51
1636 ; CHECK-NEXT: vsub.vv v8, v8, v12
1637 ; CHECK-NEXT: vand.vx v12, v8, a0
1638 ; CHECK-NEXT: vsrl.vi v8, v8, 2
1639 ; CHECK-NEXT: vand.vx v8, v8, a0
1640 ; CHECK-NEXT: vadd.vv v8, v12, v8
1641 ; CHECK-NEXT: vsrl.vi v12, v8, 4
1642 ; CHECK-NEXT: vadd.vv v8, v8, v12
1643 ; CHECK-NEXT: vand.vi v8, v8, 15
1644 ; CHECK-NEXT: ret
1645 ;
1646 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv32i8_unmasked:
1647 ; CHECK-ZVBB: # %bb.0:
1648 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
1649 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1650 ; CHECK-ZVBB-NEXT: ret
1651 %v = call <vscale x 32 x i8> @llvm.vp.ctlz.nxv32i8(<vscale x 32 x i8> %va, i1 true, <vscale x 32 x i1> splat (i1 true), i32 %evl)
1652 ret <vscale x 32 x i8> %v
1653 }
1656 define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {
1657 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv64i8:
1658 ; CHECK: # %bb.0:
1659 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
1660 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
1661 ; CHECK-NEXT: li a0, 85
1662 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
1663 ; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t
1664 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
1665 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
1666 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
1667 ; CHECK-NEXT: vnot.v v8, v8, v0.t
1668 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
1669 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
1670 ; CHECK-NEXT: li a0, 51
1671 ; CHECK-NEXT: vsub.vv v8, v8, v16, v0.t
1672 ; CHECK-NEXT: vand.vx v16, v8, a0, v0.t
1673 ; CHECK-NEXT: vsrl.vi v8, v8, 2, v0.t
1674 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1675 ; CHECK-NEXT: vadd.vv v8, v16, v8, v0.t
1676 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
1677 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
1678 ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t
1679 ; CHECK-NEXT: ret
1680 ;
1681 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv64i8:
1682 ; CHECK-ZVBB: # %bb.0:
1683 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma
1684 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1685 ; CHECK-ZVBB-NEXT: ret
1686 %v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> %m, i32 %evl)
1687 ret <vscale x 64 x i8> %v
1688 }
1690 define <vscale x 64 x i8> @vp_ctlz_zero_undef_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {
1691 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv64i8_unmasked:
1692 ; CHECK: # %bb.0:
1693 ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
1694 ; CHECK-NEXT: vsrl.vi v16, v8, 1
1695 ; CHECK-NEXT: li a0, 85
1696 ; CHECK-NEXT: vor.vv v8, v8, v16
1697 ; CHECK-NEXT: vsrl.vi v16, v8, 2
1698 ; CHECK-NEXT: vor.vv v8, v8, v16
1699 ; CHECK-NEXT: vsrl.vi v16, v8, 4
1700 ; CHECK-NEXT: vor.vv v8, v8, v16
1701 ; CHECK-NEXT: vnot.v v8, v8
1702 ; CHECK-NEXT: vsrl.vi v16, v8, 1
1703 ; CHECK-NEXT: vand.vx v16, v16, a0
1704 ; CHECK-NEXT: li a0, 51
1705 ; CHECK-NEXT: vsub.vv v8, v8, v16
1706 ; CHECK-NEXT: vand.vx v16, v8, a0
1707 ; CHECK-NEXT: vsrl.vi v8, v8, 2
1708 ; CHECK-NEXT: vand.vx v8, v8, a0
1709 ; CHECK-NEXT: vadd.vv v8, v16, v8
1710 ; CHECK-NEXT: vsrl.vi v16, v8, 4
1711 ; CHECK-NEXT: vadd.vv v8, v8, v16
1712 ; CHECK-NEXT: vand.vi v8, v8, 15
1713 ; CHECK-NEXT: ret
1714 ;
1715 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv64i8_unmasked:
1716 ; CHECK-ZVBB: # %bb.0:
1717 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e8, m8, ta, ma
1718 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1719 ; CHECK-ZVBB-NEXT: ret
1720 %v = call <vscale x 64 x i8> @llvm.vp.ctlz.nxv64i8(<vscale x 64 x i8> %va, i1 true, <vscale x 64 x i1> splat (i1 true), i32 %evl)
1721 ret <vscale x 64 x i8> %v
1722 }
1725 define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
1726 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i16:
1727 ; CHECK: # %bb.0:
1728 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1729 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
1730 ; CHECK-NEXT: li a0, 142
1731 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
1732 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
1733 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
1734 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
1735 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1736 ; CHECK-NEXT: ret
1737 ;
1738 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i16:
1739 ; CHECK-ZVBB: # %bb.0:
1740 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1741 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1742 ; CHECK-ZVBB-NEXT: ret
1743 %v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
1744 ret <vscale x 1 x i16> %v
1745 }
1747 define <vscale x 1 x i16> @vp_ctlz_zero_undef_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {
1748 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i16_unmasked:
1749 ; CHECK: # %bb.0:
1750 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1751 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
1752 ; CHECK-NEXT: vnsrl.wi v8, v9, 23
1753 ; CHECK-NEXT: li a0, 142
1754 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1755 ; CHECK-NEXT: ret
1756 ;
1757 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i16_unmasked:
1758 ; CHECK-ZVBB: # %bb.0:
1759 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
1760 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1761 ; CHECK-ZVBB-NEXT: ret
1762 %v = call <vscale x 1 x i16> @llvm.vp.ctlz.nxv1i16(<vscale x 1 x i16> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)
1763 ret <vscale x 1 x i16> %v
1764 }
1767 define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
1768 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i16:
1769 ; CHECK: # %bb.0:
1770 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
1771 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
1772 ; CHECK-NEXT: li a0, 142
1773 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1774 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
1775 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1776 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
1777 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
1778 ; CHECK-NEXT: ret
1779 ;
1780 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i16:
1781 ; CHECK-ZVBB: # %bb.0:
1782 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
1783 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1784 ; CHECK-ZVBB-NEXT: ret
1785 %v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
1786 ret <vscale x 2 x i16> %v
1787 }
1789 define <vscale x 2 x i16> @vp_ctlz_zero_undef_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {
1790 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i16_unmasked:
1791 ; CHECK: # %bb.0:
1792 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
1793 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
1794 ; CHECK-NEXT: vnsrl.wi v8, v9, 23
1795 ; CHECK-NEXT: li a0, 142
1796 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1797 ; CHECK-NEXT: ret
1798 ;
1799 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i16_unmasked:
1800 ; CHECK-ZVBB: # %bb.0:
1801 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
1802 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1803 ; CHECK-ZVBB-NEXT: ret
1804 %v = call <vscale x 2 x i16> @llvm.vp.ctlz.nxv2i16(<vscale x 2 x i16> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)
1805 ret <vscale x 2 x i16> %v
1806 }
1809 define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
1810 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i16:
1811 ; CHECK: # %bb.0:
1812 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
1813 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8, v0.t
1814 ; CHECK-NEXT: li a0, 142
1815 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1816 ; CHECK-NEXT: vsrl.vi v8, v10, 23, v0.t
1817 ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1818 ; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
1819 ; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t
1820 ; CHECK-NEXT: ret
1821 ;
1822 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i16:
1823 ; CHECK-ZVBB: # %bb.0:
1824 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
1825 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1826 ; CHECK-ZVBB-NEXT: ret
1827 %v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
1828 ret <vscale x 4 x i16> %v
1829 }
1831 define <vscale x 4 x i16> @vp_ctlz_zero_undef_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {
1832 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i16_unmasked:
1833 ; CHECK: # %bb.0:
1834 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
1835 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
1836 ; CHECK-NEXT: vnsrl.wi v8, v10, 23
1837 ; CHECK-NEXT: li a0, 142
1838 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1839 ; CHECK-NEXT: ret
1840 ;
1841 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i16_unmasked:
1842 ; CHECK-ZVBB: # %bb.0:
1843 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m1, ta, ma
1844 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1845 ; CHECK-ZVBB-NEXT: ret
1846 %v = call <vscale x 4 x i16> @llvm.vp.ctlz.nxv4i16(<vscale x 4 x i16> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)
1847 ret <vscale x 4 x i16> %v
1848 }
1851 define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
1852 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i16:
1853 ; CHECK: # %bb.0:
1854 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
1855 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8, v0.t
1856 ; CHECK-NEXT: li a0, 142
1857 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1858 ; CHECK-NEXT: vsrl.vi v8, v12, 23, v0.t
1859 ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
1860 ; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
1861 ; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t
1862 ; CHECK-NEXT: ret
1863 ;
1864 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i16:
1865 ; CHECK-ZVBB: # %bb.0:
1866 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
1867 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1868 ; CHECK-ZVBB-NEXT: ret
1869 %v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
1870 ret <vscale x 8 x i16> %v
1871 }
1873 define <vscale x 8 x i16> @vp_ctlz_zero_undef_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {
1874 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i16_unmasked:
1875 ; CHECK: # %bb.0:
1876 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
1877 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
1878 ; CHECK-NEXT: vnsrl.wi v8, v12, 23
1879 ; CHECK-NEXT: li a0, 142
1880 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1881 ; CHECK-NEXT: ret
1882 ;
1883 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i16_unmasked:
1884 ; CHECK-ZVBB: # %bb.0:
1885 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m2, ta, ma
1886 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1887 ; CHECK-ZVBB-NEXT: ret
1888 %v = call <vscale x 8 x i16> @llvm.vp.ctlz.nxv8i16(<vscale x 8 x i16> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)
1889 ret <vscale x 8 x i16> %v
1890 }
1893 define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
1894 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i16:
1895 ; CHECK: # %bb.0:
1896 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
1897 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8, v0.t
1898 ; CHECK-NEXT: li a0, 142
1899 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
1900 ; CHECK-NEXT: vsrl.vi v8, v16, 23, v0.t
1901 ; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
1902 ; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
1903 ; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t
1904 ; CHECK-NEXT: ret
1905 ;
1906 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i16:
1907 ; CHECK-ZVBB: # %bb.0:
1908 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
1909 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1910 ; CHECK-ZVBB-NEXT: ret
1911 %v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
1912 ret <vscale x 16 x i16> %v
1913 }
1915 define <vscale x 16 x i16> @vp_ctlz_zero_undef_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {
1916 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i16_unmasked:
1917 ; CHECK: # %bb.0:
1918 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
1919 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
1920 ; CHECK-NEXT: vnsrl.wi v8, v16, 23
1921 ; CHECK-NEXT: li a0, 142
1922 ; CHECK-NEXT: vrsub.vx v8, v8, a0
1923 ; CHECK-NEXT: ret
1924 ;
1925 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i16_unmasked:
1926 ; CHECK-ZVBB: # %bb.0:
1927 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m4, ta, ma
1928 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
1929 ; CHECK-ZVBB-NEXT: ret
1930 %v = call <vscale x 16 x i16> @llvm.vp.ctlz.nxv16i16(<vscale x 16 x i16> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)
1931 ret <vscale x 16 x i16> %v
1932 }
1935 define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
1936 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i16:
1937 ; CHECK: # %bb.0:
1938 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
1939 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
1940 ; CHECK-NEXT: lui a0, 5
1941 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
1942 ; CHECK-NEXT: addi a0, a0, 1365
1943 ; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t
1944 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
1945 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
1946 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
1947 ; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
1948 ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
1949 ; CHECK-NEXT: vnot.v v8, v8, v0.t
1950 ; CHECK-NEXT: vsrl.vi v16, v8, 1, v0.t
1951 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
1952 ; CHECK-NEXT: lui a0, 3
1953 ; CHECK-NEXT: addi a0, a0, 819
1954 ; CHECK-NEXT: vsub.vv v16, v8, v16, v0.t
1955 ; CHECK-NEXT: vand.vx v8, v16, a0, v0.t
1956 ; CHECK-NEXT: vsrl.vi v16, v16, 2, v0.t
1957 ; CHECK-NEXT: vand.vx v16, v16, a0, v0.t
1958 ; CHECK-NEXT: lui a0, 1
1959 ; CHECK-NEXT: addi a0, a0, -241
1960 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
1961 ; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
1962 ; CHECK-NEXT: vadd.vv v8, v8, v16, v0.t
1963 ; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
1964 ; CHECK-NEXT: li a0, 257
1965 ; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
1966 ; CHECK-NEXT: vsrl.vi v8, v8, 8, v0.t
1967 ; CHECK-NEXT: ret
1968 ;
1969 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv32i16:
1970 ; CHECK-ZVBB: # %bb.0:
1971 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
1972 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
1973 ; CHECK-ZVBB-NEXT: ret
1974 %v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> %m, i32 %evl)
1975 ret <vscale x 32 x i16> %v
1976 }
1978 define <vscale x 32 x i16> @vp_ctlz_zero_undef_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {
1979 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv32i16_unmasked:
1980 ; CHECK: # %bb.0:
1981 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
1982 ; CHECK-NEXT: vsrl.vi v16, v8, 1
1983 ; CHECK-NEXT: lui a0, 5
1984 ; CHECK-NEXT: vor.vv v8, v8, v16
1985 ; CHECK-NEXT: addi a0, a0, 1365
1986 ; CHECK-NEXT: vsrl.vi v16, v8, 2
1987 ; CHECK-NEXT: vor.vv v8, v8, v16
1988 ; CHECK-NEXT: vsrl.vi v16, v8, 4
1989 ; CHECK-NEXT: vor.vv v8, v8, v16
1990 ; CHECK-NEXT: vsrl.vi v16, v8, 8
1991 ; CHECK-NEXT: vor.vv v8, v8, v16
1992 ; CHECK-NEXT: vnot.v v8, v8
1993 ; CHECK-NEXT: vsrl.vi v16, v8, 1
1994 ; CHECK-NEXT: vand.vx v16, v16, a0
1995 ; CHECK-NEXT: lui a0, 3
1996 ; CHECK-NEXT: addi a0, a0, 819
1997 ; CHECK-NEXT: vsub.vv v8, v8, v16
1998 ; CHECK-NEXT: vand.vx v16, v8, a0
1999 ; CHECK-NEXT: vsrl.vi v8, v8, 2
2000 ; CHECK-NEXT: vand.vx v8, v8, a0
2001 ; CHECK-NEXT: lui a0, 1
2002 ; CHECK-NEXT: addi a0, a0, -241
2003 ; CHECK-NEXT: vadd.vv v8, v16, v8
2004 ; CHECK-NEXT: vsrl.vi v16, v8, 4
2005 ; CHECK-NEXT: vadd.vv v8, v8, v16
2006 ; CHECK-NEXT: vand.vx v8, v8, a0
2007 ; CHECK-NEXT: li a0, 257
2008 ; CHECK-NEXT: vmul.vx v8, v8, a0
2009 ; CHECK-NEXT: vsrl.vi v8, v8, 8
2010 ; CHECK-NEXT: ret
2011 ;
2012 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv32i16_unmasked:
2013 ; CHECK-ZVBB: # %bb.0:
2014 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, m8, ta, ma
2015 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2016 ; CHECK-ZVBB-NEXT: ret
2017 %v = call <vscale x 32 x i16> @llvm.vp.ctlz.nxv32i16(<vscale x 32 x i16> %va, i1 true, <vscale x 32 x i1> splat (i1 true), i32 %evl)
2018 ret <vscale x 32 x i16> %v
2019 }
2022 define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2023 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i32:
2024 ; CHECK: # %bb.0:
2025 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
2026 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2027 ; CHECK-NEXT: li a0, 52
2028 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
2029 ; CHECK-NEXT: vsrl.vx v8, v9, a0, v0.t
2030 ; CHECK-NEXT: li a0, 1054
2031 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2032 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2033 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2034 ; CHECK-NEXT: ret
2035 ;
2036 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i32:
2037 ; CHECK-ZVBB: # %bb.0:
2038 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
2039 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2040 ; CHECK-ZVBB-NEXT: ret
2041 %v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
2042 ret <vscale x 1 x i32> %v
2043 }
2045 define <vscale x 1 x i32> @vp_ctlz_zero_undef_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {
2046 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i32_unmasked:
2047 ; CHECK: # %bb.0:
2048 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
2049 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
2050 ; CHECK-NEXT: li a0, 52
2051 ; CHECK-NEXT: vnsrl.wx v8, v9, a0
2052 ; CHECK-NEXT: li a0, 1054
2053 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2054 ; CHECK-NEXT: ret
2055 ;
2056 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i32_unmasked:
2057 ; CHECK-ZVBB: # %bb.0:
2058 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
2059 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2060 ; CHECK-ZVBB-NEXT: ret
2061 %v = call <vscale x 1 x i32> @llvm.vp.ctlz.nxv1i32(<vscale x 1 x i32> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)
2062 ret <vscale x 1 x i32> %v
2063 }
2066 define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
2067 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i32:
2068 ; CHECK: # %bb.0:
2069 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
2070 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8, v0.t
2071 ; CHECK-NEXT: li a0, 52
2072 ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
2073 ; CHECK-NEXT: vsrl.vx v8, v10, a0, v0.t
2074 ; CHECK-NEXT: li a0, 1054
2075 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
2076 ; CHECK-NEXT: vnsrl.wi v10, v8, 0, v0.t
2077 ; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t
2078 ; CHECK-NEXT: ret
2079 ;
2080 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i32:
2081 ; CHECK-ZVBB: # %bb.0:
2082 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
2083 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2084 ; CHECK-ZVBB-NEXT: ret
2085 %v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
2086 ret <vscale x 2 x i32> %v
2087 }
2089 define <vscale x 2 x i32> @vp_ctlz_zero_undef_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {
2090 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i32_unmasked:
2091 ; CHECK: # %bb.0:
2092 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
2093 ; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
2094 ; CHECK-NEXT: li a0, 52
2095 ; CHECK-NEXT: vnsrl.wx v8, v10, a0
2096 ; CHECK-NEXT: li a0, 1054
2097 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2098 ; CHECK-NEXT: ret
2099 ;
2100 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i32_unmasked:
2101 ; CHECK-ZVBB: # %bb.0:
2102 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m1, ta, ma
2103 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2104 ; CHECK-ZVBB-NEXT: ret
2105 %v = call <vscale x 2 x i32> @llvm.vp.ctlz.nxv2i32(<vscale x 2 x i32> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)
2106 ret <vscale x 2 x i32> %v
2107 }
2110 define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
2111 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i32:
2112 ; CHECK: # %bb.0:
2113 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
2114 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8, v0.t
2115 ; CHECK-NEXT: li a0, 52
2116 ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
2117 ; CHECK-NEXT: vsrl.vx v8, v12, a0, v0.t
2118 ; CHECK-NEXT: li a0, 1054
2119 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
2120 ; CHECK-NEXT: vnsrl.wi v12, v8, 0, v0.t
2121 ; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t
2122 ; CHECK-NEXT: ret
2123 ;
2124 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i32:
2125 ; CHECK-ZVBB: # %bb.0:
2126 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
2127 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2128 ; CHECK-ZVBB-NEXT: ret
2129 %v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
2130 ret <vscale x 4 x i32> %v
2131 }
2133 define <vscale x 4 x i32> @vp_ctlz_zero_undef_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {
2134 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i32_unmasked:
2135 ; CHECK: # %bb.0:
2136 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
2137 ; CHECK-NEXT: vfwcvt.f.xu.v v12, v8
2138 ; CHECK-NEXT: li a0, 52
2139 ; CHECK-NEXT: vnsrl.wx v8, v12, a0
2140 ; CHECK-NEXT: li a0, 1054
2141 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2142 ; CHECK-NEXT: ret
2143 ;
2144 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i32_unmasked:
2145 ; CHECK-ZVBB: # %bb.0:
2146 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m2, ta, ma
2147 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2148 ; CHECK-ZVBB-NEXT: ret
2149 %v = call <vscale x 4 x i32> @llvm.vp.ctlz.nxv4i32(<vscale x 4 x i32> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)
2150 ret <vscale x 4 x i32> %v
2151 }
2154 define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
2155 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i32:
2156 ; CHECK: # %bb.0:
2157 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
2158 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8, v0.t
2159 ; CHECK-NEXT: li a0, 52
2160 ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
2161 ; CHECK-NEXT: vsrl.vx v8, v16, a0, v0.t
2162 ; CHECK-NEXT: li a0, 1054
2163 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
2164 ; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
2165 ; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t
2166 ; CHECK-NEXT: ret
2167 ;
2168 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i32:
2169 ; CHECK-ZVBB: # %bb.0:
2170 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
2171 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2172 ; CHECK-ZVBB-NEXT: ret
2173 %v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
2174 ret <vscale x 8 x i32> %v
2175 }
2177 define <vscale x 8 x i32> @vp_ctlz_zero_undef_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {
2178 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i32_unmasked:
2179 ; CHECK: # %bb.0:
2180 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
2181 ; CHECK-NEXT: vfwcvt.f.xu.v v16, v8
2182 ; CHECK-NEXT: li a0, 52
2183 ; CHECK-NEXT: vnsrl.wx v8, v16, a0
2184 ; CHECK-NEXT: li a0, 1054
2185 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2186 ; CHECK-NEXT: ret
2187 ;
2188 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i32_unmasked:
2189 ; CHECK-ZVBB: # %bb.0:
2190 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m4, ta, ma
2191 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2192 ; CHECK-ZVBB-NEXT: ret
2193 %v = call <vscale x 8 x i32> @llvm.vp.ctlz.nxv8i32(<vscale x 8 x i32> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)
2194 ret <vscale x 8 x i32> %v
2195 }
2198 define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
2199 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i32:
2200 ; CHECK: # %bb.0:
2201 ; CHECK-NEXT: fsrmi a1, 1
2202 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
2203 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
2204 ; CHECK-NEXT: li a0, 158
2205 ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t
2206 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2207 ; CHECK-NEXT: fsrm a1
2208 ; CHECK-NEXT: ret
2209 ;
2210 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i32:
2211 ; CHECK-ZVBB: # %bb.0:
2212 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
2213 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2214 ; CHECK-ZVBB-NEXT: ret
2215 %v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
2216 ret <vscale x 16 x i32> %v
2217 }
2219 define <vscale x 16 x i32> @vp_ctlz_zero_undef_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {
2220 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i32_unmasked:
2221 ; CHECK: # %bb.0:
2222 ; CHECK-NEXT: fsrmi a1, 1
2223 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
2224 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
2225 ; CHECK-NEXT: vsrl.vi v8, v8, 23
2226 ; CHECK-NEXT: li a0, 158
2227 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2228 ; CHECK-NEXT: fsrm a1
2229 ; CHECK-NEXT: ret
2230 ;
2231 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i32_unmasked:
2232 ; CHECK-ZVBB: # %bb.0:
2233 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e32, m8, ta, ma
2234 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2235 ; CHECK-ZVBB-NEXT: ret
2236 %v = call <vscale x 16 x i32> @llvm.vp.ctlz.nxv16i32(<vscale x 16 x i32> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)
2237 ret <vscale x 16 x i32> %v
2238 }
2241 define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2242 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i64:
2243 ; CHECK: # %bb.0:
2244 ; CHECK-NEXT: fsrmi a1, 1
2245 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
2246 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
2247 ; CHECK-NEXT: li a0, 52
2248 ; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
2249 ; CHECK-NEXT: li a0, 1086
2250 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2251 ; CHECK-NEXT: fsrm a1
2252 ; CHECK-NEXT: ret
2253 ;
2254 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i64:
2255 ; CHECK-ZVBB: # %bb.0:
2256 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
2257 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2258 ; CHECK-ZVBB-NEXT: ret
2259 %v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
2260 ret <vscale x 1 x i64> %v
2261 }
2263 define <vscale x 1 x i64> @vp_ctlz_zero_undef_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {
2264 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i64_unmasked:
2265 ; CHECK: # %bb.0:
2266 ; CHECK-NEXT: fsrmi a1, 1
2267 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
2268 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
2269 ; CHECK-NEXT: li a0, 52
2270 ; CHECK-NEXT: vsrl.vx v8, v8, a0
2271 ; CHECK-NEXT: li a0, 1086
2272 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2273 ; CHECK-NEXT: fsrm a1
2274 ; CHECK-NEXT: ret
2275 ;
2276 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i64_unmasked:
2277 ; CHECK-ZVBB: # %bb.0:
2278 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m1, ta, ma
2279 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2280 ; CHECK-ZVBB-NEXT: ret
2281 %v = call <vscale x 1 x i64> @llvm.vp.ctlz.nxv1i64(<vscale x 1 x i64> %va, i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)
2282 ret <vscale x 1 x i64> %v
2283 }
2286 define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
2287 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i64:
2288 ; CHECK: # %bb.0:
2289 ; CHECK-NEXT: fsrmi a1, 1
2290 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
2291 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
2292 ; CHECK-NEXT: li a0, 52
2293 ; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
2294 ; CHECK-NEXT: li a0, 1086
2295 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2296 ; CHECK-NEXT: fsrm a1
2297 ; CHECK-NEXT: ret
2298 ;
2299 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i64:
2300 ; CHECK-ZVBB: # %bb.0:
2301 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
2302 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2303 ; CHECK-ZVBB-NEXT: ret
2304 %v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> %m, i32 %evl)
2305 ret <vscale x 2 x i64> %v
2306 }
2308 define <vscale x 2 x i64> @vp_ctlz_zero_undef_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {
2309 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i64_unmasked:
2310 ; CHECK: # %bb.0:
2311 ; CHECK-NEXT: fsrmi a1, 1
2312 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
2313 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
2314 ; CHECK-NEXT: li a0, 52
2315 ; CHECK-NEXT: vsrl.vx v8, v8, a0
2316 ; CHECK-NEXT: li a0, 1086
2317 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2318 ; CHECK-NEXT: fsrm a1
2319 ; CHECK-NEXT: ret
2320 ;
2321 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i64_unmasked:
2322 ; CHECK-ZVBB: # %bb.0:
2323 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m2, ta, ma
2324 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2325 ; CHECK-ZVBB-NEXT: ret
2326 %v = call <vscale x 2 x i64> @llvm.vp.ctlz.nxv2i64(<vscale x 2 x i64> %va, i1 true, <vscale x 2 x i1> splat (i1 true), i32 %evl)
2327 ret <vscale x 2 x i64> %v
2328 }
2331 define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
2332 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i64:
2333 ; CHECK: # %bb.0:
2334 ; CHECK-NEXT: fsrmi a1, 1
2335 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
2336 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
2337 ; CHECK-NEXT: li a0, 52
2338 ; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
2339 ; CHECK-NEXT: li a0, 1086
2340 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2341 ; CHECK-NEXT: fsrm a1
2342 ; CHECK-NEXT: ret
2343 ;
2344 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i64:
2345 ; CHECK-ZVBB: # %bb.0:
2346 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
2347 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2348 ; CHECK-ZVBB-NEXT: ret
2349 %v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> %m, i32 %evl)
2350 ret <vscale x 4 x i64> %v
2351 }
2353 define <vscale x 4 x i64> @vp_ctlz_zero_undef_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {
2354 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i64_unmasked:
2355 ; CHECK: # %bb.0:
2356 ; CHECK-NEXT: fsrmi a1, 1
2357 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
2358 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
2359 ; CHECK-NEXT: li a0, 52
2360 ; CHECK-NEXT: vsrl.vx v8, v8, a0
2361 ; CHECK-NEXT: li a0, 1086
2362 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2363 ; CHECK-NEXT: fsrm a1
2364 ; CHECK-NEXT: ret
2365 ;
2366 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i64_unmasked:
2367 ; CHECK-ZVBB: # %bb.0:
2368 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m4, ta, ma
2369 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2370 ; CHECK-ZVBB-NEXT: ret
2371 %v = call <vscale x 4 x i64> @llvm.vp.ctlz.nxv4i64(<vscale x 4 x i64> %va, i1 true, <vscale x 4 x i1> splat (i1 true), i32 %evl)
2372 ret <vscale x 4 x i64> %v
2373 }
2376 define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64(<vscale x 7 x i64> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
2377 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv7i64:
2378 ; CHECK: # %bb.0:
2379 ; CHECK-NEXT: fsrmi a1, 1
2380 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2381 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
2382 ; CHECK-NEXT: li a0, 52
2383 ; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
2384 ; CHECK-NEXT: li a0, 1086
2385 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2386 ; CHECK-NEXT: fsrm a1
2387 ; CHECK-NEXT: ret
2388 ;
2389 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv7i64:
2390 ; CHECK-ZVBB: # %bb.0:
2391 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2392 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2393 ; CHECK-ZVBB-NEXT: ret
2394 %v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> %m, i32 %evl)
2395 ret <vscale x 7 x i64> %v
2396 }
2398 define <vscale x 7 x i64> @vp_ctlz_zero_undef_nxv7i64_unmasked(<vscale x 7 x i64> %va, i32 zeroext %evl) {
2399 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv7i64_unmasked:
2400 ; CHECK: # %bb.0:
2401 ; CHECK-NEXT: fsrmi a1, 1
2402 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2403 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
2404 ; CHECK-NEXT: li a0, 52
2405 ; CHECK-NEXT: vsrl.vx v8, v8, a0
2406 ; CHECK-NEXT: li a0, 1086
2407 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2408 ; CHECK-NEXT: fsrm a1
2409 ; CHECK-NEXT: ret
2410 ;
2411 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv7i64_unmasked:
2412 ; CHECK-ZVBB: # %bb.0:
2413 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2414 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2415 ; CHECK-ZVBB-NEXT: ret
2416 %v = call <vscale x 7 x i64> @llvm.vp.ctlz.nxv7i64(<vscale x 7 x i64> %va, i1 true, <vscale x 7 x i1> splat (i1 true), i32 %evl)
2417 ret <vscale x 7 x i64> %v
2418 }
2421 define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
2422 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i64:
2423 ; CHECK: # %bb.0:
2424 ; CHECK-NEXT: fsrmi a1, 1
2425 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2426 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
2427 ; CHECK-NEXT: li a0, 52
2428 ; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t
2429 ; CHECK-NEXT: li a0, 1086
2430 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2431 ; CHECK-NEXT: fsrm a1
2432 ; CHECK-NEXT: ret
2433 ;
2434 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i64:
2435 ; CHECK-ZVBB: # %bb.0:
2436 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2437 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2438 ; CHECK-ZVBB-NEXT: ret
2439 %v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> %m, i32 %evl)
2440 ret <vscale x 8 x i64> %v
2441 }
2443 define <vscale x 8 x i64> @vp_ctlz_zero_undef_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {
2444 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i64_unmasked:
2445 ; CHECK: # %bb.0:
2446 ; CHECK-NEXT: fsrmi a1, 1
2447 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2448 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
2449 ; CHECK-NEXT: li a0, 52
2450 ; CHECK-NEXT: vsrl.vx v8, v8, a0
2451 ; CHECK-NEXT: li a0, 1086
2452 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2453 ; CHECK-NEXT: fsrm a1
2454 ; CHECK-NEXT: ret
2455 ;
2456 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i64_unmasked:
2457 ; CHECK-ZVBB: # %bb.0:
2458 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2459 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2460 ; CHECK-ZVBB-NEXT: ret
2461 %v = call <vscale x 8 x i64> @llvm.vp.ctlz.nxv8i64(<vscale x 8 x i64> %va, i1 true, <vscale x 8 x i1> splat (i1 true), i32 %evl)
2462 ret <vscale x 8 x i64> %v
2463 }
2465 define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
2466 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i64:
2467 ; CHECK: # %bb.0:
2468 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
2469 ; CHECK-NEXT: vmv1r.v v24, v0
2470 ; CHECK-NEXT: csrr a1, vlenb
2471 ; CHECK-NEXT: fsrmi a3, 1
2472 ; CHECK-NEXT: srli a2, a1, 3
2473 ; CHECK-NEXT: sub a4, a0, a1
2474 ; CHECK-NEXT: vslidedown.vx v0, v0, a2
2475 ; CHECK-NEXT: sltu a2, a0, a4
2476 ; CHECK-NEXT: addi a2, a2, -1
2477 ; CHECK-NEXT: and a4, a2, a4
2478 ; CHECK-NEXT: li a2, 52
2479 ; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
2480 ; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
2481 ; CHECK-NEXT: fsrm a3
2482 ; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t
2483 ; CHECK-NEXT: li a3, 1086
2484 ; CHECK-NEXT: vrsub.vx v16, v16, a3, v0.t
2485 ; CHECK-NEXT: bltu a0, a1, .LBB94_2
2486 ; CHECK-NEXT: # %bb.1:
2487 ; CHECK-NEXT: mv a0, a1
2488 ; CHECK-NEXT: .LBB94_2:
2489 ; CHECK-NEXT: fsrmi a1, 1
2490 ; CHECK-NEXT: vmv1r.v v0, v24
2491 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2492 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
2493 ; CHECK-NEXT: vsrl.vx v8, v8, a2, v0.t
2494 ; CHECK-NEXT: vrsub.vx v8, v8, a3, v0.t
2495 ; CHECK-NEXT: fsrm a1
2496 ; CHECK-NEXT: ret
2497 ;
2498 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i64:
2499 ; CHECK-ZVBB: # %bb.0:
2500 ; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
2501 ; CHECK-ZVBB-NEXT: vmv1r.v v24, v0
2502 ; CHECK-ZVBB-NEXT: csrr a1, vlenb
2503 ; CHECK-ZVBB-NEXT: srli a2, a1, 3
2504 ; CHECK-ZVBB-NEXT: sub a3, a0, a1
2505 ; CHECK-ZVBB-NEXT: vslidedown.vx v0, v0, a2
2506 ; CHECK-ZVBB-NEXT: sltu a2, a0, a3
2507 ; CHECK-ZVBB-NEXT: addi a2, a2, -1
2508 ; CHECK-ZVBB-NEXT: and a2, a2, a3
2509 ; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
2510 ; CHECK-ZVBB-NEXT: vclz.v v16, v16, v0.t
2511 ; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB94_2
2512 ; CHECK-ZVBB-NEXT: # %bb.1:
2513 ; CHECK-ZVBB-NEXT: mv a0, a1
2514 ; CHECK-ZVBB-NEXT: .LBB94_2:
2515 ; CHECK-ZVBB-NEXT: vmv1r.v v0, v24
2516 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2517 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2518 ; CHECK-ZVBB-NEXT: ret
2519 %v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> %m, i32 %evl)
2520 ret <vscale x 16 x i64> %v
2521 }
2523 define <vscale x 16 x i64> @vp_ctlz_zero_undef_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
2524 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i64_unmasked:
2525 ; CHECK: # %bb.0:
2526 ; CHECK-NEXT: csrr a1, vlenb
2527 ; CHECK-NEXT: fsrmi a3, 1
2528 ; CHECK-NEXT: sub a2, a0, a1
2529 ; CHECK-NEXT: sltu a4, a0, a2
2530 ; CHECK-NEXT: addi a4, a4, -1
2531 ; CHECK-NEXT: and a4, a4, a2
2532 ; CHECK-NEXT: li a2, 52
2533 ; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
2534 ; CHECK-NEXT: vfcvt.f.xu.v v16, v16
2535 ; CHECK-NEXT: fsrm a3
2536 ; CHECK-NEXT: vsrl.vx v16, v16, a2
2537 ; CHECK-NEXT: li a3, 1086
2538 ; CHECK-NEXT: vrsub.vx v16, v16, a3
2539 ; CHECK-NEXT: bltu a0, a1, .LBB95_2
2540 ; CHECK-NEXT: # %bb.1:
2541 ; CHECK-NEXT: mv a0, a1
2542 ; CHECK-NEXT: .LBB95_2:
2543 ; CHECK-NEXT: fsrmi a1, 1
2544 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2545 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8
2546 ; CHECK-NEXT: vsrl.vx v8, v8, a2
2547 ; CHECK-NEXT: vrsub.vx v8, v8, a3
2548 ; CHECK-NEXT: fsrm a1
2549 ; CHECK-NEXT: ret
2550 ;
2551 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i64_unmasked:
2552 ; CHECK-ZVBB: # %bb.0:
2553 ; CHECK-ZVBB-NEXT: csrr a1, vlenb
2554 ; CHECK-ZVBB-NEXT: sub a2, a0, a1
2555 ; CHECK-ZVBB-NEXT: sltu a3, a0, a2
2556 ; CHECK-ZVBB-NEXT: addi a3, a3, -1
2557 ; CHECK-ZVBB-NEXT: and a2, a3, a2
2558 ; CHECK-ZVBB-NEXT: vsetvli zero, a2, e64, m8, ta, ma
2559 ; CHECK-ZVBB-NEXT: vclz.v v16, v16
2560 ; CHECK-ZVBB-NEXT: bltu a0, a1, .LBB95_2
2561 ; CHECK-ZVBB-NEXT: # %bb.1:
2562 ; CHECK-ZVBB-NEXT: mv a0, a1
2563 ; CHECK-ZVBB-NEXT: .LBB95_2:
2564 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e64, m8, ta, ma
2565 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2566 ; CHECK-ZVBB-NEXT: ret
2567 %v = call <vscale x 16 x i64> @llvm.vp.ctlz.nxv16i64(<vscale x 16 x i64> %va, i1 true, <vscale x 16 x i1> splat (i1 true), i32 %evl)
2568 ret <vscale x 16 x i64> %v
2569 }
2571 ; Test promotion.
2572 declare <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9>, i1 immarg, <vscale x 1 x i1>, i32)
2573 define <vscale x 1 x i9> @vp_ctlz_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2574 ; CHECK-LABEL: vp_ctlz_nxv1i9:
2575 ; CHECK: # %bb.0:
2576 ; CHECK-NEXT: li a1, 511
2577 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2578 ; CHECK-NEXT: vand.vx v8, v8, a1, v0.t
2579 ; CHECK-NEXT: li a0, 142
2580 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2581 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2582 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
2583 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2584 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2585 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2586 ; CHECK-NEXT: li a0, 16
2587 ; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t
2588 ; CHECK-NEXT: li a0, 7
2589 ; CHECK-NEXT: vsub.vx v8, v8, a0, v0.t
2590 ; CHECK-NEXT: ret
2591 ;
2592 ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i9:
2593 ; CHECK-ZVBB: # %bb.0:
2594 ; CHECK-ZVBB-NEXT: li a1, 511
2595 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2596 ; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1, v0.t
2597 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2598 ; CHECK-ZVBB-NEXT: li a0, 7
2599 ; CHECK-ZVBB-NEXT: vsub.vx v8, v8, a0, v0.t
2600 ; CHECK-ZVBB-NEXT: ret
2601 %v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va, i1 false, <vscale x 1 x i1> %m, i32 %evl)
2602 ret <vscale x 1 x i9> %v
2603 }
2604 define <vscale x 1 x i9> @vp_ctlz_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2605 ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i9:
2606 ; CHECK: # %bb.0:
2607 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2608 ; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
2609 ; CHECK-NEXT: li a0, 142
2610 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2611 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2612 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
2613 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2614 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2615 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2616 ; CHECK-NEXT: ret
2617 ;
2618 ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i9:
2619 ; CHECK-ZVBB: # %bb.0:
2620 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2621 ; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
2622 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2623 ; CHECK-ZVBB-NEXT: ret
2624 %v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va, i1 true, <vscale x 1 x i1> %m, i32 %evl)
2625 ret <vscale x 1 x i9> %v
2626 }
2627 define <vscale x 1 x i9> @vp_ctlo_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2628 ; CHECK-LABEL: vp_ctlo_nxv1i9:
2629 ; CHECK: # %bb.0:
2630 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2631 ; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
2632 ; CHECK-NEXT: li a0, 142
2633 ; CHECK-NEXT: vnot.v v8, v8, v0.t
2634 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2635 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2636 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
2637 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2638 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2639 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2640 ; CHECK-NEXT: ret
2641 ;
2642 ; CHECK-ZVBB-LABEL: vp_ctlo_nxv1i9:
2643 ; CHECK-ZVBB: # %bb.0:
2644 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2645 ; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
2646 ; CHECK-ZVBB-NEXT: vnot.v v8, v8, v0.t
2647 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2648 ; CHECK-ZVBB-NEXT: ret
2649 %va.not = xor <vscale x 1 x i9> %va, splat (i9 -1)
2650 %v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va.not, i1 false, <vscale x 1 x i1> %m, i32 %evl)
2651 ret <vscale x 1 x i9> %v
2652 }
2653 define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2654 ; CHECK-LABEL: vp_ctlo_zero_undef_nxv1i9:
2655 ; CHECK: # %bb.0:
2656 ; CHECK-NEXT: li a1, 511
2657 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2658 ; CHECK-NEXT: vxor.vx v8, v8, a1
2659 ; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
2660 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2661 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2662 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
2663 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2664 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2665 ; CHECK-NEXT: li a0, 142
2666 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2667 ; CHECK-NEXT: ret
2668 ;
2669 ; CHECK-ZVBB-LABEL: vp_ctlo_zero_undef_nxv1i9:
2670 ; CHECK-ZVBB: # %bb.0:
2671 ; CHECK-ZVBB-NEXT: li a1, 511
2672 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2673 ; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1
2674 ; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
2675 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2676 ; CHECK-ZVBB-NEXT: ret
2677 %va.not = xor <vscale x 1 x i9> %va, splat (i9 -1)
2678 %v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va.not, i1 true, <vscale x 1 x i1> %m, i32 %evl)
2679 ret <vscale x 1 x i9> %v
2680 }
2682 define <vscale x 1 x i9> @vp_ctlo_nxv1i9_vp_xor(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2683 ; CHECK-LABEL: vp_ctlo_nxv1i9_vp_xor:
2684 ; CHECK: # %bb.0:
2685 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2686 ; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
2687 ; CHECK-NEXT: li a0, 142
2688 ; CHECK-NEXT: vnot.v v8, v8, v0.t
2689 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2690 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2691 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
2692 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2693 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2694 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2695 ; CHECK-NEXT: ret
2696 ;
2697 ; CHECK-ZVBB-LABEL: vp_ctlo_nxv1i9_vp_xor:
2698 ; CHECK-ZVBB: # %bb.0:
2699 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2700 ; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
2701 ; CHECK-ZVBB-NEXT: vnot.v v8, v8, v0.t
2702 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2703 ; CHECK-ZVBB-NEXT: ret
2704 %va.not = call <vscale x 1 x i9> @llvm.vp.xor.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i9> splat (i9 -1), <vscale x 1 x i1> %m, i32 %evl)
2705 %v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va.not, i1 false, <vscale x 1 x i1> %m, i32 %evl)
2706 ret <vscale x 1 x i9> %v
2707 }
2709 define <vscale x 1 x i9> @vp_ctlo_zero_undef_nxv1i9_vp_xor(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2710 ; CHECK-LABEL: vp_ctlo_zero_undef_nxv1i9_vp_xor:
2711 ; CHECK: # %bb.0:
2712 ; CHECK-NEXT: li a1, 511
2713 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2714 ; CHECK-NEXT: vxor.vx v8, v8, a1, v0.t
2715 ; CHECK-NEXT: vsll.vi v8, v8, 7, v0.t
2716 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8, v0.t
2717 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2718 ; CHECK-NEXT: vsrl.vi v8, v9, 23, v0.t
2719 ; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
2720 ; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t
2721 ; CHECK-NEXT: li a0, 142
2722 ; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t
2723 ; CHECK-NEXT: ret
2724 ;
2725 ; CHECK-ZVBB-LABEL: vp_ctlo_zero_undef_nxv1i9_vp_xor:
2726 ; CHECK-ZVBB: # %bb.0:
2727 ; CHECK-ZVBB-NEXT: li a1, 511
2728 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2729 ; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1, v0.t
2730 ; CHECK-ZVBB-NEXT: vsll.vi v8, v8, 7, v0.t
2731 ; CHECK-ZVBB-NEXT: vclz.v v8, v8, v0.t
2732 ; CHECK-ZVBB-NEXT: ret
2733 %va.not = call <vscale x 1 x i9> @llvm.vp.xor.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i9> splat (i9 -1), <vscale x 1 x i1> %m, i32 %evl)
2734 %v = call <vscale x 1 x i9> @llvm.vp.ctlz.nxv1i9(<vscale x 1 x i9> %va.not, i1 true, <vscale x 1 x i1> %m, i32 %evl)
2735 ret <vscale x 1 x i9> %v
2736 }
2738 define <vscale x 1 x i9> @vp_ctlo_zero_nxv1i9_unpredicated_ctlz_with_vp_xor(<vscale x 1 x i9> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
2739 ; CHECK-LABEL: vp_ctlo_zero_nxv1i9_unpredicated_ctlz_with_vp_xor:
2740 ; CHECK: # %bb.0:
2741 ; CHECK-NEXT: li a1, 511
2742 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2743 ; CHECK-NEXT: vxor.vx v8, v8, a1, v0.t
2744 ; CHECK-NEXT: li a0, 142
2745 ; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
2746 ; CHECK-NEXT: vand.vx v8, v8, a1
2747 ; CHECK-NEXT: li a1, 16
2748 ; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
2749 ; CHECK-NEXT: vnsrl.wi v8, v9, 23
2750 ; CHECK-NEXT: vrsub.vx v8, v8, a0
2751 ; CHECK-NEXT: vminu.vx v8, v8, a1
2752 ; CHECK-NEXT: li a0, 7
2753 ; CHECK-NEXT: vsub.vx v8, v8, a0
2754 ; CHECK-NEXT: ret
2755 ;
2756 ; CHECK-ZVBB-LABEL: vp_ctlo_zero_nxv1i9_unpredicated_ctlz_with_vp_xor:
2757 ; CHECK-ZVBB: # %bb.0:
2758 ; CHECK-ZVBB-NEXT: li a1, 511
2759 ; CHECK-ZVBB-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
2760 ; CHECK-ZVBB-NEXT: vxor.vx v8, v8, a1, v0.t
2761 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2762 ; CHECK-ZVBB-NEXT: vand.vx v8, v8, a1
2763 ; CHECK-ZVBB-NEXT: vclz.v v8, v8
2764 ; CHECK-ZVBB-NEXT: li a0, 7
2765 ; CHECK-ZVBB-NEXT: vsub.vx v8, v8, a0
2766 ; CHECK-ZVBB-NEXT: ret
2767 %va.not = call <vscale x 1 x i9> @llvm.vp.xor.nxv1i9(<vscale x 1 x i9> %va, <vscale x 1 x i9> splat (i9 -1), <vscale x 1 x i1> %m, i32 %evl)
2768 %v = call <vscale x 1 x i9> @llvm.ctlz(<vscale x 1 x i9> %va.not, i1 false)
2769 ret <vscale x 1 x i9> %v
2770 }
2772 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
2773 ; RV32: {{.*}}
2774 ; RV64: {{.*}}