1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
5 define <vscale x 1 x i8> @vadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
6 ; CHECK-LABEL: vadd_vx_nxv1i8:
8 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
9 ; CHECK-NEXT: vadd.vx v8, v8, a0
11 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
12 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
13 %vc = add <vscale x 1 x i8> %va, %splat
14 ret <vscale x 1 x i8> %vc
17 define <vscale x 1 x i8> @vadd_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
18 ; CHECK-LABEL: vadd_vx_nxv1i8_0:
20 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
21 ; CHECK-NEXT: vadd.vi v8, v8, -1
23 %vc = add <vscale x 1 x i8> %va, splat (i8 -1)
24 ret <vscale x 1 x i8> %vc
27 define <vscale x 1 x i8> @vadd_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
28 ; CHECK-LABEL: vadd_vx_nxv1i8_1:
30 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
31 ; CHECK-NEXT: vadd.vi v8, v8, 2
33 %vc = add <vscale x 1 x i8> %va, splat (i8 2)
34 ret <vscale x 1 x i8> %vc
37 ; Test constant adds to see if we can optimize them away for scalable vectors.
38 define <vscale x 1 x i8> @vadd_ii_nxv1i8_1() {
39 ; CHECK-LABEL: vadd_ii_nxv1i8_1:
41 ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
42 ; CHECK-NEXT: vmv.v.i v8, 5
44 %vc = add <vscale x 1 x i8> splat (i8 2), splat (i8 3)
45 ret <vscale x 1 x i8> %vc
48 define <vscale x 2 x i8> @vadd_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
49 ; CHECK-LABEL: vadd_vx_nxv2i8:
51 ; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
52 ; CHECK-NEXT: vadd.vx v8, v8, a0
54 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
55 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
56 %vc = add <vscale x 2 x i8> %va, %splat
57 ret <vscale x 2 x i8> %vc
60 define <vscale x 2 x i8> @vadd_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
61 ; CHECK-LABEL: vadd_vx_nxv2i8_0:
63 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
64 ; CHECK-NEXT: vadd.vi v8, v8, -1
66 %vc = add <vscale x 2 x i8> %va, splat (i8 -1)
67 ret <vscale x 2 x i8> %vc
70 define <vscale x 2 x i8> @vadd_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
71 ; CHECK-LABEL: vadd_vx_nxv2i8_1:
73 ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
74 ; CHECK-NEXT: vadd.vi v8, v8, 2
76 %vc = add <vscale x 2 x i8> %va, splat (i8 2)
77 ret <vscale x 2 x i8> %vc
80 define <vscale x 4 x i8> @vadd_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
81 ; CHECK-LABEL: vadd_vx_nxv4i8:
83 ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
84 ; CHECK-NEXT: vadd.vx v8, v8, a0
86 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
87 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
88 %vc = add <vscale x 4 x i8> %va, %splat
89 ret <vscale x 4 x i8> %vc
92 define <vscale x 4 x i8> @vadd_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
93 ; CHECK-LABEL: vadd_vx_nxv4i8_0:
95 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
96 ; CHECK-NEXT: vadd.vi v8, v8, -1
98 %vc = add <vscale x 4 x i8> %va, splat (i8 -1)
99 ret <vscale x 4 x i8> %vc
102 define <vscale x 4 x i8> @vadd_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
103 ; CHECK-LABEL: vadd_vx_nxv4i8_1:
105 ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
106 ; CHECK-NEXT: vadd.vi v8, v8, 2
108 %vc = add <vscale x 4 x i8> %va, splat (i8 2)
109 ret <vscale x 4 x i8> %vc
112 define <vscale x 8 x i8> @vadd_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
113 ; CHECK-LABEL: vadd_vx_nxv8i8:
115 ; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
116 ; CHECK-NEXT: vadd.vx v8, v8, a0
118 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
119 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
120 %vc = add <vscale x 8 x i8> %va, %splat
121 ret <vscale x 8 x i8> %vc
124 define <vscale x 8 x i8> @vadd_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
125 ; CHECK-LABEL: vadd_vx_nxv8i8_0:
127 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
128 ; CHECK-NEXT: vadd.vi v8, v8, -1
130 %vc = add <vscale x 8 x i8> %va, splat (i8 -1)
131 ret <vscale x 8 x i8> %vc
134 define <vscale x 8 x i8> @vadd_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
135 ; CHECK-LABEL: vadd_vx_nxv8i8_1:
137 ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
138 ; CHECK-NEXT: vadd.vi v8, v8, 2
140 %vc = add <vscale x 8 x i8> %va, splat (i8 2)
141 ret <vscale x 8 x i8> %vc
144 define <vscale x 16 x i8> @vadd_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
145 ; CHECK-LABEL: vadd_vx_nxv16i8:
147 ; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma
148 ; CHECK-NEXT: vadd.vx v8, v8, a0
150 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
151 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
152 %vc = add <vscale x 16 x i8> %va, %splat
153 ret <vscale x 16 x i8> %vc
156 define <vscale x 16 x i8> @vadd_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
157 ; CHECK-LABEL: vadd_vx_nxv16i8_0:
159 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
160 ; CHECK-NEXT: vadd.vi v8, v8, -1
162 %vc = add <vscale x 16 x i8> %va, splat (i8 -1)
163 ret <vscale x 16 x i8> %vc
166 define <vscale x 16 x i8> @vadd_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
167 ; CHECK-LABEL: vadd_vx_nxv16i8_1:
169 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
170 ; CHECK-NEXT: vadd.vi v8, v8, 2
172 %vc = add <vscale x 16 x i8> %va, splat (i8 2)
173 ret <vscale x 16 x i8> %vc
176 define <vscale x 32 x i8> @vadd_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
177 ; CHECK-LABEL: vadd_vx_nxv32i8:
179 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
180 ; CHECK-NEXT: vadd.vx v8, v8, a0
182 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
183 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
184 %vc = add <vscale x 32 x i8> %va, %splat
185 ret <vscale x 32 x i8> %vc
188 define <vscale x 32 x i8> @vadd_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
189 ; CHECK-LABEL: vadd_vx_nxv32i8_0:
191 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
192 ; CHECK-NEXT: vadd.vi v8, v8, -1
194 %vc = add <vscale x 32 x i8> %va, splat (i8 -1)
195 ret <vscale x 32 x i8> %vc
198 define <vscale x 32 x i8> @vadd_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
199 ; CHECK-LABEL: vadd_vx_nxv32i8_1:
201 ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
202 ; CHECK-NEXT: vadd.vi v8, v8, 2
204 %vc = add <vscale x 32 x i8> %va, splat (i8 2)
205 ret <vscale x 32 x i8> %vc
208 define <vscale x 64 x i8> @vadd_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
209 ; CHECK-LABEL: vadd_vx_nxv64i8:
211 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
212 ; CHECK-NEXT: vadd.vx v8, v8, a0
214 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
215 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
216 %vc = add <vscale x 64 x i8> %va, %splat
217 ret <vscale x 64 x i8> %vc
220 define <vscale x 64 x i8> @vadd_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
221 ; CHECK-LABEL: vadd_vx_nxv64i8_0:
223 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
224 ; CHECK-NEXT: vadd.vi v8, v8, -1
226 %vc = add <vscale x 64 x i8> %va, splat (i8 -1)
227 ret <vscale x 64 x i8> %vc
230 define <vscale x 64 x i8> @vadd_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
231 ; CHECK-LABEL: vadd_vx_nxv64i8_1:
233 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
234 ; CHECK-NEXT: vadd.vi v8, v8, 2
236 %vc = add <vscale x 64 x i8> %va, splat (i8 2)
237 ret <vscale x 64 x i8> %vc
240 define <vscale x 1 x i16> @vadd_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
241 ; CHECK-LABEL: vadd_vx_nxv1i16:
243 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
244 ; CHECK-NEXT: vadd.vx v8, v8, a0
246 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
247 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
248 %vc = add <vscale x 1 x i16> %va, %splat
249 ret <vscale x 1 x i16> %vc
252 define <vscale x 1 x i16> @vadd_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
253 ; CHECK-LABEL: vadd_vx_nxv1i16_0:
255 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
256 ; CHECK-NEXT: vadd.vi v8, v8, -1
258 %vc = add <vscale x 1 x i16> %va, splat (i16 -1)
259 ret <vscale x 1 x i16> %vc
262 define <vscale x 1 x i16> @vadd_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
263 ; CHECK-LABEL: vadd_vx_nxv1i16_1:
265 ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
266 ; CHECK-NEXT: vadd.vi v8, v8, 2
268 %vc = add <vscale x 1 x i16> %va, splat (i16 2)
269 ret <vscale x 1 x i16> %vc
272 define <vscale x 2 x i16> @vadd_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
273 ; CHECK-LABEL: vadd_vx_nxv2i16:
275 ; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
276 ; CHECK-NEXT: vadd.vx v8, v8, a0
278 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
279 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
280 %vc = add <vscale x 2 x i16> %va, %splat
281 ret <vscale x 2 x i16> %vc
284 define <vscale x 2 x i16> @vadd_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
285 ; CHECK-LABEL: vadd_vx_nxv2i16_0:
287 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
288 ; CHECK-NEXT: vadd.vi v8, v8, -1
290 %vc = add <vscale x 2 x i16> %va, splat (i16 -1)
291 ret <vscale x 2 x i16> %vc
294 define <vscale x 2 x i16> @vadd_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
295 ; CHECK-LABEL: vadd_vx_nxv2i16_1:
297 ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
298 ; CHECK-NEXT: vadd.vi v8, v8, 2
300 %vc = add <vscale x 2 x i16> %va, splat (i16 2)
301 ret <vscale x 2 x i16> %vc
304 define <vscale x 4 x i16> @vadd_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
305 ; CHECK-LABEL: vadd_vx_nxv4i16:
307 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
308 ; CHECK-NEXT: vadd.vx v8, v8, a0
310 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
311 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
312 %vc = add <vscale x 4 x i16> %va, %splat
313 ret <vscale x 4 x i16> %vc
316 define <vscale x 4 x i16> @vadd_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
317 ; CHECK-LABEL: vadd_vx_nxv4i16_0:
319 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
320 ; CHECK-NEXT: vadd.vi v8, v8, -1
322 %vc = add <vscale x 4 x i16> %va, splat (i16 -1)
323 ret <vscale x 4 x i16> %vc
326 define <vscale x 4 x i16> @vadd_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
327 ; CHECK-LABEL: vadd_vx_nxv4i16_1:
329 ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
330 ; CHECK-NEXT: vadd.vi v8, v8, 2
332 %vc = add <vscale x 4 x i16> %va, splat (i16 2)
333 ret <vscale x 4 x i16> %vc
336 define <vscale x 8 x i16> @vadd_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
337 ; CHECK-LABEL: vadd_vx_nxv8i16:
339 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
340 ; CHECK-NEXT: vadd.vx v8, v8, a0
342 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
343 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
344 %vc = add <vscale x 8 x i16> %va, %splat
345 ret <vscale x 8 x i16> %vc
348 define <vscale x 8 x i16> @vadd_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
349 ; CHECK-LABEL: vadd_vx_nxv8i16_0:
351 ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
352 ; CHECK-NEXT: vadd.vi v8, v8, -1
354 %vc = add <vscale x 8 x i16> %va, splat (i16 -1)
355 ret <vscale x 8 x i16> %vc
358 define <vscale x 8 x i16> @vadd_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
359 ; CHECK-LABEL: vadd_vx_nxv8i16_1:
361 ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
362 ; CHECK-NEXT: vadd.vi v8, v8, 2
364 %vc = add <vscale x 8 x i16> %va, splat (i16 2)
365 ret <vscale x 8 x i16> %vc
368 define <vscale x 16 x i16> @vadd_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
369 ; CHECK-LABEL: vadd_vx_nxv16i16:
371 ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
372 ; CHECK-NEXT: vadd.vx v8, v8, a0
374 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
375 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
376 %vc = add <vscale x 16 x i16> %va, %splat
377 ret <vscale x 16 x i16> %vc
380 define <vscale x 16 x i16> @vadd_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
381 ; CHECK-LABEL: vadd_vx_nxv16i16_0:
383 ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
384 ; CHECK-NEXT: vadd.vi v8, v8, -1
386 %vc = add <vscale x 16 x i16> %va, splat (i16 -1)
387 ret <vscale x 16 x i16> %vc
390 define <vscale x 16 x i16> @vadd_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
391 ; CHECK-LABEL: vadd_vx_nxv16i16_1:
393 ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
394 ; CHECK-NEXT: vadd.vi v8, v8, 2
396 %vc = add <vscale x 16 x i16> %va, splat (i16 2)
397 ret <vscale x 16 x i16> %vc
400 define <vscale x 32 x i16> @vadd_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
401 ; CHECK-LABEL: vadd_vx_nxv32i16:
403 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
404 ; CHECK-NEXT: vadd.vx v8, v8, a0
406 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
407 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
408 %vc = add <vscale x 32 x i16> %va, %splat
409 ret <vscale x 32 x i16> %vc
412 define <vscale x 32 x i16> @vadd_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
413 ; CHECK-LABEL: vadd_vx_nxv32i16_0:
415 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
416 ; CHECK-NEXT: vadd.vi v8, v8, -1
418 %vc = add <vscale x 32 x i16> %va, splat (i16 -1)
419 ret <vscale x 32 x i16> %vc
422 define <vscale x 32 x i16> @vadd_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
423 ; CHECK-LABEL: vadd_vx_nxv32i16_1:
425 ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
426 ; CHECK-NEXT: vadd.vi v8, v8, 2
428 %vc = add <vscale x 32 x i16> %va, splat (i16 2)
429 ret <vscale x 32 x i16> %vc
432 define <vscale x 1 x i32> @vadd_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
433 ; CHECK-LABEL: vadd_vx_nxv1i32:
435 ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
436 ; CHECK-NEXT: vadd.vx v8, v8, a0
438 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
439 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
440 %vc = add <vscale x 1 x i32> %va, %splat
441 ret <vscale x 1 x i32> %vc
444 define <vscale x 1 x i32> @vadd_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
445 ; CHECK-LABEL: vadd_vx_nxv1i32_0:
447 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
448 ; CHECK-NEXT: vadd.vi v8, v8, -1
450 %vc = add <vscale x 1 x i32> %va, splat (i32 -1)
451 ret <vscale x 1 x i32> %vc
454 define <vscale x 1 x i32> @vadd_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
455 ; CHECK-LABEL: vadd_vx_nxv1i32_1:
457 ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
458 ; CHECK-NEXT: vadd.vi v8, v8, 2
460 %vc = add <vscale x 1 x i32> %va, splat (i32 2)
461 ret <vscale x 1 x i32> %vc
464 define <vscale x 2 x i32> @vadd_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
465 ; CHECK-LABEL: vadd_vx_nxv2i32:
467 ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
468 ; CHECK-NEXT: vadd.vx v8, v8, a0
470 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
471 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
472 %vc = add <vscale x 2 x i32> %va, %splat
473 ret <vscale x 2 x i32> %vc
476 define <vscale x 2 x i32> @vadd_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
477 ; CHECK-LABEL: vadd_vx_nxv2i32_0:
479 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
480 ; CHECK-NEXT: vadd.vi v8, v8, -1
482 %vc = add <vscale x 2 x i32> %va, splat (i32 -1)
483 ret <vscale x 2 x i32> %vc
486 define <vscale x 2 x i32> @vadd_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
487 ; CHECK-LABEL: vadd_vx_nxv2i32_1:
489 ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
490 ; CHECK-NEXT: vadd.vi v8, v8, 2
492 %vc = add <vscale x 2 x i32> %va, splat (i32 2)
493 ret <vscale x 2 x i32> %vc
496 define <vscale x 4 x i32> @vadd_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
497 ; CHECK-LABEL: vadd_vx_nxv4i32:
499 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
500 ; CHECK-NEXT: vadd.vx v8, v8, a0
502 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
503 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
504 %vc = add <vscale x 4 x i32> %va, %splat
505 ret <vscale x 4 x i32> %vc
508 define <vscale x 4 x i32> @vadd_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
509 ; CHECK-LABEL: vadd_vx_nxv4i32_0:
511 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
512 ; CHECK-NEXT: vadd.vi v8, v8, -1
514 %vc = add <vscale x 4 x i32> %va, splat (i32 -1)
515 ret <vscale x 4 x i32> %vc
518 define <vscale x 4 x i32> @vadd_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
519 ; CHECK-LABEL: vadd_vx_nxv4i32_1:
521 ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
522 ; CHECK-NEXT: vadd.vi v8, v8, 2
524 %vc = add <vscale x 4 x i32> %va, splat (i32 2)
525 ret <vscale x 4 x i32> %vc
528 define <vscale x 8 x i32> @vadd_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
529 ; CHECK-LABEL: vadd_vx_nxv8i32:
531 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
532 ; CHECK-NEXT: vadd.vx v8, v8, a0
534 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
535 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
536 %vc = add <vscale x 8 x i32> %va, %splat
537 ret <vscale x 8 x i32> %vc
540 define <vscale x 8 x i32> @vadd_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
541 ; CHECK-LABEL: vadd_vx_nxv8i32_0:
543 ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
544 ; CHECK-NEXT: vadd.vi v8, v8, -1
546 %vc = add <vscale x 8 x i32> %va, splat (i32 -1)
547 ret <vscale x 8 x i32> %vc
550 define <vscale x 8 x i32> @vadd_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
551 ; CHECK-LABEL: vadd_vx_nxv8i32_1:
553 ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
554 ; CHECK-NEXT: vadd.vi v8, v8, 2
556 %vc = add <vscale x 8 x i32> %va, splat (i32 2)
557 ret <vscale x 8 x i32> %vc
560 define <vscale x 16 x i32> @vadd_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
561 ; CHECK-LABEL: vadd_vx_nxv16i32:
563 ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
564 ; CHECK-NEXT: vadd.vx v8, v8, a0
566 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
567 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
568 %vc = add <vscale x 16 x i32> %va, %splat
569 ret <vscale x 16 x i32> %vc
572 define <vscale x 16 x i32> @vadd_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
573 ; CHECK-LABEL: vadd_vx_nxv16i32_0:
575 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
576 ; CHECK-NEXT: vadd.vi v8, v8, -1
578 %vc = add <vscale x 16 x i32> %va, splat (i32 -1)
579 ret <vscale x 16 x i32> %vc
582 define <vscale x 16 x i32> @vadd_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
583 ; CHECK-LABEL: vadd_vx_nxv16i32_1:
585 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
586 ; CHECK-NEXT: vadd.vi v8, v8, 2
588 %vc = add <vscale x 16 x i32> %va, splat (i32 2)
589 ret <vscale x 16 x i32> %vc
592 define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
593 ; RV32-LABEL: vadd_vx_nxv1i64:
595 ; RV32-NEXT: addi sp, sp, -16
596 ; RV32-NEXT: .cfi_def_cfa_offset 16
597 ; RV32-NEXT: sw a0, 8(sp)
598 ; RV32-NEXT: sw a1, 12(sp)
599 ; RV32-NEXT: addi a0, sp, 8
600 ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
601 ; RV32-NEXT: vlse64.v v9, (a0), zero
602 ; RV32-NEXT: vadd.vv v8, v8, v9
603 ; RV32-NEXT: addi sp, sp, 16
604 ; RV32-NEXT: .cfi_def_cfa_offset 0
607 ; RV64-LABEL: vadd_vx_nxv1i64:
609 ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
610 ; RV64-NEXT: vadd.vx v8, v8, a0
612 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
613 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
614 %vc = add <vscale x 1 x i64> %va, %splat
615 ret <vscale x 1 x i64> %vc
618 define <vscale x 1 x i64> @vadd_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
619 ; CHECK-LABEL: vadd_vx_nxv1i64_0:
621 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
622 ; CHECK-NEXT: vadd.vi v8, v8, -1
624 %vc = add <vscale x 1 x i64> %va, splat (i64 -1)
625 ret <vscale x 1 x i64> %vc
628 define <vscale x 1 x i64> @vadd_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
629 ; CHECK-LABEL: vadd_vx_nxv1i64_1:
631 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
632 ; CHECK-NEXT: vadd.vi v8, v8, 2
634 %vc = add <vscale x 1 x i64> %va, splat (i64 2)
635 ret <vscale x 1 x i64> %vc
638 define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
639 ; RV32-LABEL: vadd_vx_nxv2i64:
641 ; RV32-NEXT: addi sp, sp, -16
642 ; RV32-NEXT: .cfi_def_cfa_offset 16
643 ; RV32-NEXT: sw a0, 8(sp)
644 ; RV32-NEXT: sw a1, 12(sp)
645 ; RV32-NEXT: addi a0, sp, 8
646 ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
647 ; RV32-NEXT: vlse64.v v10, (a0), zero
648 ; RV32-NEXT: vadd.vv v8, v8, v10
649 ; RV32-NEXT: addi sp, sp, 16
650 ; RV32-NEXT: .cfi_def_cfa_offset 0
653 ; RV64-LABEL: vadd_vx_nxv2i64:
655 ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
656 ; RV64-NEXT: vadd.vx v8, v8, a0
658 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
659 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
660 %vc = add <vscale x 2 x i64> %va, %splat
661 ret <vscale x 2 x i64> %vc
664 define <vscale x 2 x i64> @vadd_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
665 ; CHECK-LABEL: vadd_vx_nxv2i64_0:
667 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
668 ; CHECK-NEXT: vadd.vi v8, v8, -1
670 %vc = add <vscale x 2 x i64> %va, splat (i64 -1)
671 ret <vscale x 2 x i64> %vc
674 define <vscale x 2 x i64> @vadd_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
675 ; CHECK-LABEL: vadd_vx_nxv2i64_1:
677 ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
678 ; CHECK-NEXT: vadd.vi v8, v8, 2
680 %vc = add <vscale x 2 x i64> %va, splat (i64 2)
681 ret <vscale x 2 x i64> %vc
684 define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
685 ; RV32-LABEL: vadd_vx_nxv4i64:
687 ; RV32-NEXT: addi sp, sp, -16
688 ; RV32-NEXT: .cfi_def_cfa_offset 16
689 ; RV32-NEXT: sw a0, 8(sp)
690 ; RV32-NEXT: sw a1, 12(sp)
691 ; RV32-NEXT: addi a0, sp, 8
692 ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
693 ; RV32-NEXT: vlse64.v v12, (a0), zero
694 ; RV32-NEXT: vadd.vv v8, v8, v12
695 ; RV32-NEXT: addi sp, sp, 16
696 ; RV32-NEXT: .cfi_def_cfa_offset 0
699 ; RV64-LABEL: vadd_vx_nxv4i64:
701 ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
702 ; RV64-NEXT: vadd.vx v8, v8, a0
704 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
705 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
706 %vc = add <vscale x 4 x i64> %va, %splat
707 ret <vscale x 4 x i64> %vc
710 define <vscale x 4 x i64> @vadd_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
711 ; CHECK-LABEL: vadd_vx_nxv4i64_0:
713 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
714 ; CHECK-NEXT: vadd.vi v8, v8, -1
716 %vc = add <vscale x 4 x i64> %va, splat (i64 -1)
717 ret <vscale x 4 x i64> %vc
720 define <vscale x 4 x i64> @vadd_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
721 ; CHECK-LABEL: vadd_vx_nxv4i64_1:
723 ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
724 ; CHECK-NEXT: vadd.vi v8, v8, 2
726 %vc = add <vscale x 4 x i64> %va, splat (i64 2)
727 ret <vscale x 4 x i64> %vc
730 define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
731 ; RV32-LABEL: vadd_vx_nxv8i64:
733 ; RV32-NEXT: addi sp, sp, -16
734 ; RV32-NEXT: .cfi_def_cfa_offset 16
735 ; RV32-NEXT: sw a0, 8(sp)
736 ; RV32-NEXT: sw a1, 12(sp)
737 ; RV32-NEXT: addi a0, sp, 8
738 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
739 ; RV32-NEXT: vlse64.v v16, (a0), zero
740 ; RV32-NEXT: vadd.vv v8, v8, v16
741 ; RV32-NEXT: addi sp, sp, 16
742 ; RV32-NEXT: .cfi_def_cfa_offset 0
745 ; RV64-LABEL: vadd_vx_nxv8i64:
747 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
748 ; RV64-NEXT: vadd.vx v8, v8, a0
750 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
751 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
752 %vc = add <vscale x 8 x i64> %va, %splat
753 ret <vscale x 8 x i64> %vc
756 define <vscale x 8 x i64> @vadd_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
757 ; CHECK-LABEL: vadd_vx_nxv8i64_0:
759 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
760 ; CHECK-NEXT: vadd.vi v8, v8, -1
762 %vc = add <vscale x 8 x i64> %va, splat (i64 -1)
763 ret <vscale x 8 x i64> %vc
766 define <vscale x 8 x i64> @vadd_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
767 ; CHECK-LABEL: vadd_vx_nxv8i64_1:
769 ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
770 ; CHECK-NEXT: vadd.vi v8, v8, 2
772 %vc = add <vscale x 8 x i64> %va, splat (i64 2)
773 ret <vscale x 8 x i64> %vc
776 define <vscale x 8 x i64> @vadd_xx_nxv8i64(i64 %a, i64 %b) nounwind {
777 ; RV32-LABEL: vadd_xx_nxv8i64:
779 ; RV32-NEXT: addi sp, sp, -16
780 ; RV32-NEXT: add a2, a0, a2
781 ; RV32-NEXT: add a1, a1, a3
782 ; RV32-NEXT: sltu a0, a2, a0
783 ; RV32-NEXT: add a0, a1, a0
784 ; RV32-NEXT: sw a2, 8(sp)
785 ; RV32-NEXT: sw a0, 12(sp)
786 ; RV32-NEXT: addi a0, sp, 8
787 ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
788 ; RV32-NEXT: vlse64.v v8, (a0), zero
789 ; RV32-NEXT: addi sp, sp, 16
792 ; RV64-LABEL: vadd_xx_nxv8i64:
794 ; RV64-NEXT: add a0, a0, a1
795 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
796 ; RV64-NEXT: vmv.v.x v8, a0
798 %head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
799 %splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
800 %head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
801 %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
802 %v = add <vscale x 8 x i64> %splat1, %splat2
803 ret <vscale x 8 x i64> %v
806 define <vscale x 8 x i32> @vadd_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
807 ; CHECK-LABEL: vadd_vv_mask_nxv8i32:
809 ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
810 ; CHECK-NEXT: vadd.vv v8, v8, v12, v0.t
812 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
813 %vc = add <vscale x 8 x i32> %va, %vs
814 ret <vscale x 8 x i32> %vc
817 define <vscale x 8 x i32> @vadd_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
818 ; CHECK-LABEL: vadd_vx_mask_nxv8i32:
820 ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
821 ; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
823 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
824 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
825 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
826 %vc = add <vscale x 8 x i32> %va, %vs
827 ret <vscale x 8 x i32> %vc
830 define <vscale x 8 x i32> @vadd_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
831 ; CHECK-LABEL: vadd_vi_mask_nxv8i32:
833 ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
834 ; CHECK-NEXT: vadd.vi v8, v8, 7, v0.t
836 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 7), <vscale x 8 x i32> zeroinitializer
837 %vc = add <vscale x 8 x i32> %va, %vs
838 ret <vscale x 8 x i32> %vc
841 define <vscale x 8 x i32> @vadd_vv_mask_negative0_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
842 ; CHECK-LABEL: vadd_vv_mask_negative0_nxv8i32:
844 ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
845 ; CHECK-NEXT: vmv.v.i v16, 1
846 ; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
847 ; CHECK-NEXT: vadd.vv v8, v8, v12
849 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> splat (i32 1)
850 %vc = add <vscale x 8 x i32> %va, %vs
851 ret <vscale x 8 x i32> %vc
854 define <vscale x 8 x i32> @vadd_vv_mask_negative1_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
855 ; CHECK-LABEL: vadd_vv_mask_negative1_nxv8i32:
857 ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
858 ; CHECK-NEXT: vmv.v.i v16, 0
859 ; CHECK-NEXT: vmerge.vvm v12, v16, v12, v0
860 ; CHECK-NEXT: vadd.vv v8, v8, v12
861 ; CHECK-NEXT: vadd.vv v8, v8, v12
863 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
864 %vc = add <vscale x 8 x i32> %va, %vs
865 %vd = add <vscale x 8 x i32> %vc, %vs
866 ret <vscale x 8 x i32> %vd