| blob | a43b22102c24bfb1f8a65433306fa91de89981f5 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=thumbv6m-none-unknown-eabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=ARM
4 declare i4 @llvm.umul.fix.sat.i4 (i4, i4, i32)
5 declare i32 @llvm.umul.fix.sat.i32 (i32, i32, i32)
6 declare i64 @llvm.umul.fix.sat.i64 (i64, i64, i32)
8 define i32 @func(i32 %x, i32 %y) nounwind {
9 ; ARM-LABEL: func:
10 ; ARM: @ %bb.0:
11 ; ARM-NEXT: .save {r4, lr}
12 ; ARM-NEXT: push {r4, lr}
13 ; ARM-NEXT: mov r2, r1
14 ; ARM-NEXT: movs r4, #0
15 ; ARM-NEXT: mov r1, r4
16 ; ARM-NEXT: mov r3, r4
17 ; ARM-NEXT: bl __aeabi_lmul
18 ; ARM-NEXT: cmp r1, #3
19 ; ARM-NEXT: bhi .LBB0_2
20 ; ARM-NEXT: @ %bb.1:
21 ; ARM-NEXT: lsrs r0, r0, #2
22 ; ARM-NEXT: lsls r1, r1, #30
23 ; ARM-NEXT: adds r0, r1, r0
24 ; ARM-NEXT: pop {r4, pc}
25 ; ARM-NEXT: .LBB0_2:
26 ; ARM-NEXT: mvns r0, r4
27 ; ARM-NEXT: pop {r4, pc}
28 %tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 2)
29 ret i32 %tmp
30 }
32 define i64 @func2(i64 %x, i64 %y) nounwind {
33 ; ARM-LABEL: func2:
34 ; ARM: @ %bb.0:
35 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
36 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
37 ; ARM-NEXT: .pad #28
38 ; ARM-NEXT: sub sp, #28
39 ; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill
40 ; ARM-NEXT: mov r5, r1
41 ; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
42 ; ARM-NEXT: movs r4, #0
43 ; ARM-NEXT: mov r6, r0
44 ; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
45 ; ARM-NEXT: mov r1, r4
46 ; ARM-NEXT: mov r7, r2
47 ; ARM-NEXT: str r2, [sp, #12] @ 4-byte Spill
48 ; ARM-NEXT: mov r3, r4
49 ; ARM-NEXT: bl __aeabi_lmul
50 ; ARM-NEXT: str r0, [sp, #20] @ 4-byte Spill
51 ; ARM-NEXT: str r1, [sp, #16] @ 4-byte Spill
52 ; ARM-NEXT: mov r0, r5
53 ; ARM-NEXT: mov r1, r4
54 ; ARM-NEXT: mov r2, r7
55 ; ARM-NEXT: mov r3, r4
56 ; ARM-NEXT: bl __aeabi_lmul
57 ; ARM-NEXT: mov r5, r1
58 ; ARM-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
59 ; ARM-NEXT: adds r0, r0, r1
60 ; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
61 ; ARM-NEXT: adcs r5, r4
62 ; ARM-NEXT: mov r0, r6
63 ; ARM-NEXT: mov r1, r4
64 ; ARM-NEXT: ldr r7, [sp, #24] @ 4-byte Reload
65 ; ARM-NEXT: mov r2, r7
66 ; ARM-NEXT: mov r3, r4
67 ; ARM-NEXT: bl __aeabi_lmul
68 ; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
69 ; ARM-NEXT: adds r0, r0, r2
70 ; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
71 ; ARM-NEXT: adcs r1, r4
72 ; ARM-NEXT: adds r0, r5, r1
73 ; ARM-NEXT: str r0, [sp] @ 4-byte Spill
74 ; ARM-NEXT: mov r6, r4
75 ; ARM-NEXT: adcs r6, r4
76 ; ARM-NEXT: ldr r5, [sp, #4] @ 4-byte Reload
77 ; ARM-NEXT: mov r0, r5
78 ; ARM-NEXT: mov r1, r4
79 ; ARM-NEXT: mov r2, r7
80 ; ARM-NEXT: mov r3, r4
81 ; ARM-NEXT: bl __aeabi_lmul
82 ; ARM-NEXT: mov r7, r1
83 ; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload
84 ; ARM-NEXT: adds r0, r0, r1
85 ; ARM-NEXT: str r0, [sp] @ 4-byte Spill
86 ; ARM-NEXT: adcs r7, r6
87 ; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
88 ; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
89 ; ARM-NEXT: mov r2, r4
90 ; ARM-NEXT: mov r3, r4
91 ; ARM-NEXT: bl __aeabi_lmul
92 ; ARM-NEXT: mov r6, r0
93 ; ARM-NEXT: str r1, [sp, #24] @ 4-byte Spill
94 ; ARM-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
95 ; ARM-NEXT: mov r1, r5
96 ; ARM-NEXT: mov r2, r4
97 ; ARM-NEXT: mov r3, r4
98 ; ARM-NEXT: bl __aeabi_lmul
99 ; ARM-NEXT: adds r0, r0, r6
100 ; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
101 ; ARM-NEXT: adcs r1, r2
102 ; ARM-NEXT: ldr r2, [sp] @ 4-byte Reload
103 ; ARM-NEXT: adds r0, r2, r0
104 ; ARM-NEXT: adcs r1, r7
105 ; ARM-NEXT: lsrs r5, r0, #2
106 ; ARM-NEXT: orrs r5, r1
107 ; ARM-NEXT: lsls r0, r0, #30
108 ; ARM-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
109 ; ARM-NEXT: lsrs r1, r3, #2
110 ; ARM-NEXT: adds r2, r0, r1
111 ; ARM-NEXT: lsls r0, r3, #30
112 ; ARM-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
113 ; ARM-NEXT: lsrs r1, r1, #2
114 ; ARM-NEXT: adds r3, r0, r1
115 ; ARM-NEXT: mvns r1, r4
116 ; ARM-NEXT: cmp r5, #0
117 ; ARM-NEXT: mov r0, r1
118 ; ARM-NEXT: beq .LBB1_3
119 ; ARM-NEXT: @ %bb.1:
120 ; ARM-NEXT: beq .LBB1_4
121 ; ARM-NEXT: .LBB1_2:
122 ; ARM-NEXT: add sp, #28
123 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
124 ; ARM-NEXT: .LBB1_3:
125 ; ARM-NEXT: mov r0, r3
126 ; ARM-NEXT: bne .LBB1_2
127 ; ARM-NEXT: .LBB1_4:
128 ; ARM-NEXT: mov r1, r2
129 ; ARM-NEXT: add sp, #28
130 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
131 %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 2)
132 ret i64 %tmp
133 }
135 define i4 @func3(i4 %x, i4 %y) nounwind {
136 ; ARM-LABEL: func3:
137 ; ARM: @ %bb.0:
138 ; ARM-NEXT: .save {r4, lr}
139 ; ARM-NEXT: push {r4, lr}
140 ; ARM-NEXT: movs r2, #15
141 ; ARM-NEXT: ands r2, r1
142 ; ARM-NEXT: lsls r0, r0, #28
143 ; ARM-NEXT: movs r4, #0
144 ; ARM-NEXT: mov r1, r4
145 ; ARM-NEXT: mov r3, r4
146 ; ARM-NEXT: bl __aeabi_lmul
147 ; ARM-NEXT: cmp r1, #3
148 ; ARM-NEXT: bhi .LBB2_2
149 ; ARM-NEXT: @ %bb.1:
150 ; ARM-NEXT: lsrs r0, r0, #2
151 ; ARM-NEXT: lsls r1, r1, #30
152 ; ARM-NEXT: adds r0, r1, r0
153 ; ARM-NEXT: lsrs r0, r0, #28
154 ; ARM-NEXT: pop {r4, pc}
155 ; ARM-NEXT: .LBB2_2:
156 ; ARM-NEXT: mvns r0, r4
157 ; ARM-NEXT: lsrs r0, r0, #28
158 ; ARM-NEXT: pop {r4, pc}
159 %tmp = call i4 @llvm.umul.fix.sat.i4(i4 %x, i4 %y, i32 2)
160 ret i4 %tmp
161 }
163 ;; These result in regular integer multiplication with a saturation check.
164 define i32 @func4(i32 %x, i32 %y) nounwind {
165 ; ARM-LABEL: func4:
166 ; ARM: @ %bb.0:
167 ; ARM-NEXT: .save {r4, lr}
168 ; ARM-NEXT: push {r4, lr}
169 ; ARM-NEXT: mov r2, r1
170 ; ARM-NEXT: movs r4, #0
171 ; ARM-NEXT: mov r1, r4
172 ; ARM-NEXT: mov r3, r4
173 ; ARM-NEXT: bl __aeabi_lmul
174 ; ARM-NEXT: cmp r1, #0
175 ; ARM-NEXT: bls .LBB3_2
176 ; ARM-NEXT: @ %bb.1:
177 ; ARM-NEXT: mvns r0, r4
178 ; ARM-NEXT: .LBB3_2:
179 ; ARM-NEXT: pop {r4, pc}
180 %tmp = call i32 @llvm.umul.fix.sat.i32(i32 %x, i32 %y, i32 0)
181 ret i32 %tmp
182 }
184 define i64 @func5(i64 %x, i64 %y) {
185 ; ARM-LABEL: func5:
186 ; ARM: @ %bb.0:
187 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
188 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
189 ; ARM-NEXT: .pad #12
190 ; ARM-NEXT: sub sp, #12
191 ; ARM-NEXT: mov r6, r3
192 ; ARM-NEXT: str r2, [sp, #8] @ 4-byte Spill
193 ; ARM-NEXT: mov r4, r1
194 ; ARM-NEXT: mov r2, r0
195 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
196 ; ARM-NEXT: movs r5, #0
197 ; ARM-NEXT: mov r0, r3
198 ; ARM-NEXT: mov r1, r5
199 ; ARM-NEXT: mov r3, r5
200 ; ARM-NEXT: bl __aeabi_lmul
201 ; ARM-NEXT: str r0, [sp] @ 4-byte Spill
202 ; ARM-NEXT: mov r7, r1
203 ; ARM-NEXT: subs r0, r1, #1
204 ; ARM-NEXT: sbcs r7, r0
205 ; ARM-NEXT: mov r0, r4
206 ; ARM-NEXT: mov r1, r5
207 ; ARM-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
208 ; ARM-NEXT: mov r3, r5
209 ; ARM-NEXT: bl __aeabi_lmul
210 ; ARM-NEXT: subs r2, r1, #1
211 ; ARM-NEXT: sbcs r1, r2
212 ; ARM-NEXT: subs r2, r6, #1
213 ; ARM-NEXT: sbcs r6, r2
214 ; ARM-NEXT: subs r2, r4, #1
215 ; ARM-NEXT: sbcs r4, r2
216 ; ARM-NEXT: ands r4, r6
217 ; ARM-NEXT: orrs r4, r1
218 ; ARM-NEXT: orrs r4, r7
219 ; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload
220 ; ARM-NEXT: adds r6, r0, r1
221 ; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
222 ; ARM-NEXT: mov r1, r5
223 ; ARM-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
224 ; ARM-NEXT: mov r3, r5
225 ; ARM-NEXT: bl __aeabi_lmul
226 ; ARM-NEXT: adds r3, r1, r6
227 ; ARM-NEXT: mov r2, r5
228 ; ARM-NEXT: adcs r2, r5
229 ; ARM-NEXT: orrs r2, r4
230 ; ARM-NEXT: mvns r1, r5
231 ; ARM-NEXT: cmp r2, #0
232 ; ARM-NEXT: mov r2, r1
233 ; ARM-NEXT: bne .LBB4_2
234 ; ARM-NEXT: @ %bb.1:
235 ; ARM-NEXT: mov r2, r0
236 ; ARM-NEXT: .LBB4_2:
237 ; ARM-NEXT: bne .LBB4_4
238 ; ARM-NEXT: @ %bb.3:
239 ; ARM-NEXT: mov r1, r3
240 ; ARM-NEXT: .LBB4_4:
241 ; ARM-NEXT: mov r0, r2
242 ; ARM-NEXT: add sp, #12
243 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
244 %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 0)
245 ret i64 %tmp
246 }
248 define i4 @func6(i4 %x, i4 %y) nounwind {
249 ; ARM-LABEL: func6:
250 ; ARM: @ %bb.0:
251 ; ARM-NEXT: .save {r4, lr}
252 ; ARM-NEXT: push {r4, lr}
253 ; ARM-NEXT: movs r2, #15
254 ; ARM-NEXT: ands r2, r1
255 ; ARM-NEXT: lsls r0, r0, #28
256 ; ARM-NEXT: movs r4, #0
257 ; ARM-NEXT: mov r1, r4
258 ; ARM-NEXT: mov r3, r4
259 ; ARM-NEXT: bl __aeabi_lmul
260 ; ARM-NEXT: cmp r1, #0
261 ; ARM-NEXT: bls .LBB5_2
262 ; ARM-NEXT: @ %bb.1:
263 ; ARM-NEXT: mvns r0, r4
264 ; ARM-NEXT: .LBB5_2:
265 ; ARM-NEXT: lsrs r0, r0, #28
266 ; ARM-NEXT: pop {r4, pc}
267 %tmp = call i4 @llvm.umul.fix.sat.i4(i4 %x, i4 %y, i32 0)
268 ret i4 %tmp
269 }
271 define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {
272 ; ARM-LABEL: vec2:
273 ; ARM: @ %bb.0:
274 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
275 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
276 ; ARM-NEXT: .pad #12
277 ; ARM-NEXT: sub sp, #12
278 ; ARM-NEXT: str r3, [sp, #8] @ 4-byte Spill
279 ; ARM-NEXT: mov r7, r2
280 ; ARM-NEXT: mov r5, r1
281 ; ARM-NEXT: ldr r2, [sp, #32]
282 ; ARM-NEXT: movs r6, #0
283 ; ARM-NEXT: mov r1, r6
284 ; ARM-NEXT: mov r3, r6
285 ; ARM-NEXT: bl __aeabi_lmul
286 ; ARM-NEXT: mvns r4, r6
287 ; ARM-NEXT: cmp r1, #0
288 ; ARM-NEXT: mov r1, r4
289 ; ARM-NEXT: bhi .LBB6_2
290 ; ARM-NEXT: @ %bb.1:
291 ; ARM-NEXT: mov r1, r0
292 ; ARM-NEXT: .LBB6_2:
293 ; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
294 ; ARM-NEXT: ldr r2, [sp, #36]
295 ; ARM-NEXT: mov r0, r5
296 ; ARM-NEXT: mov r1, r6
297 ; ARM-NEXT: mov r3, r6
298 ; ARM-NEXT: bl __aeabi_lmul
299 ; ARM-NEXT: cmp r1, #0
300 ; ARM-NEXT: mov r5, r4
301 ; ARM-NEXT: bhi .LBB6_4
302 ; ARM-NEXT: @ %bb.3:
303 ; ARM-NEXT: mov r5, r0
304 ; ARM-NEXT: .LBB6_4:
305 ; ARM-NEXT: ldr r2, [sp, #40]
306 ; ARM-NEXT: mov r0, r7
307 ; ARM-NEXT: mov r1, r6
308 ; ARM-NEXT: mov r3, r6
309 ; ARM-NEXT: bl __aeabi_lmul
310 ; ARM-NEXT: cmp r1, #0
311 ; ARM-NEXT: mov r7, r4
312 ; ARM-NEXT: bhi .LBB6_6
313 ; ARM-NEXT: @ %bb.5:
314 ; ARM-NEXT: mov r7, r0
315 ; ARM-NEXT: .LBB6_6:
316 ; ARM-NEXT: ldr r2, [sp, #44]
317 ; ARM-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
318 ; ARM-NEXT: mov r1, r6
319 ; ARM-NEXT: mov r3, r6
320 ; ARM-NEXT: bl __aeabi_lmul
321 ; ARM-NEXT: cmp r1, #0
322 ; ARM-NEXT: bhi .LBB6_8
323 ; ARM-NEXT: @ %bb.7:
324 ; ARM-NEXT: mov r4, r0
325 ; ARM-NEXT: .LBB6_8:
326 ; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
327 ; ARM-NEXT: mov r1, r5
328 ; ARM-NEXT: mov r2, r7
329 ; ARM-NEXT: mov r3, r4
330 ; ARM-NEXT: add sp, #12
331 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
332 %tmp = call <4 x i32> @llvm.umul.fix.sat.v4i32(<4 x i32> %x, <4 x i32> %y, i32 0)
333 ret <4 x i32> %tmp
334 }
336 define i64 @func7(i64 %x, i64 %y) nounwind {
337 ; ARM-LABEL: func7:
338 ; ARM: @ %bb.0:
339 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
340 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
341 ; ARM-NEXT: .pad #28
342 ; ARM-NEXT: sub sp, #28
343 ; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill
344 ; ARM-NEXT: mov r7, r2
345 ; ARM-NEXT: str r2, [sp, #20] @ 4-byte Spill
346 ; ARM-NEXT: mov r5, r1
347 ; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill
348 ; ARM-NEXT: movs r4, #0
349 ; ARM-NEXT: mov r6, r0
350 ; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
351 ; ARM-NEXT: mov r1, r4
352 ; ARM-NEXT: mov r3, r4
353 ; ARM-NEXT: bl __aeabi_lmul
354 ; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill
355 ; ARM-NEXT: mov r0, r5
356 ; ARM-NEXT: mov r1, r4
357 ; ARM-NEXT: mov r2, r7
358 ; ARM-NEXT: mov r3, r4
359 ; ARM-NEXT: bl __aeabi_lmul
360 ; ARM-NEXT: mov r7, r1
361 ; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
362 ; ARM-NEXT: adds r5, r0, r1
363 ; ARM-NEXT: adcs r7, r4
364 ; ARM-NEXT: mov r0, r6
365 ; ARM-NEXT: mov r1, r4
366 ; ARM-NEXT: ldr r6, [sp, #24] @ 4-byte Reload
367 ; ARM-NEXT: mov r2, r6
368 ; ARM-NEXT: mov r3, r4
369 ; ARM-NEXT: bl __aeabi_lmul
370 ; ARM-NEXT: adds r0, r0, r5
371 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
372 ; ARM-NEXT: adcs r1, r4
373 ; ARM-NEXT: adds r0, r7, r1
374 ; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
375 ; ARM-NEXT: mov r5, r4
376 ; ARM-NEXT: adcs r5, r4
377 ; ARM-NEXT: ldr r7, [sp, #12] @ 4-byte Reload
378 ; ARM-NEXT: mov r0, r7
379 ; ARM-NEXT: mov r1, r4
380 ; ARM-NEXT: mov r2, r6
381 ; ARM-NEXT: mov r3, r4
382 ; ARM-NEXT: bl __aeabi_lmul
383 ; ARM-NEXT: mov r6, r1
384 ; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
385 ; ARM-NEXT: adds r0, r0, r1
386 ; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
387 ; ARM-NEXT: adcs r6, r5
388 ; ARM-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
389 ; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
390 ; ARM-NEXT: mov r2, r4
391 ; ARM-NEXT: mov r3, r4
392 ; ARM-NEXT: bl __aeabi_lmul
393 ; ARM-NEXT: mov r5, r0
394 ; ARM-NEXT: str r1, [sp, #24] @ 4-byte Spill
395 ; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
396 ; ARM-NEXT: mov r1, r7
397 ; ARM-NEXT: mov r2, r4
398 ; ARM-NEXT: mov r3, r4
399 ; ARM-NEXT: bl __aeabi_lmul
400 ; ARM-NEXT: mov r2, r1
401 ; ARM-NEXT: adds r0, r0, r5
402 ; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
403 ; ARM-NEXT: adcs r2, r1
404 ; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
405 ; ARM-NEXT: adds r3, r1, r0
406 ; ARM-NEXT: adcs r2, r6
407 ; ARM-NEXT: mvns r1, r4
408 ; ARM-NEXT: cmp r2, #0
409 ; ARM-NEXT: mov r0, r1
410 ; ARM-NEXT: beq .LBB7_3
411 ; ARM-NEXT: @ %bb.1:
412 ; ARM-NEXT: beq .LBB7_4
413 ; ARM-NEXT: .LBB7_2:
414 ; ARM-NEXT: add sp, #28
415 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
416 ; ARM-NEXT: .LBB7_3:
417 ; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
418 ; ARM-NEXT: bne .LBB7_2
419 ; ARM-NEXT: .LBB7_4:
420 ; ARM-NEXT: mov r1, r3
421 ; ARM-NEXT: add sp, #28
422 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
423 %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 32)
424 ret i64 %tmp
425 }
427 define i64 @func8(i64 %x, i64 %y) nounwind {
428 ; ARM-LABEL: func8:
429 ; ARM: @ %bb.0:
430 ; ARM-NEXT: .save {r4, r5, r6, r7, lr}
431 ; ARM-NEXT: push {r4, r5, r6, r7, lr}
432 ; ARM-NEXT: .pad #28
433 ; ARM-NEXT: sub sp, #28
434 ; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill
435 ; ARM-NEXT: mov r7, r2
436 ; ARM-NEXT: str r2, [sp, #16] @ 4-byte Spill
437 ; ARM-NEXT: mov r5, r1
438 ; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill
439 ; ARM-NEXT: movs r4, #0
440 ; ARM-NEXT: mov r6, r0
441 ; ARM-NEXT: str r0, [sp, #12] @ 4-byte Spill
442 ; ARM-NEXT: mov r1, r4
443 ; ARM-NEXT: mov r3, r4
444 ; ARM-NEXT: bl __aeabi_lmul
445 ; ARM-NEXT: str r1, [sp, #20] @ 4-byte Spill
446 ; ARM-NEXT: mov r0, r5
447 ; ARM-NEXT: mov r1, r4
448 ; ARM-NEXT: mov r2, r7
449 ; ARM-NEXT: mov r3, r4
450 ; ARM-NEXT: bl __aeabi_lmul
451 ; ARM-NEXT: mov r7, r1
452 ; ARM-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
453 ; ARM-NEXT: adds r5, r0, r1
454 ; ARM-NEXT: adcs r7, r4
455 ; ARM-NEXT: mov r0, r6
456 ; ARM-NEXT: mov r1, r4
457 ; ARM-NEXT: ldr r6, [sp, #24] @ 4-byte Reload
458 ; ARM-NEXT: mov r2, r6
459 ; ARM-NEXT: mov r3, r4
460 ; ARM-NEXT: bl __aeabi_lmul
461 ; ARM-NEXT: adds r0, r0, r5
462 ; ARM-NEXT: str r0, [sp, #20] @ 4-byte Spill
463 ; ARM-NEXT: adcs r1, r4
464 ; ARM-NEXT: adds r0, r7, r1
465 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
466 ; ARM-NEXT: mov r5, r4
467 ; ARM-NEXT: adcs r5, r4
468 ; ARM-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
469 ; ARM-NEXT: mov r0, r7
470 ; ARM-NEXT: mov r1, r4
471 ; ARM-NEXT: mov r2, r6
472 ; ARM-NEXT: mov r3, r4
473 ; ARM-NEXT: bl __aeabi_lmul
474 ; ARM-NEXT: mov r6, r1
475 ; ARM-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
476 ; ARM-NEXT: adds r0, r0, r1
477 ; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
478 ; ARM-NEXT: adcs r6, r5
479 ; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
480 ; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
481 ; ARM-NEXT: mov r2, r4
482 ; ARM-NEXT: mov r3, r4
483 ; ARM-NEXT: bl __aeabi_lmul
484 ; ARM-NEXT: mov r5, r0
485 ; ARM-NEXT: str r1, [sp, #24] @ 4-byte Spill
486 ; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
487 ; ARM-NEXT: mov r1, r7
488 ; ARM-NEXT: mov r2, r4
489 ; ARM-NEXT: mov r3, r4
490 ; ARM-NEXT: bl __aeabi_lmul
491 ; ARM-NEXT: adds r0, r0, r5
492 ; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
493 ; ARM-NEXT: adcs r1, r2
494 ; ARM-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
495 ; ARM-NEXT: adds r0, r2, r0
496 ; ARM-NEXT: adcs r1, r6
497 ; ARM-NEXT: lsls r1, r1, #1
498 ; ARM-NEXT: lsrs r5, r0, #31
499 ; ARM-NEXT: adds r2, r1, r5
500 ; ARM-NEXT: lsls r0, r0, #1
501 ; ARM-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
502 ; ARM-NEXT: lsrs r1, r1, #31
503 ; ARM-NEXT: adds r3, r0, r1
504 ; ARM-NEXT: mvns r1, r4
505 ; ARM-NEXT: cmp r5, #0
506 ; ARM-NEXT: mov r0, r1
507 ; ARM-NEXT: beq .LBB8_3
508 ; ARM-NEXT: @ %bb.1:
509 ; ARM-NEXT: beq .LBB8_4
510 ; ARM-NEXT: .LBB8_2:
511 ; ARM-NEXT: add sp, #28
512 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
513 ; ARM-NEXT: .LBB8_3:
514 ; ARM-NEXT: mov r0, r3
515 ; ARM-NEXT: bne .LBB8_2
516 ; ARM-NEXT: .LBB8_4:
517 ; ARM-NEXT: mov r1, r2
518 ; ARM-NEXT: add sp, #28
519 ; ARM-NEXT: pop {r4, r5, r6, r7, pc}
520 %tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 63)
521 ret i64 %tmp
522 }