| blob | 0d0e45956080def6371bc35bf367ace7325b6bd8 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-LE
3 ; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-BE
5 define arm_aapcs_vfpcc <4 x i32> @bitcast_to_v4i1(i4 %b, <4 x i32> %a) {
6 ; CHECK-LE-LABEL: bitcast_to_v4i1:
7 ; CHECK-LE: @ %bb.0: @ %entry
8 ; CHECK-LE-NEXT: .pad #4
9 ; CHECK-LE-NEXT: sub sp, #4
10 ; CHECK-LE-NEXT: and r0, r0, #15
11 ; CHECK-LE-NEXT: vmov.i8 q1, #0x0
12 ; CHECK-LE-NEXT: vmov.i8 q2, #0xff
13 ; CHECK-LE-NEXT: vmsr p0, r0
14 ; CHECK-LE-NEXT: vpsel q1, q2, q1
15 ; CHECK-LE-NEXT: vmov.u8 r0, q1[2]
16 ; CHECK-LE-NEXT: vmov.u8 r1, q1[0]
17 ; CHECK-LE-NEXT: vmov q2[2], q2[0], r1, r0
18 ; CHECK-LE-NEXT: vmov.u8 r0, q1[3]
19 ; CHECK-LE-NEXT: vmov.u8 r1, q1[1]
20 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
21 ; CHECK-LE-NEXT: vmov q2[3], q2[1], r1, r0
22 ; CHECK-LE-NEXT: vcmp.i32 ne, q2, zr
23 ; CHECK-LE-NEXT: vpsel q0, q0, q1
24 ; CHECK-LE-NEXT: add sp, #4
25 ; CHECK-LE-NEXT: bx lr
26 ;
27 ; CHECK-BE-LABEL: bitcast_to_v4i1:
28 ; CHECK-BE: @ %bb.0: @ %entry
29 ; CHECK-BE-NEXT: .pad #4
30 ; CHECK-BE-NEXT: sub sp, #4
31 ; CHECK-BE-NEXT: rbit r0, r0
32 ; CHECK-BE-NEXT: vmov.i8 q1, #0x0
33 ; CHECK-BE-NEXT: vmov.i8 q2, #0xff
34 ; CHECK-BE-NEXT: lsrs r0, r0, #28
35 ; CHECK-BE-NEXT: vmsr p0, r0
36 ; CHECK-BE-NEXT: vpsel q1, q2, q1
37 ; CHECK-BE-NEXT: vmov.u8 r0, q1[2]
38 ; CHECK-BE-NEXT: vmov.u8 r1, q1[0]
39 ; CHECK-BE-NEXT: vmov q2[2], q2[0], r1, r0
40 ; CHECK-BE-NEXT: vmov.u8 r0, q1[3]
41 ; CHECK-BE-NEXT: vmov.u8 r1, q1[1]
42 ; CHECK-BE-NEXT: vrev64.32 q1, q0
43 ; CHECK-BE-NEXT: vmov q2[3], q2[1], r1, r0
44 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
45 ; CHECK-BE-NEXT: vcmp.i32 ne, q2, zr
46 ; CHECK-BE-NEXT: vpsel q1, q1, q0
47 ; CHECK-BE-NEXT: vrev64.32 q0, q1
48 ; CHECK-BE-NEXT: add sp, #4
49 ; CHECK-BE-NEXT: bx lr
50 entry:
51 %c = bitcast i4 %b to <4 x i1>
52 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
53 ret <4 x i32> %s
54 }
56 define arm_aapcs_vfpcc <8 x i16> @bitcast_to_v8i1(i8 %b, <8 x i16> %a) {
57 ; CHECK-LE-LABEL: bitcast_to_v8i1:
58 ; CHECK-LE: @ %bb.0: @ %entry
59 ; CHECK-LE-NEXT: .pad #4
60 ; CHECK-LE-NEXT: sub sp, #4
61 ; CHECK-LE-NEXT: uxtb r0, r0
62 ; CHECK-LE-NEXT: vmov.i8 q1, #0x0
63 ; CHECK-LE-NEXT: vmov.i8 q2, #0xff
64 ; CHECK-LE-NEXT: vmsr p0, r0
65 ; CHECK-LE-NEXT: vpsel q2, q2, q1
66 ; CHECK-LE-NEXT: vmov.u8 r0, q2[0]
67 ; CHECK-LE-NEXT: vmov.16 q1[0], r0
68 ; CHECK-LE-NEXT: vmov.u8 r0, q2[1]
69 ; CHECK-LE-NEXT: vmov.16 q1[1], r0
70 ; CHECK-LE-NEXT: vmov.u8 r0, q2[2]
71 ; CHECK-LE-NEXT: vmov.16 q1[2], r0
72 ; CHECK-LE-NEXT: vmov.u8 r0, q2[3]
73 ; CHECK-LE-NEXT: vmov.16 q1[3], r0
74 ; CHECK-LE-NEXT: vmov.u8 r0, q2[4]
75 ; CHECK-LE-NEXT: vmov.16 q1[4], r0
76 ; CHECK-LE-NEXT: vmov.u8 r0, q2[5]
77 ; CHECK-LE-NEXT: vmov.16 q1[5], r0
78 ; CHECK-LE-NEXT: vmov.u8 r0, q2[6]
79 ; CHECK-LE-NEXT: vmov.16 q1[6], r0
80 ; CHECK-LE-NEXT: vmov.u8 r0, q2[7]
81 ; CHECK-LE-NEXT: vmov.16 q1[7], r0
82 ; CHECK-LE-NEXT: vcmp.i16 ne, q1, zr
83 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
84 ; CHECK-LE-NEXT: vpsel q0, q0, q1
85 ; CHECK-LE-NEXT: add sp, #4
86 ; CHECK-LE-NEXT: bx lr
87 ;
88 ; CHECK-BE-LABEL: bitcast_to_v8i1:
89 ; CHECK-BE: @ %bb.0: @ %entry
90 ; CHECK-BE-NEXT: .pad #4
91 ; CHECK-BE-NEXT: sub sp, #4
92 ; CHECK-BE-NEXT: uxtb r0, r0
93 ; CHECK-BE-NEXT: vmov.i8 q1, #0x0
94 ; CHECK-BE-NEXT: rbit r0, r0
95 ; CHECK-BE-NEXT: vmov.i8 q2, #0xff
96 ; CHECK-BE-NEXT: lsrs r0, r0, #24
97 ; CHECK-BE-NEXT: vmsr p0, r0
98 ; CHECK-BE-NEXT: vpsel q2, q2, q1
99 ; CHECK-BE-NEXT: vmov.u8 r0, q2[0]
100 ; CHECK-BE-NEXT: vmov.16 q1[0], r0
101 ; CHECK-BE-NEXT: vmov.u8 r0, q2[1]
102 ; CHECK-BE-NEXT: vmov.16 q1[1], r0
103 ; CHECK-BE-NEXT: vmov.u8 r0, q2[2]
104 ; CHECK-BE-NEXT: vmov.16 q1[2], r0
105 ; CHECK-BE-NEXT: vmov.u8 r0, q2[3]
106 ; CHECK-BE-NEXT: vmov.16 q1[3], r0
107 ; CHECK-BE-NEXT: vmov.u8 r0, q2[4]
108 ; CHECK-BE-NEXT: vmov.16 q1[4], r0
109 ; CHECK-BE-NEXT: vmov.u8 r0, q2[5]
110 ; CHECK-BE-NEXT: vmov.16 q1[5], r0
111 ; CHECK-BE-NEXT: vmov.u8 r0, q2[6]
112 ; CHECK-BE-NEXT: vmov.16 q1[6], r0
113 ; CHECK-BE-NEXT: vmov.u8 r0, q2[7]
114 ; CHECK-BE-NEXT: vmov.16 q1[7], r0
115 ; CHECK-BE-NEXT: vcmp.i16 ne, q1, zr
116 ; CHECK-BE-NEXT: vrev64.16 q1, q0
117 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
118 ; CHECK-BE-NEXT: vpsel q1, q1, q0
119 ; CHECK-BE-NEXT: vrev64.16 q0, q1
120 ; CHECK-BE-NEXT: add sp, #4
121 ; CHECK-BE-NEXT: bx lr
122 entry:
123 %c = bitcast i8 %b to <8 x i1>
124 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> zeroinitializer
125 ret <8 x i16> %s
126 }
128 define arm_aapcs_vfpcc <16 x i8> @bitcast_to_v16i1(i16 %b, <16 x i8> %a) {
129 ; CHECK-LE-LABEL: bitcast_to_v16i1:
130 ; CHECK-LE: @ %bb.0: @ %entry
131 ; CHECK-LE-NEXT: .pad #4
132 ; CHECK-LE-NEXT: sub sp, #4
133 ; CHECK-LE-NEXT: vmsr p0, r0
134 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
135 ; CHECK-LE-NEXT: vpsel q0, q0, q1
136 ; CHECK-LE-NEXT: add sp, #4
137 ; CHECK-LE-NEXT: bx lr
138 ;
139 ; CHECK-BE-LABEL: bitcast_to_v16i1:
140 ; CHECK-BE: @ %bb.0: @ %entry
141 ; CHECK-BE-NEXT: .pad #4
142 ; CHECK-BE-NEXT: sub sp, #4
143 ; CHECK-BE-NEXT: uxth r0, r0
144 ; CHECK-BE-NEXT: vrev64.8 q1, q0
145 ; CHECK-BE-NEXT: rbit r0, r0
146 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
147 ; CHECK-BE-NEXT: lsrs r0, r0, #16
148 ; CHECK-BE-NEXT: vmsr p0, r0
149 ; CHECK-BE-NEXT: vpsel q1, q1, q0
150 ; CHECK-BE-NEXT: vrev64.8 q0, q1
151 ; CHECK-BE-NEXT: add sp, #4
152 ; CHECK-BE-NEXT: bx lr
153 entry:
154 %c = bitcast i16 %b to <16 x i1>
155 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> zeroinitializer
156 ret <16 x i8> %s
157 }
159 define arm_aapcs_vfpcc <2 x i64> @bitcast_to_v2i1(i2 %b, <2 x i64> %a) {
160 ; CHECK-LE-LABEL: bitcast_to_v2i1:
161 ; CHECK-LE: @ %bb.0: @ %entry
162 ; CHECK-LE-NEXT: .pad #4
163 ; CHECK-LE-NEXT: sub sp, #4
164 ; CHECK-LE-NEXT: and r0, r0, #3
165 ; CHECK-LE-NEXT: vmov.i8 q1, #0x0
166 ; CHECK-LE-NEXT: vmov.i8 q2, #0xff
167 ; CHECK-LE-NEXT: vmsr p0, r0
168 ; CHECK-LE-NEXT: vpsel q1, q2, q1
169 ; CHECK-LE-NEXT: vmov.u8 r0, q1[1]
170 ; CHECK-LE-NEXT: vmov.u8 r1, q1[0]
171 ; CHECK-LE-NEXT: vmov q1[2], q1[0], r1, r0
172 ; CHECK-LE-NEXT: vmov q1[3], q1[1], r1, r0
173 ; CHECK-LE-NEXT: vcmp.i32 ne, q1, zr
174 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
175 ; CHECK-LE-NEXT: vpsel q0, q0, q1
176 ; CHECK-LE-NEXT: add sp, #4
177 ; CHECK-LE-NEXT: bx lr
178 ;
179 ; CHECK-BE-LABEL: bitcast_to_v2i1:
180 ; CHECK-BE: @ %bb.0: @ %entry
181 ; CHECK-BE-NEXT: .pad #4
182 ; CHECK-BE-NEXT: sub sp, #4
183 ; CHECK-BE-NEXT: rbit r0, r0
184 ; CHECK-BE-NEXT: vmov.i8 q1, #0x0
185 ; CHECK-BE-NEXT: vmov.i8 q2, #0xff
186 ; CHECK-BE-NEXT: lsrs r0, r0, #30
187 ; CHECK-BE-NEXT: vmsr p0, r0
188 ; CHECK-BE-NEXT: vpsel q1, q2, q1
189 ; CHECK-BE-NEXT: vmov.u8 r0, q1[1]
190 ; CHECK-BE-NEXT: vmov.u8 r1, q1[0]
191 ; CHECK-BE-NEXT: vmov q1[2], q1[0], r1, r0
192 ; CHECK-BE-NEXT: vmov q1[3], q1[1], r1, r0
193 ; CHECK-BE-NEXT: vcmp.i32 ne, q1, zr
194 ; CHECK-BE-NEXT: vmov.i32 q1, #0x0
195 ; CHECK-BE-NEXT: vpsel q0, q0, q1
196 ; CHECK-BE-NEXT: add sp, #4
197 ; CHECK-BE-NEXT: bx lr
198 entry:
199 %c = bitcast i2 %b to <2 x i1>
200 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> zeroinitializer
201 ret <2 x i64> %s
202 }
205 define arm_aapcs_vfpcc i4 @bitcast_from_v4i1(<4 x i32> %a) {
206 ; CHECK-LE-LABEL: bitcast_from_v4i1:
207 ; CHECK-LE: @ %bb.0: @ %entry
208 ; CHECK-LE-NEXT: .pad #4
209 ; CHECK-LE-NEXT: sub sp, #4
210 ; CHECK-LE-NEXT: vcmp.i32 eq, q0, zr
211 ; CHECK-LE-NEXT: vmrs r1, p0
212 ; CHECK-LE-NEXT: and r0, r1, #1
213 ; CHECK-LE-NEXT: rsbs r2, r0, #0
214 ; CHECK-LE-NEXT: movs r0, #0
215 ; CHECK-LE-NEXT: bfi r0, r2, #0, #1
216 ; CHECK-LE-NEXT: ubfx r2, r1, #4, #1
217 ; CHECK-LE-NEXT: rsbs r2, r2, #0
218 ; CHECK-LE-NEXT: bfi r0, r2, #1, #1
219 ; CHECK-LE-NEXT: ubfx r2, r1, #8, #1
220 ; CHECK-LE-NEXT: ubfx r1, r1, #12, #1
221 ; CHECK-LE-NEXT: rsbs r2, r2, #0
222 ; CHECK-LE-NEXT: bfi r0, r2, #2, #1
223 ; CHECK-LE-NEXT: rsbs r1, r1, #0
224 ; CHECK-LE-NEXT: bfi r0, r1, #3, #1
225 ; CHECK-LE-NEXT: add sp, #4
226 ; CHECK-LE-NEXT: bx lr
227 ;
228 ; CHECK-BE-LABEL: bitcast_from_v4i1:
229 ; CHECK-BE: @ %bb.0: @ %entry
230 ; CHECK-BE-NEXT: .pad #4
231 ; CHECK-BE-NEXT: sub sp, #4
232 ; CHECK-BE-NEXT: vrev64.32 q1, q0
233 ; CHECK-BE-NEXT: vcmp.i32 eq, q1, zr
234 ; CHECK-BE-NEXT: vmrs r1, p0
235 ; CHECK-BE-NEXT: ubfx r0, r1, #12, #1
236 ; CHECK-BE-NEXT: rsbs r2, r0, #0
237 ; CHECK-BE-NEXT: movs r0, #0
238 ; CHECK-BE-NEXT: bfi r0, r2, #0, #1
239 ; CHECK-BE-NEXT: ubfx r2, r1, #8, #1
240 ; CHECK-BE-NEXT: rsbs r2, r2, #0
241 ; CHECK-BE-NEXT: bfi r0, r2, #1, #1
242 ; CHECK-BE-NEXT: ubfx r2, r1, #4, #1
243 ; CHECK-BE-NEXT: and r1, r1, #1
244 ; CHECK-BE-NEXT: rsbs r2, r2, #0
245 ; CHECK-BE-NEXT: bfi r0, r2, #2, #1
246 ; CHECK-BE-NEXT: rsbs r1, r1, #0
247 ; CHECK-BE-NEXT: bfi r0, r1, #3, #1
248 ; CHECK-BE-NEXT: add sp, #4
249 ; CHECK-BE-NEXT: bx lr
250 entry:
251 %c = icmp eq <4 x i32> %a, zeroinitializer
252 %b = bitcast <4 x i1> %c to i4
253 ret i4 %b
254 }
256 define arm_aapcs_vfpcc i8 @bitcast_from_v8i1(<8 x i16> %a) {
257 ; CHECK-LE-LABEL: bitcast_from_v8i1:
258 ; CHECK-LE: @ %bb.0: @ %entry
259 ; CHECK-LE-NEXT: .pad #4
260 ; CHECK-LE-NEXT: sub sp, #4
261 ; CHECK-LE-NEXT: vcmp.i16 eq, q0, zr
262 ; CHECK-LE-NEXT: vmrs r1, p0
263 ; CHECK-LE-NEXT: and r0, r1, #1
264 ; CHECK-LE-NEXT: rsbs r2, r0, #0
265 ; CHECK-LE-NEXT: movs r0, #0
266 ; CHECK-LE-NEXT: bfi r0, r2, #0, #1
267 ; CHECK-LE-NEXT: ubfx r2, r1, #2, #1
268 ; CHECK-LE-NEXT: rsbs r2, r2, #0
269 ; CHECK-LE-NEXT: bfi r0, r2, #1, #1
270 ; CHECK-LE-NEXT: ubfx r2, r1, #4, #1
271 ; CHECK-LE-NEXT: rsbs r2, r2, #0
272 ; CHECK-LE-NEXT: bfi r0, r2, #2, #1
273 ; CHECK-LE-NEXT: ubfx r2, r1, #6, #1
274 ; CHECK-LE-NEXT: rsbs r2, r2, #0
275 ; CHECK-LE-NEXT: bfi r0, r2, #3, #1
276 ; CHECK-LE-NEXT: ubfx r2, r1, #8, #1
277 ; CHECK-LE-NEXT: rsbs r2, r2, #0
278 ; CHECK-LE-NEXT: bfi r0, r2, #4, #1
279 ; CHECK-LE-NEXT: ubfx r2, r1, #10, #1
280 ; CHECK-LE-NEXT: rsbs r2, r2, #0
281 ; CHECK-LE-NEXT: bfi r0, r2, #5, #1
282 ; CHECK-LE-NEXT: ubfx r2, r1, #12, #1
283 ; CHECK-LE-NEXT: ubfx r1, r1, #14, #1
284 ; CHECK-LE-NEXT: rsbs r2, r2, #0
285 ; CHECK-LE-NEXT: bfi r0, r2, #6, #1
286 ; CHECK-LE-NEXT: rsbs r1, r1, #0
287 ; CHECK-LE-NEXT: bfi r0, r1, #7, #1
288 ; CHECK-LE-NEXT: uxtb r0, r0
289 ; CHECK-LE-NEXT: add sp, #4
290 ; CHECK-LE-NEXT: bx lr
291 ;
292 ; CHECK-BE-LABEL: bitcast_from_v8i1:
293 ; CHECK-BE: @ %bb.0: @ %entry
294 ; CHECK-BE-NEXT: .pad #4
295 ; CHECK-BE-NEXT: sub sp, #4
296 ; CHECK-BE-NEXT: vrev64.16 q1, q0
297 ; CHECK-BE-NEXT: vcmp.i16 eq, q1, zr
298 ; CHECK-BE-NEXT: vmrs r1, p0
299 ; CHECK-BE-NEXT: ubfx r0, r1, #14, #1
300 ; CHECK-BE-NEXT: rsbs r2, r0, #0
301 ; CHECK-BE-NEXT: movs r0, #0
302 ; CHECK-BE-NEXT: bfi r0, r2, #0, #1
303 ; CHECK-BE-NEXT: ubfx r2, r1, #12, #1
304 ; CHECK-BE-NEXT: rsbs r2, r2, #0
305 ; CHECK-BE-NEXT: bfi r0, r2, #1, #1
306 ; CHECK-BE-NEXT: ubfx r2, r1, #10, #1
307 ; CHECK-BE-NEXT: rsbs r2, r2, #0
308 ; CHECK-BE-NEXT: bfi r0, r2, #2, #1
309 ; CHECK-BE-NEXT: ubfx r2, r1, #8, #1
310 ; CHECK-BE-NEXT: rsbs r2, r2, #0
311 ; CHECK-BE-NEXT: bfi r0, r2, #3, #1
312 ; CHECK-BE-NEXT: ubfx r2, r1, #6, #1
313 ; CHECK-BE-NEXT: rsbs r2, r2, #0
314 ; CHECK-BE-NEXT: bfi r0, r2, #4, #1
315 ; CHECK-BE-NEXT: ubfx r2, r1, #4, #1
316 ; CHECK-BE-NEXT: rsbs r2, r2, #0
317 ; CHECK-BE-NEXT: bfi r0, r2, #5, #1
318 ; CHECK-BE-NEXT: ubfx r2, r1, #2, #1
319 ; CHECK-BE-NEXT: and r1, r1, #1
320 ; CHECK-BE-NEXT: rsbs r2, r2, #0
321 ; CHECK-BE-NEXT: bfi r0, r2, #6, #1
322 ; CHECK-BE-NEXT: rsbs r1, r1, #0
323 ; CHECK-BE-NEXT: bfi r0, r1, #7, #1
324 ; CHECK-BE-NEXT: uxtb r0, r0
325 ; CHECK-BE-NEXT: add sp, #4
326 ; CHECK-BE-NEXT: bx lr
327 entry:
328 %c = icmp eq <8 x i16> %a, zeroinitializer
329 %b = bitcast <8 x i1> %c to i8
330 ret i8 %b
331 }
333 define arm_aapcs_vfpcc i16 @bitcast_from_v16i1(<16 x i8> %a) {
334 ; CHECK-LE-LABEL: bitcast_from_v16i1:
335 ; CHECK-LE: @ %bb.0: @ %entry
336 ; CHECK-LE-NEXT: .pad #4
337 ; CHECK-LE-NEXT: sub sp, #4
338 ; CHECK-LE-NEXT: vcmp.i8 eq, q0, zr
339 ; CHECK-LE-NEXT: vmrs r0, p0
340 ; CHECK-LE-NEXT: uxth r0, r0
341 ; CHECK-LE-NEXT: add sp, #4
342 ; CHECK-LE-NEXT: bx lr
343 ;
344 ; CHECK-BE-LABEL: bitcast_from_v16i1:
345 ; CHECK-BE: @ %bb.0: @ %entry
346 ; CHECK-BE-NEXT: .pad #4
347 ; CHECK-BE-NEXT: sub sp, #4
348 ; CHECK-BE-NEXT: vrev64.8 q1, q0
349 ; CHECK-BE-NEXT: vcmp.i8 eq, q1, zr
350 ; CHECK-BE-NEXT: vmrs r0, p0
351 ; CHECK-BE-NEXT: rbit r0, r0
352 ; CHECK-BE-NEXT: lsrs r0, r0, #16
353 ; CHECK-BE-NEXT: add sp, #4
354 ; CHECK-BE-NEXT: bx lr
355 entry:
356 %c = icmp eq <16 x i8> %a, zeroinitializer
357 %b = bitcast <16 x i1> %c to i16
358 ret i16 %b
359 }
361 define arm_aapcs_vfpcc i2 @bitcast_from_v2i1(<2 x i64> %a) {
362 ; CHECK-LE-LABEL: bitcast_from_v2i1:
363 ; CHECK-LE: @ %bb.0: @ %entry
364 ; CHECK-LE-NEXT: .pad #4
365 ; CHECK-LE-NEXT: sub sp, #4
366 ; CHECK-LE-NEXT: vmov r0, r1, d0
367 ; CHECK-LE-NEXT: orrs r0, r1
368 ; CHECK-LE-NEXT: csetm r1, eq
369 ; CHECK-LE-NEXT: movs r0, #0
370 ; CHECK-LE-NEXT: bfi r0, r1, #0, #1
371 ; CHECK-LE-NEXT: vmov r1, r2, d1
372 ; CHECK-LE-NEXT: orrs r1, r2
373 ; CHECK-LE-NEXT: csetm r1, eq
374 ; CHECK-LE-NEXT: bfi r0, r1, #1, #1
375 ; CHECK-LE-NEXT: add sp, #4
376 ; CHECK-LE-NEXT: bx lr
377 ;
378 ; CHECK-BE-LABEL: bitcast_from_v2i1:
379 ; CHECK-BE: @ %bb.0: @ %entry
380 ; CHECK-BE-NEXT: .pad #4
381 ; CHECK-BE-NEXT: sub sp, #4
382 ; CHECK-BE-NEXT: vrev64.32 q1, q0
383 ; CHECK-BE-NEXT: vmov r0, r1, d3
384 ; CHECK-BE-NEXT: orrs r0, r1
385 ; CHECK-BE-NEXT: csetm r1, eq
386 ; CHECK-BE-NEXT: movs r0, #0
387 ; CHECK-BE-NEXT: bfi r0, r1, #0, #1
388 ; CHECK-BE-NEXT: vmov r1, r2, d2
389 ; CHECK-BE-NEXT: orrs r1, r2
390 ; CHECK-BE-NEXT: csetm r1, eq
391 ; CHECK-BE-NEXT: bfi r0, r1, #1, #1
392 ; CHECK-BE-NEXT: add sp, #4
393 ; CHECK-BE-NEXT: bx lr
394 entry:
395 %c = icmp eq <2 x i64> %a, zeroinitializer
396 %b = bitcast <2 x i1> %c to i2
397 ret i2 %b
398 }