| blob | ba3d5c22fc671b2f00a078b357aa890341a443d2 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-LE
3 ; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK-BE
5 define arm_aapcs_vfpcc <4 x i32> @load_v4i1(ptr %src, <4 x i32> %a) {
6 ; CHECK-LE-LABEL: load_v4i1:
7 ; CHECK-LE: @ %bb.0: @ %entry
8 ; CHECK-LE-NEXT: ldrb r0, [r0]
9 ; CHECK-LE-NEXT: vmov.i8 q1, #0x0
10 ; CHECK-LE-NEXT: vmov.i8 q2, #0xff
11 ; CHECK-LE-NEXT: vmsr p0, r0
12 ; CHECK-LE-NEXT: vpsel q1, q2, q1
13 ; CHECK-LE-NEXT: vmov.u8 r0, q1[2]
14 ; CHECK-LE-NEXT: vmov.u8 r1, q1[0]
15 ; CHECK-LE-NEXT: vmov q2[2], q2[0], r1, r0
16 ; CHECK-LE-NEXT: vmov.u8 r0, q1[3]
17 ; CHECK-LE-NEXT: vmov.u8 r1, q1[1]
18 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
19 ; CHECK-LE-NEXT: vmov q2[3], q2[1], r1, r0
20 ; CHECK-LE-NEXT: vcmp.i32 ne, q2, zr
21 ; CHECK-LE-NEXT: vpsel q0, q0, q1
22 ; CHECK-LE-NEXT: bx lr
23 ;
24 ; CHECK-BE-LABEL: load_v4i1:
25 ; CHECK-BE: @ %bb.0: @ %entry
26 ; CHECK-BE-NEXT: ldrb r0, [r0]
27 ; CHECK-BE-NEXT: vmov.i8 q1, #0x0
28 ; CHECK-BE-NEXT: vmov.i8 q2, #0xff
29 ; CHECK-BE-NEXT: rbit r0, r0
30 ; CHECK-BE-NEXT: lsrs r0, r0, #28
31 ; CHECK-BE-NEXT: vmsr p0, r0
32 ; CHECK-BE-NEXT: vpsel q1, q2, q1
33 ; CHECK-BE-NEXT: vmov.u8 r0, q1[2]
34 ; CHECK-BE-NEXT: vmov.u8 r1, q1[0]
35 ; CHECK-BE-NEXT: vmov q2[2], q2[0], r1, r0
36 ; CHECK-BE-NEXT: vmov.u8 r0, q1[3]
37 ; CHECK-BE-NEXT: vmov.u8 r1, q1[1]
38 ; CHECK-BE-NEXT: vrev64.32 q1, q0
39 ; CHECK-BE-NEXT: vmov q2[3], q2[1], r1, r0
40 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
41 ; CHECK-BE-NEXT: vcmp.i32 ne, q2, zr
42 ; CHECK-BE-NEXT: vpsel q1, q1, q0
43 ; CHECK-BE-NEXT: vrev64.32 q0, q1
44 ; CHECK-BE-NEXT: bx lr
45 entry:
46 %c = load <4 x i1>, ptr %src
47 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
48 ret <4 x i32> %s
49 }
51 define arm_aapcs_vfpcc <8 x i16> @load_v8i1(ptr %src, <8 x i16> %a) {
52 ; CHECK-LE-LABEL: load_v8i1:
53 ; CHECK-LE: @ %bb.0: @ %entry
54 ; CHECK-LE-NEXT: ldrb r0, [r0]
55 ; CHECK-LE-NEXT: vmov.i8 q1, #0x0
56 ; CHECK-LE-NEXT: vmov.i8 q2, #0xff
57 ; CHECK-LE-NEXT: vmsr p0, r0
58 ; CHECK-LE-NEXT: vpsel q2, q2, q1
59 ; CHECK-LE-NEXT: vmov.u8 r0, q2[0]
60 ; CHECK-LE-NEXT: vmov.16 q1[0], r0
61 ; CHECK-LE-NEXT: vmov.u8 r0, q2[1]
62 ; CHECK-LE-NEXT: vmov.16 q1[1], r0
63 ; CHECK-LE-NEXT: vmov.u8 r0, q2[2]
64 ; CHECK-LE-NEXT: vmov.16 q1[2], r0
65 ; CHECK-LE-NEXT: vmov.u8 r0, q2[3]
66 ; CHECK-LE-NEXT: vmov.16 q1[3], r0
67 ; CHECK-LE-NEXT: vmov.u8 r0, q2[4]
68 ; CHECK-LE-NEXT: vmov.16 q1[4], r0
69 ; CHECK-LE-NEXT: vmov.u8 r0, q2[5]
70 ; CHECK-LE-NEXT: vmov.16 q1[5], r0
71 ; CHECK-LE-NEXT: vmov.u8 r0, q2[6]
72 ; CHECK-LE-NEXT: vmov.16 q1[6], r0
73 ; CHECK-LE-NEXT: vmov.u8 r0, q2[7]
74 ; CHECK-LE-NEXT: vmov.16 q1[7], r0
75 ; CHECK-LE-NEXT: vcmp.i16 ne, q1, zr
76 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
77 ; CHECK-LE-NEXT: vpsel q0, q0, q1
78 ; CHECK-LE-NEXT: bx lr
79 ;
80 ; CHECK-BE-LABEL: load_v8i1:
81 ; CHECK-BE: @ %bb.0: @ %entry
82 ; CHECK-BE-NEXT: ldrb r0, [r0]
83 ; CHECK-BE-NEXT: vmov.i8 q1, #0x0
84 ; CHECK-BE-NEXT: vmov.i8 q2, #0xff
85 ; CHECK-BE-NEXT: rbit r0, r0
86 ; CHECK-BE-NEXT: lsrs r0, r0, #24
87 ; CHECK-BE-NEXT: vmsr p0, r0
88 ; CHECK-BE-NEXT: vpsel q2, q2, q1
89 ; CHECK-BE-NEXT: vmov.u8 r0, q2[0]
90 ; CHECK-BE-NEXT: vmov.16 q1[0], r0
91 ; CHECK-BE-NEXT: vmov.u8 r0, q2[1]
92 ; CHECK-BE-NEXT: vmov.16 q1[1], r0
93 ; CHECK-BE-NEXT: vmov.u8 r0, q2[2]
94 ; CHECK-BE-NEXT: vmov.16 q1[2], r0
95 ; CHECK-BE-NEXT: vmov.u8 r0, q2[3]
96 ; CHECK-BE-NEXT: vmov.16 q1[3], r0
97 ; CHECK-BE-NEXT: vmov.u8 r0, q2[4]
98 ; CHECK-BE-NEXT: vmov.16 q1[4], r0
99 ; CHECK-BE-NEXT: vmov.u8 r0, q2[5]
100 ; CHECK-BE-NEXT: vmov.16 q1[5], r0
101 ; CHECK-BE-NEXT: vmov.u8 r0, q2[6]
102 ; CHECK-BE-NEXT: vmov.16 q1[6], r0
103 ; CHECK-BE-NEXT: vmov.u8 r0, q2[7]
104 ; CHECK-BE-NEXT: vmov.16 q1[7], r0
105 ; CHECK-BE-NEXT: vcmp.i16 ne, q1, zr
106 ; CHECK-BE-NEXT: vrev64.16 q1, q0
107 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
108 ; CHECK-BE-NEXT: vpsel q1, q1, q0
109 ; CHECK-BE-NEXT: vrev64.16 q0, q1
110 ; CHECK-BE-NEXT: bx lr
111 entry:
112 %c = load <8 x i1>, ptr %src
113 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> zeroinitializer
114 ret <8 x i16> %s
115 }
117 define arm_aapcs_vfpcc <16 x i8> @load_v16i1(ptr %src, <16 x i8> %a) {
118 ; CHECK-LE-LABEL: load_v16i1:
119 ; CHECK-LE: @ %bb.0: @ %entry
120 ; CHECK-LE-NEXT: ldrh r0, [r0]
121 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
122 ; CHECK-LE-NEXT: vmsr p0, r0
123 ; CHECK-LE-NEXT: vpsel q0, q0, q1
124 ; CHECK-LE-NEXT: bx lr
125 ;
126 ; CHECK-BE-LABEL: load_v16i1:
127 ; CHECK-BE: @ %bb.0: @ %entry
128 ; CHECK-BE-NEXT: ldrh r0, [r0]
129 ; CHECK-BE-NEXT: vrev64.8 q1, q0
130 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
131 ; CHECK-BE-NEXT: rbit r0, r0
132 ; CHECK-BE-NEXT: lsrs r0, r0, #16
133 ; CHECK-BE-NEXT: vmsr p0, r0
134 ; CHECK-BE-NEXT: vpsel q1, q1, q0
135 ; CHECK-BE-NEXT: vrev64.8 q0, q1
136 ; CHECK-BE-NEXT: bx lr
137 entry:
138 %c = load <16 x i1>, ptr %src
139 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> zeroinitializer
140 ret <16 x i8> %s
141 }
143 define arm_aapcs_vfpcc <2 x i64> @load_v2i1(ptr %src, <2 x i64> %a) {
144 ; CHECK-LE-LABEL: load_v2i1:
145 ; CHECK-LE: @ %bb.0: @ %entry
146 ; CHECK-LE-NEXT: ldrb r0, [r0]
147 ; CHECK-LE-NEXT: vmov.i8 q1, #0x0
148 ; CHECK-LE-NEXT: vmov.i8 q2, #0xff
149 ; CHECK-LE-NEXT: vmsr p0, r0
150 ; CHECK-LE-NEXT: vpsel q1, q2, q1
151 ; CHECK-LE-NEXT: vmov.u8 r0, q1[1]
152 ; CHECK-LE-NEXT: vmov.u8 r1, q1[0]
153 ; CHECK-LE-NEXT: vmov q1[2], q1[0], r1, r0
154 ; CHECK-LE-NEXT: vmov q1[3], q1[1], r1, r0
155 ; CHECK-LE-NEXT: vcmp.i32 ne, q1, zr
156 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
157 ; CHECK-LE-NEXT: vpsel q0, q0, q1
158 ; CHECK-LE-NEXT: bx lr
159 ;
160 ; CHECK-BE-LABEL: load_v2i1:
161 ; CHECK-BE: @ %bb.0: @ %entry
162 ; CHECK-BE-NEXT: ldrb r0, [r0]
163 ; CHECK-BE-NEXT: vmov.i8 q1, #0x0
164 ; CHECK-BE-NEXT: vmov.i8 q2, #0xff
165 ; CHECK-BE-NEXT: rbit r0, r0
166 ; CHECK-BE-NEXT: lsrs r0, r0, #30
167 ; CHECK-BE-NEXT: vmsr p0, r0
168 ; CHECK-BE-NEXT: vpsel q1, q2, q1
169 ; CHECK-BE-NEXT: vmov.u8 r0, q1[1]
170 ; CHECK-BE-NEXT: vmov.u8 r1, q1[0]
171 ; CHECK-BE-NEXT: vmov q1[2], q1[0], r1, r0
172 ; CHECK-BE-NEXT: vmov q1[3], q1[1], r1, r0
173 ; CHECK-BE-NEXT: vcmp.i32 ne, q1, zr
174 ; CHECK-BE-NEXT: vmov.i32 q1, #0x0
175 ; CHECK-BE-NEXT: vpsel q0, q0, q1
176 ; CHECK-BE-NEXT: bx lr
177 entry:
178 %c = load <2 x i1>, ptr %src
179 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> zeroinitializer
180 ret <2 x i64> %s
181 }
184 define arm_aapcs_vfpcc void @store_v4i1(ptr %dst, <4 x i32> %a) {
185 ; CHECK-LE-LABEL: store_v4i1:
186 ; CHECK-LE: @ %bb.0: @ %entry
187 ; CHECK-LE-NEXT: vcmp.i32 eq, q0, zr
188 ; CHECK-LE-NEXT: movs r3, #0
189 ; CHECK-LE-NEXT: vmrs r1, p0
190 ; CHECK-LE-NEXT: and r2, r1, #1
191 ; CHECK-LE-NEXT: rsbs r2, r2, #0
192 ; CHECK-LE-NEXT: bfi r3, r2, #0, #1
193 ; CHECK-LE-NEXT: ubfx r2, r1, #4, #1
194 ; CHECK-LE-NEXT: rsbs r2, r2, #0
195 ; CHECK-LE-NEXT: bfi r3, r2, #1, #1
196 ; CHECK-LE-NEXT: ubfx r2, r1, #8, #1
197 ; CHECK-LE-NEXT: ubfx r1, r1, #12, #1
198 ; CHECK-LE-NEXT: rsbs r2, r2, #0
199 ; CHECK-LE-NEXT: bfi r3, r2, #2, #1
200 ; CHECK-LE-NEXT: rsbs r1, r1, #0
201 ; CHECK-LE-NEXT: bfi r3, r1, #3, #1
202 ; CHECK-LE-NEXT: strb r3, [r0]
203 ; CHECK-LE-NEXT: bx lr
204 ;
205 ; CHECK-BE-LABEL: store_v4i1:
206 ; CHECK-BE: @ %bb.0: @ %entry
207 ; CHECK-BE-NEXT: vrev64.32 q1, q0
208 ; CHECK-BE-NEXT: movs r3, #0
209 ; CHECK-BE-NEXT: vcmp.i32 eq, q1, zr
210 ; CHECK-BE-NEXT: vmrs r1, p0
211 ; CHECK-BE-NEXT: ubfx r2, r1, #12, #1
212 ; CHECK-BE-NEXT: rsbs r2, r2, #0
213 ; CHECK-BE-NEXT: bfi r3, r2, #0, #1
214 ; CHECK-BE-NEXT: ubfx r2, r1, #8, #1
215 ; CHECK-BE-NEXT: rsbs r2, r2, #0
216 ; CHECK-BE-NEXT: bfi r3, r2, #1, #1
217 ; CHECK-BE-NEXT: ubfx r2, r1, #4, #1
218 ; CHECK-BE-NEXT: and r1, r1, #1
219 ; CHECK-BE-NEXT: rsbs r2, r2, #0
220 ; CHECK-BE-NEXT: bfi r3, r2, #2, #1
221 ; CHECK-BE-NEXT: rsbs r1, r1, #0
222 ; CHECK-BE-NEXT: bfi r3, r1, #3, #1
223 ; CHECK-BE-NEXT: strb r3, [r0]
224 ; CHECK-BE-NEXT: bx lr
225 entry:
226 %c = icmp eq <4 x i32> %a, zeroinitializer
227 store <4 x i1> %c, ptr %dst
228 ret void
229 }
231 define arm_aapcs_vfpcc void @store_v8i1(ptr %dst, <8 x i16> %a) {
232 ; CHECK-LE-LABEL: store_v8i1:
233 ; CHECK-LE: @ %bb.0: @ %entry
234 ; CHECK-LE-NEXT: vcmp.i16 eq, q0, zr
235 ; CHECK-LE-NEXT: vmrs r2, p0
236 ; CHECK-LE-NEXT: and r1, r2, #1
237 ; CHECK-LE-NEXT: rsbs r3, r1, #0
238 ; CHECK-LE-NEXT: movs r1, #0
239 ; CHECK-LE-NEXT: bfi r1, r3, #0, #1
240 ; CHECK-LE-NEXT: ubfx r3, r2, #2, #1
241 ; CHECK-LE-NEXT: rsbs r3, r3, #0
242 ; CHECK-LE-NEXT: bfi r1, r3, #1, #1
243 ; CHECK-LE-NEXT: ubfx r3, r2, #4, #1
244 ; CHECK-LE-NEXT: rsbs r3, r3, #0
245 ; CHECK-LE-NEXT: bfi r1, r3, #2, #1
246 ; CHECK-LE-NEXT: ubfx r3, r2, #6, #1
247 ; CHECK-LE-NEXT: rsbs r3, r3, #0
248 ; CHECK-LE-NEXT: bfi r1, r3, #3, #1
249 ; CHECK-LE-NEXT: ubfx r3, r2, #8, #1
250 ; CHECK-LE-NEXT: rsbs r3, r3, #0
251 ; CHECK-LE-NEXT: bfi r1, r3, #4, #1
252 ; CHECK-LE-NEXT: ubfx r3, r2, #10, #1
253 ; CHECK-LE-NEXT: rsbs r3, r3, #0
254 ; CHECK-LE-NEXT: bfi r1, r3, #5, #1
255 ; CHECK-LE-NEXT: ubfx r3, r2, #12, #1
256 ; CHECK-LE-NEXT: ubfx r2, r2, #14, #1
257 ; CHECK-LE-NEXT: rsbs r3, r3, #0
258 ; CHECK-LE-NEXT: bfi r1, r3, #6, #1
259 ; CHECK-LE-NEXT: rsbs r2, r2, #0
260 ; CHECK-LE-NEXT: bfi r1, r2, #7, #1
261 ; CHECK-LE-NEXT: strb r1, [r0]
262 ; CHECK-LE-NEXT: bx lr
263 ;
264 ; CHECK-BE-LABEL: store_v8i1:
265 ; CHECK-BE: @ %bb.0: @ %entry
266 ; CHECK-BE-NEXT: vrev64.16 q1, q0
267 ; CHECK-BE-NEXT: vcmp.i16 eq, q1, zr
268 ; CHECK-BE-NEXT: vmrs r2, p0
269 ; CHECK-BE-NEXT: ubfx r1, r2, #14, #1
270 ; CHECK-BE-NEXT: rsbs r3, r1, #0
271 ; CHECK-BE-NEXT: movs r1, #0
272 ; CHECK-BE-NEXT: bfi r1, r3, #0, #1
273 ; CHECK-BE-NEXT: ubfx r3, r2, #12, #1
274 ; CHECK-BE-NEXT: rsbs r3, r3, #0
275 ; CHECK-BE-NEXT: bfi r1, r3, #1, #1
276 ; CHECK-BE-NEXT: ubfx r3, r2, #10, #1
277 ; CHECK-BE-NEXT: rsbs r3, r3, #0
278 ; CHECK-BE-NEXT: bfi r1, r3, #2, #1
279 ; CHECK-BE-NEXT: ubfx r3, r2, #8, #1
280 ; CHECK-BE-NEXT: rsbs r3, r3, #0
281 ; CHECK-BE-NEXT: bfi r1, r3, #3, #1
282 ; CHECK-BE-NEXT: ubfx r3, r2, #6, #1
283 ; CHECK-BE-NEXT: rsbs r3, r3, #0
284 ; CHECK-BE-NEXT: bfi r1, r3, #4, #1
285 ; CHECK-BE-NEXT: ubfx r3, r2, #4, #1
286 ; CHECK-BE-NEXT: rsbs r3, r3, #0
287 ; CHECK-BE-NEXT: bfi r1, r3, #5, #1
288 ; CHECK-BE-NEXT: ubfx r3, r2, #2, #1
289 ; CHECK-BE-NEXT: and r2, r2, #1
290 ; CHECK-BE-NEXT: rsbs r3, r3, #0
291 ; CHECK-BE-NEXT: bfi r1, r3, #6, #1
292 ; CHECK-BE-NEXT: rsbs r2, r2, #0
293 ; CHECK-BE-NEXT: bfi r1, r2, #7, #1
294 ; CHECK-BE-NEXT: strb r1, [r0]
295 ; CHECK-BE-NEXT: bx lr
296 entry:
297 %c = icmp eq <8 x i16> %a, zeroinitializer
298 store <8 x i1> %c, ptr %dst
299 ret void
300 }
302 define arm_aapcs_vfpcc void @store_v16i1(ptr %dst, <16 x i8> %a) {
303 ; CHECK-LE-LABEL: store_v16i1:
304 ; CHECK-LE: @ %bb.0: @ %entry
305 ; CHECK-LE-NEXT: vcmp.i8 eq, q0, zr
306 ; CHECK-LE-NEXT: vmrs r1, p0
307 ; CHECK-LE-NEXT: strh r1, [r0]
308 ; CHECK-LE-NEXT: bx lr
309 ;
310 ; CHECK-BE-LABEL: store_v16i1:
311 ; CHECK-BE: @ %bb.0: @ %entry
312 ; CHECK-BE-NEXT: vrev64.8 q1, q0
313 ; CHECK-BE-NEXT: vcmp.i8 eq, q1, zr
314 ; CHECK-BE-NEXT: vmrs r1, p0
315 ; CHECK-BE-NEXT: rbit r1, r1
316 ; CHECK-BE-NEXT: lsrs r1, r1, #16
317 ; CHECK-BE-NEXT: strh r1, [r0]
318 ; CHECK-BE-NEXT: bx lr
319 entry:
320 %c = icmp eq <16 x i8> %a, zeroinitializer
321 store <16 x i1> %c, ptr %dst
322 ret void
323 }
325 define arm_aapcs_vfpcc void @store_v2i1(ptr %dst, <2 x i64> %a) {
326 ; CHECK-LE-LABEL: store_v2i1:
327 ; CHECK-LE: @ %bb.0: @ %entry
328 ; CHECK-LE-NEXT: vmov r1, r2, d0
329 ; CHECK-LE-NEXT: orrs r1, r2
330 ; CHECK-LE-NEXT: mov.w r2, #0
331 ; CHECK-LE-NEXT: csetm r1, eq
332 ; CHECK-LE-NEXT: bfi r2, r1, #0, #1
333 ; CHECK-LE-NEXT: vmov r1, r3, d1
334 ; CHECK-LE-NEXT: orrs r1, r3
335 ; CHECK-LE-NEXT: csetm r1, eq
336 ; CHECK-LE-NEXT: bfi r2, r1, #1, #1
337 ; CHECK-LE-NEXT: strb r2, [r0]
338 ; CHECK-LE-NEXT: bx lr
339 ;
340 ; CHECK-BE-LABEL: store_v2i1:
341 ; CHECK-BE: @ %bb.0: @ %entry
342 ; CHECK-BE-NEXT: vrev64.32 q1, q0
343 ; CHECK-BE-NEXT: vmov r1, r2, d3
344 ; CHECK-BE-NEXT: orrs r1, r2
345 ; CHECK-BE-NEXT: mov.w r2, #0
346 ; CHECK-BE-NEXT: csetm r1, eq
347 ; CHECK-BE-NEXT: bfi r2, r1, #0, #1
348 ; CHECK-BE-NEXT: vmov r1, r3, d2
349 ; CHECK-BE-NEXT: orrs r1, r3
350 ; CHECK-BE-NEXT: csetm r1, eq
351 ; CHECK-BE-NEXT: bfi r2, r1, #1, #1
352 ; CHECK-BE-NEXT: strb r2, [r0]
353 ; CHECK-BE-NEXT: bx lr
354 entry:
355 %c = icmp eq <2 x i64> %a, zeroinitializer
356 store <2 x i1> %c, ptr %dst
357 ret void
358 }
360 define arm_aapcs_vfpcc <4 x i32> @load_predcastzext(ptr %i, <4 x i32> %a) {
361 ; CHECK-LE-LABEL: load_predcastzext:
362 ; CHECK-LE: @ %bb.0:
363 ; CHECK-LE-NEXT: ldrh r0, [r0]
364 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
365 ; CHECK-LE-NEXT: vmsr p0, r0
366 ; CHECK-LE-NEXT: vpsel q0, q0, q1
367 ; CHECK-LE-NEXT: bx lr
368 ;
369 ; CHECK-BE-LABEL: load_predcastzext:
370 ; CHECK-BE: @ %bb.0:
371 ; CHECK-BE-NEXT: ldrh r0, [r0]
372 ; CHECK-BE-NEXT: vrev64.32 q1, q0
373 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
374 ; CHECK-BE-NEXT: vmsr p0, r0
375 ; CHECK-BE-NEXT: vpsel q1, q1, q0
376 ; CHECK-BE-NEXT: vrev64.32 q0, q1
377 ; CHECK-BE-NEXT: bx lr
378 %l = load i16, ptr %i, align 4
379 %lz = zext i16 %l to i32
380 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %lz)
381 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
382 ret <4 x i32> %s
383 }
385 define arm_aapcs_vfpcc <4 x i32> @load_bc4(ptr %i, <4 x i32> %a) {
386 ; CHECK-LE-LABEL: load_bc4:
387 ; CHECK-LE: @ %bb.0:
388 ; CHECK-LE-NEXT: vldr p0, [r0]
389 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
390 ; CHECK-LE-NEXT: vpsel q0, q0, q1
391 ; CHECK-LE-NEXT: bx lr
392 ;
393 ; CHECK-BE-LABEL: load_bc4:
394 ; CHECK-BE: @ %bb.0:
395 ; CHECK-BE-NEXT: vldr p0, [r0]
396 ; CHECK-BE-NEXT: vrev64.32 q1, q0
397 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
398 ; CHECK-BE-NEXT: vpsel q1, q1, q0
399 ; CHECK-BE-NEXT: vrev64.32 q0, q1
400 ; CHECK-BE-NEXT: bx lr
401 %l = load i32, ptr %i, align 4
402 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)
403 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
404 ret <4 x i32> %s
405 }
407 define arm_aapcs_vfpcc <8 x i16> @load_predcast8(ptr %i, <8 x i16> %a) {
408 ; CHECK-LE-LABEL: load_predcast8:
409 ; CHECK-LE: @ %bb.0:
410 ; CHECK-LE-NEXT: vldr p0, [r0]
411 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
412 ; CHECK-LE-NEXT: vpsel q0, q0, q1
413 ; CHECK-LE-NEXT: bx lr
414 ;
415 ; CHECK-BE-LABEL: load_predcast8:
416 ; CHECK-BE: @ %bb.0:
417 ; CHECK-BE-NEXT: vldr p0, [r0]
418 ; CHECK-BE-NEXT: vrev64.16 q1, q0
419 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
420 ; CHECK-BE-NEXT: vpsel q1, q1, q0
421 ; CHECK-BE-NEXT: vrev64.16 q0, q1
422 ; CHECK-BE-NEXT: bx lr
423 %l = load i32, ptr %i, align 4
424 %c = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %l)
425 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> zeroinitializer
426 ret <8 x i16> %s
427 }
429 define arm_aapcs_vfpcc <16 x i8> @load_predcast16(ptr %i, <16 x i8> %a) {
430 ; CHECK-LE-LABEL: load_predcast16:
431 ; CHECK-LE: @ %bb.0:
432 ; CHECK-LE-NEXT: vldr p0, [r0]
433 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
434 ; CHECK-LE-NEXT: vpsel q0, q0, q1
435 ; CHECK-LE-NEXT: bx lr
436 ;
437 ; CHECK-BE-LABEL: load_predcast16:
438 ; CHECK-BE: @ %bb.0:
439 ; CHECK-BE-NEXT: vldr p0, [r0]
440 ; CHECK-BE-NEXT: vrev64.8 q1, q0
441 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
442 ; CHECK-BE-NEXT: vpsel q1, q1, q0
443 ; CHECK-BE-NEXT: vrev64.8 q0, q1
444 ; CHECK-BE-NEXT: bx lr
445 %l = load i32, ptr %i, align 4
446 %c = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %l)
447 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> zeroinitializer
448 ret <16 x i8> %s
449 }
451 define arm_aapcs_vfpcc <4 x i32> @load_bc4_align2(ptr %i, <4 x i32> %a) {
452 ; CHECK-LE-LABEL: load_bc4_align2:
453 ; CHECK-LE: @ %bb.0:
454 ; CHECK-LE-NEXT: ldr r0, [r0]
455 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
456 ; CHECK-LE-NEXT: vmsr p0, r0
457 ; CHECK-LE-NEXT: vpsel q0, q0, q1
458 ; CHECK-LE-NEXT: bx lr
459 ;
460 ; CHECK-BE-LABEL: load_bc4_align2:
461 ; CHECK-BE: @ %bb.0:
462 ; CHECK-BE-NEXT: ldr r0, [r0]
463 ; CHECK-BE-NEXT: vrev64.32 q1, q0
464 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
465 ; CHECK-BE-NEXT: vmsr p0, r0
466 ; CHECK-BE-NEXT: vpsel q1, q1, q0
467 ; CHECK-BE-NEXT: vrev64.32 q0, q1
468 ; CHECK-BE-NEXT: bx lr
469 %l = load i32, ptr %i, align 2
470 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)
471 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
472 ret <4 x i32> %s
473 }
475 define arm_aapcs_vfpcc <4 x i32> @load_bc4_offset(ptr %i, <4 x i32> %a) {
476 ; CHECK-LE-LABEL: load_bc4_offset:
477 ; CHECK-LE: @ %bb.0:
478 ; CHECK-LE-NEXT: adds r0, #6
479 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
480 ; CHECK-LE-NEXT: vldr p0, [r0]
481 ; CHECK-LE-NEXT: vpsel q0, q0, q1
482 ; CHECK-LE-NEXT: bx lr
483 ;
484 ; CHECK-BE-LABEL: load_bc4_offset:
485 ; CHECK-BE: @ %bb.0:
486 ; CHECK-BE-NEXT: adds r0, #6
487 ; CHECK-BE-NEXT: vrev64.32 q1, q0
488 ; CHECK-BE-NEXT: vldr p0, [r0]
489 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
490 ; CHECK-BE-NEXT: vpsel q1, q1, q0
491 ; CHECK-BE-NEXT: vrev64.32 q0, q1
492 ; CHECK-BE-NEXT: bx lr
493 %g = getelementptr inbounds i16, ptr %i, i32 3
494 %l = load i32, ptr %g, align 4
495 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)
496 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
497 ret <4 x i32> %s
498 }
500 define arm_aapcs_vfpcc <4 x i32> @load_bc4_range4(ptr %i, <4 x i32> %a) {
501 ; CHECK-LE-LABEL: load_bc4_range4:
502 ; CHECK-LE: @ %bb.0:
503 ; CHECK-LE-NEXT: vldr p0, [r0, #4]
504 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
505 ; CHECK-LE-NEXT: vpsel q0, q0, q1
506 ; CHECK-LE-NEXT: bx lr
507 ;
508 ; CHECK-BE-LABEL: load_bc4_range4:
509 ; CHECK-BE: @ %bb.0:
510 ; CHECK-BE-NEXT: vldr p0, [r0, #4]
511 ; CHECK-BE-NEXT: vrev64.32 q1, q0
512 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
513 ; CHECK-BE-NEXT: vpsel q1, q1, q0
514 ; CHECK-BE-NEXT: vrev64.32 q0, q1
515 ; CHECK-BE-NEXT: bx lr
516 %g = getelementptr inbounds i32, ptr %i, i32 1
517 %l = load i32, ptr %g, align 4
518 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)
519 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
520 ret <4 x i32> %s
521 }
523 define arm_aapcs_vfpcc <4 x i32> @load_bc4_range(ptr %i, <4 x i32> %a) {
524 ; CHECK-LE-LABEL: load_bc4_range:
525 ; CHECK-LE: @ %bb.0:
526 ; CHECK-LE-NEXT: vldr p0, [r0, #508]
527 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
528 ; CHECK-LE-NEXT: vpsel q0, q0, q1
529 ; CHECK-LE-NEXT: bx lr
530 ;
531 ; CHECK-BE-LABEL: load_bc4_range:
532 ; CHECK-BE: @ %bb.0:
533 ; CHECK-BE-NEXT: vldr p0, [r0, #508]
534 ; CHECK-BE-NEXT: vrev64.32 q1, q0
535 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
536 ; CHECK-BE-NEXT: vpsel q1, q1, q0
537 ; CHECK-BE-NEXT: vrev64.32 q0, q1
538 ; CHECK-BE-NEXT: bx lr
539 %g = getelementptr inbounds i32, ptr %i, i32 127
540 %l = load i32, ptr %g, align 4
541 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)
542 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
543 ret <4 x i32> %s
544 }
546 define arm_aapcs_vfpcc <4 x i32> @load_bc4_range2(ptr %i, <4 x i32> %a) {
547 ; CHECK-LE-LABEL: load_bc4_range2:
548 ; CHECK-LE: @ %bb.0:
549 ; CHECK-LE-NEXT: vldr p0, [r0, #-508]
550 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
551 ; CHECK-LE-NEXT: vpsel q0, q0, q1
552 ; CHECK-LE-NEXT: bx lr
553 ;
554 ; CHECK-BE-LABEL: load_bc4_range2:
555 ; CHECK-BE: @ %bb.0:
556 ; CHECK-BE-NEXT: vldr p0, [r0, #-508]
557 ; CHECK-BE-NEXT: vrev64.32 q1, q0
558 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
559 ; CHECK-BE-NEXT: vpsel q1, q1, q0
560 ; CHECK-BE-NEXT: vrev64.32 q0, q1
561 ; CHECK-BE-NEXT: bx lr
562 %g = getelementptr inbounds i32, ptr %i, i32 -127
563 %l = load i32, ptr %g, align 4
564 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)
565 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
566 ret <4 x i32> %s
567 }
569 define arm_aapcs_vfpcc <4 x i32> @load_bc4_range3(ptr %i, <4 x i32> %a) {
570 ; CHECK-LE-LABEL: load_bc4_range3:
571 ; CHECK-LE: @ %bb.0:
572 ; CHECK-LE-NEXT: add.w r0, r0, #512
573 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
574 ; CHECK-LE-NEXT: vldr p0, [r0]
575 ; CHECK-LE-NEXT: vpsel q0, q0, q1
576 ; CHECK-LE-NEXT: bx lr
577 ;
578 ; CHECK-BE-LABEL: load_bc4_range3:
579 ; CHECK-BE: @ %bb.0:
580 ; CHECK-BE-NEXT: add.w r0, r0, #512
581 ; CHECK-BE-NEXT: vrev64.32 q1, q0
582 ; CHECK-BE-NEXT: vldr p0, [r0]
583 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
584 ; CHECK-BE-NEXT: vpsel q1, q1, q0
585 ; CHECK-BE-NEXT: vrev64.32 q0, q1
586 ; CHECK-BE-NEXT: bx lr
587 %g = getelementptr inbounds i32, ptr %i, i32 128
588 %l = load i32, ptr %g, align 4
589 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)
590 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
591 ret <4 x i32> %s
592 }
594 define arm_aapcs_vfpcc <4 x i32> @load_bc4_range5(ptr %i, <4 x i32> %a) {
595 ; CHECK-LE-LABEL: load_bc4_range5:
596 ; CHECK-LE: @ %bb.0:
597 ; CHECK-LE-NEXT: sub.w r0, r0, #512
598 ; CHECK-LE-NEXT: vmov.i32 q1, #0x0
599 ; CHECK-LE-NEXT: vldr p0, [r0]
600 ; CHECK-LE-NEXT: vpsel q0, q0, q1
601 ; CHECK-LE-NEXT: bx lr
602 ;
603 ; CHECK-BE-LABEL: load_bc4_range5:
604 ; CHECK-BE: @ %bb.0:
605 ; CHECK-BE-NEXT: sub.w r0, r0, #512
606 ; CHECK-BE-NEXT: vrev64.32 q1, q0
607 ; CHECK-BE-NEXT: vldr p0, [r0]
608 ; CHECK-BE-NEXT: vmov.i32 q0, #0x0
609 ; CHECK-BE-NEXT: vpsel q1, q1, q0
610 ; CHECK-BE-NEXT: vrev64.32 q0, q1
611 ; CHECK-BE-NEXT: bx lr
612 %g = getelementptr inbounds i32, ptr %i, i32 -128
613 %l = load i32, ptr %g, align 4
614 %c = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l)
615 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> zeroinitializer
616 ret <4 x i32> %s
617 }
619 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
620 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
621 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)