| blob | d52b455eb2e6b0c83e99025a37163e64af8cbf43 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X86
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64
4 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
6 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
9 define i32 @PR15215_bad(<4 x i32> %input) nounwind {
10 ; X86-LABEL: PR15215_bad:
11 ; X86: # %bb.0: # %entry
12 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
13 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
14 ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
15 ; X86-NEXT: movb {{[0-9]+}}(%esp), %ah
16 ; X86-NEXT: shlb $3, %ah
17 ; X86-NEXT: andb $1, %cl
18 ; X86-NEXT: shlb $2, %cl
19 ; X86-NEXT: orb %ah, %cl
20 ; X86-NEXT: addb %dl, %dl
21 ; X86-NEXT: andb $1, %al
22 ; X86-NEXT: orb %dl, %al
23 ; X86-NEXT: andb $3, %al
24 ; X86-NEXT: orb %cl, %al
25 ; X86-NEXT: movzbl %al, %eax
26 ; X86-NEXT: andl $15, %eax
27 ; X86-NEXT: retl
28 ;
29 ; X64-LABEL: PR15215_bad:
30 ; X64: # %bb.0: # %entry
31 ; X64-NEXT: shlb $3, %cl
32 ; X64-NEXT: andb $1, %dl
33 ; X64-NEXT: shlb $2, %dl
34 ; X64-NEXT: orb %cl, %dl
35 ; X64-NEXT: addb %sil, %sil
36 ; X64-NEXT: andb $1, %dil
37 ; X64-NEXT: orb %sil, %dil
38 ; X64-NEXT: andb $3, %dil
39 ; X64-NEXT: orb %dl, %dil
40 ; X64-NEXT: movzbl %dil, %eax
41 ; X64-NEXT: andl $15, %eax
42 ; X64-NEXT: retq
43 ;
44 ; SSE2-LABEL: PR15215_bad:
45 ; SSE2: # %bb.0: # %entry
46 ; SSE2-NEXT: pslld $31, %xmm0
47 ; SSE2-NEXT: movmskps %xmm0, %eax
48 ; SSE2-NEXT: ret{{[l|q]}}
49 ;
50 ; AVX2-LABEL: PR15215_bad:
51 ; AVX2: # %bb.0: # %entry
52 ; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
53 ; AVX2-NEXT: vmovmskps %xmm0, %eax
54 ; AVX2-NEXT: ret{{[l|q]}}
55 entry:
56 %0 = trunc <4 x i32> %input to <4 x i1>
57 %1 = bitcast <4 x i1> %0 to i4
58 %2 = zext i4 %1 to i32
59 ret i32 %2
60 }
62 define i32 @PR15215_good(<4 x i32> %input) nounwind {
63 ; X86-LABEL: PR15215_good:
64 ; X86: # %bb.0: # %entry
65 ; X86-NEXT: pushl %esi
66 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
67 ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
68 ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
69 ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
70 ; X86-NEXT: andl $1, %esi
71 ; X86-NEXT: andl $1, %edx
72 ; X86-NEXT: andl $1, %ecx
73 ; X86-NEXT: andl $1, %eax
74 ; X86-NEXT: leal (%esi,%edx,2), %edx
75 ; X86-NEXT: leal (%edx,%ecx,4), %ecx
76 ; X86-NEXT: leal (%ecx,%eax,8), %eax
77 ; X86-NEXT: popl %esi
78 ; X86-NEXT: retl
79 ;
80 ; X64-LABEL: PR15215_good:
81 ; X64: # %bb.0: # %entry
82 ; X64-NEXT: # kill: def $ecx killed $ecx def $rcx
83 ; X64-NEXT: # kill: def $edx killed $edx def $rdx
84 ; X64-NEXT: # kill: def $esi killed $esi def $rsi
85 ; X64-NEXT: # kill: def $edi killed $edi def $rdi
86 ; X64-NEXT: andl $1, %edi
87 ; X64-NEXT: andl $1, %esi
88 ; X64-NEXT: andl $1, %edx
89 ; X64-NEXT: andl $1, %ecx
90 ; X64-NEXT: leal (%rdi,%rsi,2), %eax
91 ; X64-NEXT: leal (%rax,%rdx,4), %eax
92 ; X64-NEXT: leal (%rax,%rcx,8), %eax
93 ; X64-NEXT: retq
94 ;
95 ; SSE2-LABEL: PR15215_good:
96 ; SSE2: # %bb.0: # %entry
97 ; SSE2-NEXT: pslld $31, %xmm0
98 ; SSE2-NEXT: movmskps %xmm0, %eax
99 ; SSE2-NEXT: ret{{[l|q]}}
100 ;
101 ; AVX2-LABEL: PR15215_good:
102 ; AVX2: # %bb.0: # %entry
103 ; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
104 ; AVX2-NEXT: vmovmskps %xmm0, %eax
105 ; AVX2-NEXT: ret{{[l|q]}}
106 entry:
107 %0 = trunc <4 x i32> %input to <4 x i1>
108 %1 = extractelement <4 x i1> %0, i32 0
109 %e1 = select i1 %1, i32 1, i32 0
110 %2 = extractelement <4 x i1> %0, i32 1
111 %e2 = select i1 %2, i32 2, i32 0
112 %3 = extractelement <4 x i1> %0, i32 2
113 %e3 = select i1 %3, i32 4, i32 0
114 %4 = extractelement <4 x i1> %0, i32 3
115 %e4 = select i1 %4, i32 8, i32 0
116 %5 = or i32 %e1, %e2
117 %6 = or i32 %5, %e3
118 %7 = or i32 %6, %e4
119 ret i32 %7
120 }