1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2 ; RUN: llc -mtriple=xtensa -disable-block-placement -verify-machineinstrs < %s \
5 define i32 @brcc_sgt(i32 %a, i32 %b) nounwind {
6 ; CHECK-LABEL: brcc_sgt:
7 ; CHECK: bge a3, a2, .LBB0_2
8 ; CHECK-NEXT: # %bb.1: # %t1
9 ; CHECK-NEXT: addi a2, a2, 4
11 ; CHECK-NEXT: .LBB0_2: # %t2
12 ; CHECK-NEXT: addi a2, a3, 8
14 %wb = icmp sgt i32 %a, %b
15 br i1 %wb, label %t1, label %t2
23 %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
27 define i32 @brcc_ugt(i32 %a, i32 %b) nounwind {
28 ; CHECK-LABEL: brcc_ugt:
29 ; CHECK: bgeu a3, a2, .LBB1_2
30 ; CHECK-NEXT: # %bb.1: # %t1
31 ; CHECK-NEXT: addi a2, a2, 4
33 ; CHECK-NEXT: .LBB1_2: # %t2
34 ; CHECK-NEXT: addi a2, a3, 8
36 %wb = icmp ugt i32 %a, %b
37 br i1 %wb, label %t1, label %t2
45 %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
49 define i32 @brcc_sle(i32 %a, i32 %b) nounwind {
50 ; CHECK-LABEL: brcc_sle:
51 ; CHECK: blt a3, a2, .LBB2_2
52 ; CHECK-NEXT: # %bb.1: # %t1
53 ; CHECK-NEXT: addi a2, a2, 4
55 ; CHECK-NEXT: .LBB2_2: # %t2
56 ; CHECK-NEXT: addi a2, a3, 8
58 %wb = icmp sle i32 %a, %b
59 br i1 %wb, label %t1, label %t2
67 %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
71 define i32 @brcc_ule(i32 %a, i32 %b) nounwind {
72 ; CHECK-LABEL: brcc_ule:
73 ; CHECK: bltu a3, a2, .LBB3_2
74 ; CHECK-NEXT: # %bb.1: # %t1
75 ; CHECK-NEXT: addi a2, a2, 4
77 ; CHECK-NEXT: .LBB3_2: # %t2
78 ; CHECK-NEXT: addi a2, a3, 8
80 %wb = icmp ule i32 %a, %b
81 br i1 %wb, label %t1, label %t2
89 %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
93 define i32 @brcc_eq(i32 %a, i32 %b) nounwind {
94 ; CHECK-LABEL: brcc_eq:
95 ; CHECK: bne a2, a3, .LBB4_2
96 ; CHECK-NEXT: # %bb.1: # %t1
97 ; CHECK-NEXT: addi a2, a2, 4
99 ; CHECK-NEXT: .LBB4_2: # %t2
100 ; CHECK-NEXT: addi a2, a3, 8
102 %wb = icmp eq i32 %a, %b
103 br i1 %wb, label %t1, label %t2
111 %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
115 define i32 @brcc_ne(i32 %a, i32 %b) nounwind {
116 ; CHECK-LABEL: brcc_ne:
117 ; CHECK: beq a2, a3, .LBB5_2
118 ; CHECK-NEXT: # %bb.1: # %t1
119 ; CHECK-NEXT: addi a2, a2, 4
121 ; CHECK-NEXT: .LBB5_2: # %t2
122 ; CHECK-NEXT: addi a2, a3, 8
124 %wb = icmp ne i32 %a, %b
125 br i1 %wb, label %t1, label %t2
133 %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
137 define i32 @brcc_ge(i32 %a, i32 %b) nounwind {
138 ; CHECK-LABEL: brcc_ge:
139 ; CHECK: blt a2, a3, .LBB6_2
140 ; CHECK-NEXT: # %bb.1: # %t1
141 ; CHECK-NEXT: addi a2, a2, 4
143 ; CHECK-NEXT: .LBB6_2: # %t2
144 ; CHECK-NEXT: addi a2, a3, 8
146 %wb = icmp sge i32 %a, %b
147 br i1 %wb, label %t1, label %t2
155 %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
159 define i32 @brcc_lt(i32 %a, i32 %b) nounwind {
160 ; CHECK-LABEL: brcc_lt:
161 ; CHECK: bge a2, a3, .LBB7_2
162 ; CHECK-NEXT: # %bb.1: # %t1
163 ; CHECK-NEXT: addi a2, a2, 4
165 ; CHECK-NEXT: .LBB7_2: # %t2
166 ; CHECK-NEXT: addi a2, a3, 8
168 %wb = icmp slt i32 %a, %b
169 br i1 %wb, label %t1, label %t2
177 %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
181 define i32 @brcc_uge(i32 %a, i32 %b) nounwind {
182 ; CHECK-LABEL: brcc_uge:
183 ; CHECK: bltu a2, a3, .LBB8_2
184 ; CHECK-NEXT: # %bb.1: # %t1
185 ; CHECK-NEXT: addi a2, a2, 4
187 ; CHECK-NEXT: .LBB8_2: # %t2
188 ; CHECK-NEXT: addi a2, a3, 8
190 %wb = icmp uge i32 %a, %b
191 br i1 %wb, label %t1, label %t2
199 %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]
203 define i32 @brcc_ult(i32 %a, i32 %b) nounwind {
204 ; CHECK-LABEL: brcc_ult:
205 ; CHECK: bgeu a2, a3, .LBB9_2
206 ; CHECK-NEXT: # %bb.1: # %t1
207 ; CHECK-NEXT: addi a2, a2, 4
209 ; CHECK-NEXT: .LBB9_2: # %t2
210 ; CHECK-NEXT: addi a2, a3, 8
212 %wb = icmp ult i32 %a, %b
213 br i1 %wb, label %t1, label %t2
221 %v = phi i32 [ %t1v, %t1 ], [ %t2v, %t2 ]