[RISCV] Check isFixedLengthVector before calling getVectorNumElements in getSingleShu...
[llvm-project.git] / llvm / test / MC / AArch64 / FP8_SME2 / lut-diagnostics.s
blob36a5b12bc4823177ecf90ac5488bbe806203f94a
1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-lutv2 2>&1 < %s | FileCheck %s
3 // --------------------------------------------------------------------------//
4 // Invalid vector select register
6 luti4 {z0-z3}, zt0, {z0.b-z1.b}
7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8 // CHECK-NEXT: luti4 {z0-z3}, zt0, {z0.b-z1.b}
9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
11 luti4 {z0.d, z4.d, z8.d, z12.d}, zt0, {z0-z1}
12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
13 // CHECK-NEXT: luti4 {z0.d, z4.d, z8.d, z12.d}, zt0, {z0-z1}
14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
16 // --------------------------------------------------------------------------//
17 // Invalid vector grouping
19 luti4 {z0.b-z1.b}, zt0, {z0-z4}
20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
21 // CHECK-NEXT: luti4 {z0.b-z1.b}, zt0, {z0-z4}
22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
24 luti4 {z0.b - z12.b}, zt0, {z0-z1}
25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
26 // CHECK-NEXT: luti4 {z0.b - z12.b}, zt0, {z0-z1}
27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: