llvm/test/MC/AArch64/SME2/bfmls-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-b16b16 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 bfmls za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: bfmls za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 bfmls za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  13 // CHECK-NEXT: bfmls za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 bfmls za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  18 // CHECK-NEXT: bfmls za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h}
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
  23 // CHECK-NEXT: bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h}
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 // --------------------------------------------------------------------------//
  27 // Invalid indexed-vector or single-vector register
  28
  29 bfmls za.h[w8, 0], {z0.h-z1.h}, z16.h[0]
  30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  31 // CHECK-NEXT: bfmls za.h[w8, 0], {z0.h-z1.h}, z16.h[0]
  32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  33
  34 bfmls za.h[w8, 1], {z0.h-z3.h}, z16.h
  35 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  36 // CHECK-NEXT: bfmls za.h[w8, 1], {z0.h-z3.h}, z16.h
  37 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  38
  39 // --------------------------------------------------------------------------//
  40 // Invalid vector select register
  41
  42 bfmls za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
  43 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  44 // CHECK-NEXT: bfmls za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
  45 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  46
  47 bfmls za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  48 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  49 // CHECK-NEXT: bfmls za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  50 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  51
  52 // --------------------------------------------------------------------------//
  53 // Invalid vector select offset
  54
  55 bfmls za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
  57 // CHECK-NEXT: bfmls za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  59
  60 bfmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  61 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
  62 // CHECK-NEXT: bfmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  63 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  64
  65 // --------------------------------------------------------------------------//
  66 // Invalid Register Suffix
  67
  68 bfmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  69 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h
  70 // CHECK-NEXT: bfmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  71 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  72
  73 // --------------------------------------------------------------------------//
  74 // Invalid vector lane index
  75
  76 bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8]
  77 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
  78 // CHECK-NEXT: bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8]
  79 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  80
  81 bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1]
  82 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
  83 // CHECK-NEXT: bfmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1]
  84 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  85
  86 bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1]
  87 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
  88 // CHECK-NEXT: bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1]
  89 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  90
  91 bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8]
  92 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
  93 // CHECK-NEXT: bfmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8]
  94 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: