llvm/test/MC/AArch64/SME2/bfmopa-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-b16b16 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid predicate register
   5
   6 bfmopa za1.h, p8/m, p5/m, z12.h, z11.h
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
   8 // CHECK-NEXT: bfmopa za1.h, p8/m, p5/m, z12.h, z11.h
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 bfmopa za1.h, p5/m, p8/m, z12.h, z11.h
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  13 // CHECK-NEXT: bfmopa za1.h, p5/m, p8/m, z12.h, z11.h
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 bfmopa za1.h, p5.h, p5/m, z12.h, z11.h
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  18 // CHECK-NEXT: bfmopa za1.h, p5.h, p5/m, z12.h, z11.h
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 // --------------------------------------------------------------------------//
  22 // Invalid matrix operand
  23
  24 bfmopa za2.h, p5/m, p5/m, z12.h, z11.h
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  26 // CHECK-NEXT: bfmopa za2.h, p5/m, p5/m, z12.h, z11.h
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  28
  29 // --------------------------------------------------------------------------//
  30 // Invalid register suffixes
  31
  32 bfmopa za1.h, p5/m, p5/m, z12.h, z11.b
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  34 // CHECK-NEXT: bfmopa za1.h, p5/m, p5/m, z12.h, z11.b
  35 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: