llvm/test/MC/AArch64/SME2/fmls-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-f64f64 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Out of range index offset
   5
   6 fmls za.s[w8, 8], {z20.s-z21.s}, z10.s
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
   8 // CHECK-NEXT: fmls za.s[w8, 8], {z20.s-z21.s}, z10.s
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 fmls za.d[w8, -1, vgx4], {z0.s-z3.s}, z0.s
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
  13 // CHECK-NEXT: fmls za.d[w8, -1, vgx4], {z0.s-z3.s}, z0.s
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 // --------------------------------------------------------------------------//
  17 // Invalid vector select register
  18
  19 fmls za.d[w7, 0], {z0.d-z3.d}, z0.d
  20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  21 // CHECK-NEXT: fmls za.d[w7, 0], {z0.d-z3.d}, z0.d
  22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  23
  24 fmls za.s[w12, 0], {z0.s-z1.s}, z0.s
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  26 // CHECK-NEXT: fmls za.s[w12, 0], {z0.s-z1.s}, z0.s
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  28
  29 // --------------------------------------------------------------------------//
  30 // Invalid Matrix Operand
  31
  32 fmls za.b[w8, #0], {z0.b-z3.b}, z4.b
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
  34 // CHECK-NEXT: fmls za.b[w8, #0], {z0.b-z3.b}, z4.b
  35 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  36
  37
  38 // --------------------------------------------------------------------------//
  39 // Invalid vector grouping
  40
  41 fmls za.s[w8, 0, vgx4], {z0.s-z1.s}, z0.s
  42 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  43 // CHECK-NEXT: za.s[w8, 0, vgx4], {z0.s-z1.s}, z0.s
  44 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  45
  46 fmls za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
  47 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  48 // CHECK-NEXT: za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
  49 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  50
  51 // --------------------------------------------------------------------------//
  52 // Invalid vector list.
  53
  54 fmls za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
  55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  56 // CHECK-NEXT: fmls za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
  57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  58
  59 fmls za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
  60 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  61 // CHECK-NEXT: fmls za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
  62 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  63
  64 fmls za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
  65 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
  66 // CHECK-NEXT: fmls za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
  67 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  68
  69 fmls za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
  70 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  71 // CHECK-NEXT: fmls za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
  72 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  73
  74 fmls     za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
  75 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  76 // CHECK-NEXT: fmls     za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
  77 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: