[AMDGPU][True16][CodeGen] true16 codegen pattern for v_med3_u/i16 (#121850)
[llvm-project.git] / llvm / test / MC / AArch64 / spe.s
bloba4b2a555621fef3670714c860c50302903715cce
1 // RUN: llvm-mc -triple aarch64 -mattr +spe-eef -show-encoding %s 2>%t | FileCheck %s
2 // RUN: llvm-mc -triple aarch64 -mattr +v8.7a -show-encoding %s 2>%t | FileCheck %s
3 // RUN: not llvm-mc -triple aarch64 < %s 2>&1 | FileCheck --check-prefix=CHECK-NO-SPE-EEF-ERR %s
5 msr PMSNEVFR_EL1, x0
6 mrs x1, PMSNEVFR_EL1
7 // CHECK: msr PMSNEVFR_EL1, x0 // encoding: [0x20,0x99,0x18,0xd5]
8 // CHECK: mrs x1, PMSNEVFR_EL1 // encoding: [0x21,0x99,0x38,0xd5]
10 // CHECK-NO-SPE-EEF-ERR: [[@LINE-5]]:5: error: expected writable system register or pstate
11 // CHECK-NO-SPE-EEF-ERR: [[@LINE-5]]:9: error: expected readable system register