[AMDGPU] Add commute for some VOP3 inst (#121326)
[llvm-project.git] / llvm / test / MC / AArch64 / win-import-call-optimization.s
blobf26e17b9b62cc06a1eb228b49fe9ad2934956558
1 // RUN: llvm-mc -triple aarch64-windows-msvc -filetype obj -o %t.obj %s
2 // RUN: llvm-readobj --sections --sd --relocs %t.obj | FileCheck %s
4 .section nc_sect,"xr"
5 normal_call:
6 str x30, [sp, #-16]! // 8-byte Folded Spill
7 adrp x8, __imp_a
8 ldr x8, [x8, :lo12:__imp_a]
9 .Limpcall0:
10 blr x8
11 ldr x30, [sp], #16 // 8-byte Folded Reload
12 ret
14 .section tc_sect,"xr"
15 tail_call:
16 adrp x8, __imp_b
17 ldr x8, [x8, :lo12:__imp_b]
18 .Limpcall1:
19 br x8
21 .section .impcall,"yi"
22 .asciz "Imp_Call_V1"
23 .word 20
24 .secnum nc_sect
25 .word 19
26 .secoffset .Limpcall0
27 .symidx __imp_a
28 .word 20
29 .secnum tc_sect
30 .word 19
31 .secoffset .Limpcall1
32 .symidx __imp_b
34 // CHECK-LABEL: Name: .impcall (2E 69 6D 70 63 61 6C 6C)
35 // CHECK-NEXT: VirtualSize: 0x0
36 // CHECK-NEXT: VirtualAddress: 0x0
37 // CHECK-NEXT: RawDataSize: 52
38 // CHECK-NEXT: PointerToRawData: 0x150
39 // CHECK-NEXT: PointerToRelocations: 0x0
40 // CHECK-NEXT: PointerToLineNumbers: 0x0
41 // CHECK-NEXT: RelocationCount: 0
42 // CHECK-NEXT: LineNumberCount: 0
43 // CHECK-NEXT: Characteristics [
44 // CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES
45 // CHECK-NEXT: IMAGE_SCN_LNK_INFO
46 // CHECK-NEXT: ]
47 // CHECK-NEXT: SectionData (
48 // CHECK-NEXT: 0000: 496D705F 43616C6C 5F563100 14000000 |Imp_Call_V1.....|
49 // CHECK-NEXT: 0010:
50 // CHECK-SAME: [[#%.2X,NCSECT:]]000000
51 // CHECK-SAME: 13000000
52 // CHECK-SAME: [[#%.2X,NCOFFSET:]]000000
53 // CHECK-SAME: [[#%.2X,NCSYM:]]000000
54 // CHECK-NEXT: 0020:
55 // CHECK-SAME: 14000000
56 // CHECK-SAME: [[#%.2X,TCSECT:]]000000
57 // CHECK-SAME: 13000000
58 // CHECK-SAME: [[#%.2X,TCOFFSET:]]000000
59 // CHECK-NEXT: 0030:
60 // CHECK-SAME: [[#%.2X,TCSYM:]]000000
61 // CHECK-NEXT: )
63 // CHECK-LABEL: Relocations [
64 // CHECK-NEXT: Section ([[#%u,NCSECT]]) nc_sect {
65 // CHECK-NEXT: 0x[[#%x,NCOFFSET - 8]] IMAGE_REL_ARM64_PAGEBASE_REL21 __imp_a ([[#%u,NCSYM]])
66 // CHECK-NEXT: 0x[[#%x,NCOFFSET - 4]] IMAGE_REL_ARM64_PAGEOFFSET_12L __imp_a ([[#%u,NCSYM]])
67 // CHECK-NEXT: }
68 // CHECK-NEXT: Section ([[#%u,TCSECT]]) tc_sect {
69 // CHECK-NEXT: 0x[[#%x,TCOFFSET - 8]] IMAGE_REL_ARM64_PAGEBASE_REL21 __imp_b ([[#%u,TCSYM]])
70 // CHECK-NEXT: 0x[[#%x,TCOFFSET - 4]] IMAGE_REL_ARM64_PAGEOFFSET_12L __imp_b ([[#%u,TCSYM]])
71 // CHECK-NEXT: }
72 // CHECK-NEXT: ]