llvm/test/MC/AMDGPU/gfx10_err_pos.s

   1 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck %s --implicit-check-not=error: --strict-whitespace
   2
   3 //==============================================================================
   4 // operands are not valid for this GPU or mode
   5
   6 image_atomic_add v252, v2, s[8:15]
   7 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing dim operand
   8 // CHECK-NEXT:{{^}}image_atomic_add v252, v2, s[8:15]
   9 // CHECK-NEXT:{{^}}^
  10
  11 //==============================================================================
  12 // duplicate data format
  13
  14 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8]
  15 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate data format
  16 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_DATA_FORMAT_8]
  17 // CHECK-NEXT:{{^}}                                                                                ^
  18
  19 //==============================================================================
  20 // duplicate numeric format
  21
  22 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT]
  23 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: duplicate numeric format
  24 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT,BUF_NUM_FORMAT_FLOAT]
  25 // CHECK-NEXT:{{^}}                                                                                 ^
  26
  27 //==============================================================================
  28 // expected ')' in parentheses expression
  29
  30 v_bfe_u32 v0, 1+(100, v1, v2
  31 // CHECK: :[[#@LINE-1]]:21: error: expected ')'
  32 // CHECK-NEXT:{{^}}v_bfe_u32 v0, 1+(100, v1, v2
  33 // CHECK-NEXT:{{^}}                    ^
  34
  35 //==============================================================================
  36 // expected a 12-bit signed offset
  37
  38 global_load_dword v1, v[3:4] off, offset:-4097
  39 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 12-bit signed offset
  40 // CHECK-NEXT:{{^}}global_load_dword v1, v[3:4] off, offset:-4097
  41 // CHECK-NEXT:{{^}}                                  ^
  42
  43 scratch_load_dword v0, v1, off offset:-2049 glc slc
  44 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 12-bit signed offset
  45 // CHECK-NEXT:{{^}}scratch_load_dword v0, v1, off offset:-2049 glc slc
  46 // CHECK-NEXT:{{^}}                               ^
  47
  48 //==============================================================================
  49 // expected a 16-bit signed jump offset
  50
  51 s_branch 0x10000
  52 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 16-bit signed jump offset
  53 // CHECK-NEXT:{{^}}s_branch 0x10000
  54 // CHECK-NEXT:{{^}}         ^
  55
  56 //==============================================================================
  57 // expected a 2-bit lane id
  58
  59 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3)
  60 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 2-bit lane id
  61 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 4, 1, 2, 3)
  62 // CHECK-NEXT:{{^}}                                                ^
  63
  64 //==============================================================================
  65 // expected a 20-bit unsigned offset
  66
  67 s_atc_probe_buffer 0x1, s[8:11], -1
  68 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 20-bit unsigned offset
  69 // CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], -1
  70 // CHECK-NEXT:{{^}}                                 ^
  71
  72 s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000
  73 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 20-bit unsigned offset
  74 // CHECK-NEXT:{{^}}s_atc_probe_buffer 0x1, s[8:11], 0xFFFFFFFFFFF00000
  75 // CHECK-NEXT:{{^}}                                 ^
  76
  77 s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF
  78 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 20-bit unsigned offset
  79 // CHECK-NEXT:{{^}}s_buffer_atomic_swap s5, s[4:7], 0x1FFFFF
  80 // CHECK-NEXT:{{^}}                                 ^
  81
  82 //==============================================================================
  83 // expected a 21-bit signed offset
  84
  85 s_atc_probe 0x7, s[4:5], 0x1FFFFF
  86 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 21-bit signed offset
  87 // CHECK-NEXT:{{^}}s_atc_probe 0x7, s[4:5], 0x1FFFFF
  88 // CHECK-NEXT:{{^}}                         ^
  89
  90 s_atomic_swap s5, s[2:3], 0x1FFFFF
  91 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 21-bit signed offset
  92 // CHECK-NEXT:{{^}}s_atomic_swap s5, s[2:3], 0x1FFFFF
  93 // CHECK-NEXT:{{^}}                          ^
  94
  95 //==============================================================================
  96 // expected a 2-bit value
  97
  98 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,4] row_mask:0x0 bank_mask:0x0
  99 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 2-bit value
 100 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,4] row_mask:0x0 bank_mask:0x0
 101 // CHECK-NEXT:{{^}}                                      ^
 102
 103 v_mov_b32_dpp v5, v1 quad_perm:[3,-1,1,3] row_mask:0x0 bank_mask:0x0
 104 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 2-bit value
 105 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,-1,1,3] row_mask:0x0 bank_mask:0x0
 106 // CHECK-NEXT:{{^}}                                  ^
 107
 108 //==============================================================================
 109 // expected a 3-bit value
 110
 111 v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
 112 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 3-bit value
 113 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[-1,1,2,3,4,5,6,7]
 114 // CHECK-NEXT:{{^}}                           ^
 115
 116 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
 117 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 3-bit value
 118 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,8,4,5,6,7]
 119 // CHECK-NEXT:{{^}}                                 ^
 120
 121 //==============================================================================
 122 // expected a 5-character mask
 123
 124 ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")
 125 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 5-character mask
 126 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "ppii")
 127 // CHECK-NEXT:{{^}}                                                   ^
 128
 129 //==============================================================================
 130 // expected a closing parentheses
 131
 132 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3
 133 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parentheses
 134 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3
 135 // CHECK-NEXT:{{^}}                                                          ^
 136
 137 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4)
 138 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parentheses
 139 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3, 4)
 140 // CHECK-NEXT:{{^}}                                                          ^
 141
 142 //==============================================================================
 143 // expected a closing parenthesis
 144
 145 s_sendmsg sendmsg(2, 2, 0, 0)
 146 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parenthesis
 147 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 0, 0)
 148 // CHECK-NEXT:{{^}}                         ^
 149
 150 s_waitcnt vmcnt(0
 151 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing parenthesis
 152 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0
 153 // CHECK-NEXT:{{^}}                 ^
 154
 155 //==============================================================================
 156 // expected a closing square bracket
 157
 158 s_mov_b32 s1, s[0 1
 159 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 160 // CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 1
 161 // CHECK-NEXT:{{^}}                  ^
 162
 163 s_mov_b32 s1, s[0 s0
 164 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 165 // CHECK-NEXT:{{^}}s_mov_b32 s1, s[0 s0
 166 // CHECK-NEXT:{{^}}                  ^
 167
 168 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8]
 169 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 170 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT,BUF_DATA_FORMAT_8]
 171 // CHECK-NEXT:{{^}}                                                                                                    ^
 172
 173 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT
 174 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 175 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_NUM_FORMAT_UINT
 176 // CHECK-NEXT:{{^}}                                                                                ^
 177
 178 v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1
 179 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 180 // CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1 1
 181 // CHECK-NEXT:{{^}}                                          ^
 182
 183 v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1,
 184 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 185 // CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1,
 186 // CHECK-NEXT:{{^}}                                         ^
 187
 188 v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[
 189 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 190 // CHECK-NEXT:{{^}}v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1[
 191 // CHECK-NEXT:{{^}}                                         ^
 192
 193 v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
 194 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 195 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,0,0,0,0]
 196 // CHECK-NEXT:{{^}}                                       ^
 197
 198 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
 199 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 200 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7)
 201 // CHECK-NEXT:{{^}}                                          ^
 202
 203 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0) row_mask:0x0 bank_mask:0x0
 204 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a closing square bracket
 205 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0) row_mask:0x0 bank_mask:0x0
 206 // CHECK-NEXT:{{^}}                                       ^
 207
 208 //==============================================================================
 209 // expected a colon
 210
 211 ds_swizzle_b32 v8, v2 offset
 212 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a colon
 213 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset
 214 // CHECK-NEXT:{{^}}                            ^
 215
 216 ds_swizzle_b32 v8, v2 offset-
 217 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a colon
 218 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset-
 219 // CHECK-NEXT:{{^}}                            ^
 220
 221 //==============================================================================
 222 // expected a comma
 223
 224 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM
 225 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 226 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM
 227 // CHECK-NEXT:{{^}}                                              ^
 228
 229 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2)
 230 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 231 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2)
 232 // CHECK-NEXT:{{^}}                                                       ^
 233
 234 s_setreg_b32  hwreg(1,2 3), s2
 235 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 236 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(1,2 3), s2
 237 // CHECK-NEXT:{{^}}                        ^
 238
 239 v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
 240 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 241 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0 0]
 242 // CHECK-NEXT:{{^}}                                  ^
 243
 244 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
 245 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 246 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6]
 247 // CHECK-NEXT:{{^}}                                        ^
 248
 249 v_mov_b32_dpp v5, v1 quad_perm:[3,2] row_mask:0x0 bank_mask:0x0
 250 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma
 251 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,2] row_mask:0x0 bank_mask:0x0
 252 // CHECK-NEXT:{{^}}                                   ^
 253
 254 //==============================================================================
 255 // expected a comma or a closing parenthesis
 256
 257 s_setreg_b32  hwreg(1 2,3), s2
 258 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing parenthesis
 259 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(1 2,3), s2
 260 // CHECK-NEXT:{{^}}                      ^
 261
 262 //==============================================================================
 263 // expected a comma or a closing square bracket
 264
 265 s_mov_b64 s[10:11], [s0
 266 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket
 267 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0
 268 // CHECK-NEXT:{{^}}                       ^
 269
 270 s_mov_b64 s[10:11], [s0,s1
 271 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket
 272 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s1
 273 // CHECK-NEXT:{{^}}                          ^
 274
 275 image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D
 276 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket
 277 // CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254 dmask:0xe dim:1D
 278 // CHECK-NEXT:{{^}}                                       ^
 279
 280 image_load_mip v[253:255], [v255, v254
 281 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a comma or a closing square bracket
 282 // CHECK-NEXT:{{^}}image_load_mip v[253:255], [v255, v254
 283 // CHECK-NEXT:{{^}}                                      ^
 284
 285 //==============================================================================
 286 // expected a counter name
 287
 288 s_waitcnt vmcnt(0) & expcnt(0) & 1
 289 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
 290 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & 1
 291 // CHECK-NEXT:{{^}}                                 ^
 292
 293 s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)&
 294 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
 295 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)&
 296 // CHECK-NEXT:{{^}}                                            ^
 297
 298 s_waitcnt vmcnt(0) & expcnt(0) 1
 299 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
 300 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) 1
 301 // CHECK-NEXT:{{^}}                               ^
 302
 303 s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0),
 304 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a counter name
 305 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0),
 306 // CHECK-NEXT:{{^}}                                          ^
 307
 308 //==============================================================================
 309 // expected a format string
 310
 311 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[]
 312 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a format string
 313 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[]
 314 // CHECK-NEXT:{{^}}                                                             ^
 315
 316 //==============================================================================
 317 // expected a left parenthesis
 318
 319 s_waitcnt vmcnt(0) & expcnt(0) & x
 320 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left parenthesis
 321 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) & x
 322 // CHECK-NEXT:{{^}}                                  ^
 323
 324 //==============================================================================
 325 // expected a left square bracket
 326
 327 v_pk_add_u16 v1, v2, v3 op_sel:
 328 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left square bracket
 329 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:
 330 // CHECK-NEXT:{{^}}                               ^
 331
 332 //==============================================================================
 333 // expected a register
 334
 335 image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm
 336 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register
 337 // CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, 6], s[8:15] dmask:0xf dim:3D unorm
 338 // CHECK-NEXT:{{^}}                            ^
 339
 340 image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm
 341 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register
 342 // CHECK-NEXT:{{^}}image_load v[0:3], [v4, v5, v], s[8:15] dmask:0xf dim:3D unorm
 343 // CHECK-NEXT:{{^}}                            ^
 344
 345 //==============================================================================
 346 // expected a register or a list of registers
 347
 348 s_mov_b32 s1, [s0, 1
 349 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register or a list of registers
 350 // CHECK-NEXT:{{^}}s_mov_b32 s1, [s0, 1
 351 // CHECK-NEXT:{{^}}                   ^
 352
 353 //==============================================================================
 354 // expected a single 32-bit register
 355
 356 s_mov_b64 s[10:11], [s0,s[2:3]]
 357 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a single 32-bit register
 358 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s[2:3]]
 359 // CHECK-NEXT:{{^}}                        ^
 360
 361 //==============================================================================
 362 // expected a string
 363
 364 ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii)
 365 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a string
 366 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, pppii)
 367 // CHECK-NEXT:{{^}}                                                   ^
 368
 369 //==============================================================================
 370 // expected a swizzle mode
 371
 372 ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)
 373 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a swizzle mode
 374 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)
 375 // CHECK-NEXT:{{^}}                                     ^
 376
 377 //==============================================================================
 378 // expected absolute expression
 379
 380 s_waitcnt vmcnt(x)
 381 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 382 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(x)
 383 // CHECK-NEXT:{{^}}                ^
 384
 385 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32]
 386 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 387 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], format:[BUF_DATA_FORMAT_32]
 388 // CHECK-NEXT:{{^}}                                                         ^
 389
 390 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52
 391 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 392 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format: offset:52
 393 // CHECK-NEXT:{{^}}                                                             ^
 394
 395 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]
 396 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 397 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:BUF_NUM_FORMAT_UINT]
 398 // CHECK-NEXT:{{^}}                                                            ^
 399
 400 v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
 401 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 402 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:[0,1,2,x,4,5,6,7]
 403 // CHECK-NEXT:{{^}}                                 ^
 404
 405 v_mov_b32_dpp v5, v1 quad_perm:[3,x,1,0] row_mask:0x0 bank_mask:0x0
 406 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 407 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:[3,x,1,0] row_mask:0x0 bank_mask:0x0
 408 // CHECK-NEXT:{{^}}                                  ^
 409
 410 v_mov_b32_dpp v5, v1 row_share:x row_mask:0x0 bank_mask:0x0
 411 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 412 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:x row_mask:0x0 bank_mask:0x0
 413 // CHECK-NEXT:{{^}}                               ^
 414
 415 //==============================================================================
 416 // expected a message name or an absolute expression
 417
 418 s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0)
 419 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a message name or an absolute expression
 420 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GSX, GS_OP_CUT, 0)
 421 // CHECK-NEXT:{{^}}                  ^
 422
 423 //==============================================================================
 424 // expected a register name or an absolute expression
 425
 426 s_setreg_b32  hwreg(HW_REG_WRONG), s2
 427 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a register name or an absolute expression
 428 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(HW_REG_WRONG), s2
 429 // CHECK-NEXT:{{^}}                    ^
 430
 431 //==============================================================================
 432 // expected a sendmsg macro or an absolute expression
 433
 434 s_sendmsg undef
 435 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a sendmsg macro or an absolute expression
 436 // CHECK-NEXT:{{^}}s_sendmsg undef
 437 // CHECK-NEXT:{{^}}          ^
 438
 439 //==============================================================================
 440 // expected a swizzle macro or an absolute expression
 441
 442 ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
 443 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a swizzle macro or an absolute expression
 444 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:SWZ(QUAD_PERM, 0, 1, 2, 3)
 445 // CHECK-NEXT:{{^}}                             ^
 446
 447 //==============================================================================
 448 // expected a hwreg macro or an absolute expression
 449
 450 s_setreg_b32 undef, s2
 451 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a hwreg macro, structured immediate or an absolute expression
 452 // CHECK-NEXT:{{^}}s_setreg_b32 undef, s2
 453 // CHECK-NEXT:{{^}}             ^
 454
 455 //==============================================================================
 456 // expected an 11-bit unsigned offset
 457
 458 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
 459 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 11-bit unsigned offset
 460 // CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
 461 // CHECK-NEXT:{{^}}                                       ^
 462
 463 //==============================================================================
 464 // expected an absolute expression
 465
 466 v_ceil_f32 v1, abs(u)
 467 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression
 468 // CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(u)
 469 // CHECK-NEXT:{{^}}                   ^
 470
 471 v_ceil_f32 v1, neg(u)
 472 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression
 473 // CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(u)
 474 // CHECK-NEXT:{{^}}                   ^
 475
 476 v_ceil_f32 v1, |u|
 477 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression
 478 // CHECK-NEXT:{{^}}v_ceil_f32 v1, |u|
 479 // CHECK-NEXT:{{^}}                ^
 480
 481 v_mov_b32_sdwa v1, sext(u)
 482 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression
 483 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, sext(u)
 484 // CHECK-NEXT:{{^}}                        ^
 485
 486 //==============================================================================
 487 // expected a valid identifier or number in a valid range
 488
 489 v_mov_b32_sdwa v5, v1 dst_sel:
 490 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
 491 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:
 492 // CHECK-NEXT:{{^}}                              ^
 493
 494 v_mov_b32_sdwa v5, v1 dst_sel:0a
 495 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 496 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:0a
 497 // CHECK-NEXT:{{^}}                               ^
 498
 499 v_mov_b32_sdwa v5, v1 dst_sel:BYTE_1x
 500 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_sel value
 501 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:BYTE_1
 502 // CHECK-NEXT:{{^}}                              ^
 503
 504 v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD]
 505 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected absolute expression
 506 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:[UNUSED_PAD]
 507 // CHECK-NEXT:{{^}}                                               ^
 508
 509 v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:XXX
 510 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_unused value
 511 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:XXX
 512 // CHECK-NEXT:{{^}}                                               ^
 513
 514 v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:3
 515 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_unused value
 516 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:3
 517 // CHECK-NEXT:{{^}}                                               ^
 518
 519 v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:-1
 520 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_unused value
 521 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:-1
 522 // CHECK-NEXT:{{^}}                                               ^
 523
 524 //==============================================================================
 525 // expected an opening square bracket
 526
 527 v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)
 528 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an opening square bracket
 529 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 dpp8:(0,1,2,3,4,5,6,7)
 530 // CHECK-NEXT:{{^}}                          ^
 531
 532 v_mov_b32_dpp v5, v1 quad_perm:(3,2,1,0) row_mask:0x0 bank_mask:0x0
 533 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an opening square bracket
 534 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 quad_perm:(3,2,1,0) row_mask:0x0 bank_mask:0x0
 535 // CHECK-NEXT:{{^}}                               ^
 536
 537 //==============================================================================
 538 // expected an operation name or an absolute expression
 539
 540 s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)
 541 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an operation name or an absolute expression
 542 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUTX, 0)
 543 // CHECK-NEXT:{{^}}                          ^
 544
 545 //==============================================================================
 546 // failed parsing operand.
 547
 548 v_ceil_f16 v0, abs(neg(1))
 549 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: failed parsing operand.
 550 // CHECK-NEXT:{{^}}v_ceil_f16 v0, abs(neg(1))
 551 // CHECK-NEXT:{{^}}                   ^
 552
 553 //==============================================================================
 554 // first register index should not exceed second index
 555
 556 s_mov_b64 s[10:11], s[1:0]
 557 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: first register index should not exceed second index
 558 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], s[1:0]
 559 // CHECK-NEXT:{{^}}                      ^
 560
 561 //==============================================================================
 562 // group size must be a power of two
 563
 564 ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)
 565 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be a power of two
 566 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)
 567 // CHECK-NEXT:{{^}}                                               ^
 568
 569 ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
 570 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be a power of two
 571 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
 572 // CHECK-NEXT:{{^}}                                             ^
 573
 574 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)
 575 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be a power of two
 576 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)
 577 // CHECK-NEXT:{{^}}                                          ^
 578
 579 //==============================================================================
 580 // group size must be in the interval [1,16]
 581
 582 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0)
 583 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be in the interval [1,16]
 584 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0)
 585 // CHECK-NEXT:{{^}}                                          ^
 586
 587 //==============================================================================
 588 // group size must be in the interval [2,32]
 589
 590 ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0)
 591 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: group size must be in the interval [2,32]
 592 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,1,0)
 593 // CHECK-NEXT:{{^}}                                               ^
 594
 595 //==============================================================================
 596 // image address size does not match dim and a16
 597
 598 image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
 599 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: image address size does not match dim and a16
 600 // CHECK-NEXT:{{^}}image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D
 601 // CHECK-NEXT:{{^}}^
 602
 603 //==============================================================================
 604 // image data size does not match dmask, d16 and tfe
 605
 606 image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
 607 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: image data size does not match dmask, d16 and tfe
 608 // CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
 609 // CHECK-NEXT:{{^}}^
 610
 611 //==============================================================================
 612 // instruction must use glc
 613
 614 flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047
 615 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction must use glc
 616 // CHECK-NEXT:{{^}}flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:2047
 617 // CHECK-NEXT:{{^}}^
 618
 619 //==============================================================================
 620 // instruction not supported on this GPU
 621
 622 s_cbranch_join 1
 623 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 624 // CHECK-NEXT:{{^}}s_cbranch_join 1
 625 // CHECK-NEXT:{{^}}^
 626
 627 //==============================================================================
 628 // invalid bit offset: only 5-bit values are legal
 629
 630 s_getreg_b32  s2, hwreg(3,32,32)
 631 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid bit offset: only 5-bit values are legal
 632 // CHECK-NEXT:{{^}}s_getreg_b32  s2, hwreg(3,32,32)
 633 // CHECK-NEXT:{{^}}                          ^
 634
 635 //==============================================================================
 636 // invalid bitfield width: only values from 1 to 32 are legal
 637
 638 s_setreg_b32  hwreg(3,0,33), s2
 639 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid bitfield width: only values from 1 to 32 are legal
 640 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(3,0,33), s2
 641 // CHECK-NEXT:{{^}}                        ^
 642
 643 //==============================================================================
 644 // invalid hardware register: only 6-bit values are legal
 645
 646 s_setreg_b32  hwreg(0x40), s2
 647 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: only 6-bit values are legal
 648 // CHECK-NEXT:{{^}}s_setreg_b32  hwreg(0x40), s2
 649 // CHECK-NEXT:{{^}}                    ^
 650
 651 //==============================================================================
 652 // invalid counter name x
 653
 654 s_waitcnt vmcnt(0) & expcnt(0) x(0)
 655 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid counter name x
 656 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(0) & expcnt(0) x(0)
 657 // CHECK-NEXT:{{^}}                               ^
 658
 659 //==============================================================================
 660 // invalid dim value
 661
 662 image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
 663 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim value
 664 // CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:1 D
 665 // CHECK-NEXT:{{^}}                                            ^
 666
 667 image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc
 668 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim value
 669 // CHECK-NEXT:{{^}}image_atomic_xor v4, v32, s[96:103] dmask:0x1 dim:, glc
 670 // CHECK-NEXT:{{^}}                                                  ^
 671
 672 image_load v[0:1], v0, s[0:7] dmask:0x9 dim:7D
 673 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dim value
 674 // CHECK-NEXT:{{^}}image_load v[0:1], v0, s[0:7] dmask:0x9 dim:7D
 675 // CHECK-NEXT:{{^}}                                            ^
 676
 677 //==============================================================================
 678 // invalid dst_sel value
 679
 680 v_mov_b32_sdwa v5, v1 dst_sel:WORD
 681 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_sel value
 682 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_sel:WORD
 683 // CHECK-NEXT:{{^}}                              ^
 684
 685 //==============================================================================
 686 // invalid dst_unused value
 687
 688 v_mov_b32_sdwa v5, v1 dst_unused:UNUSED
 689 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid dst_unused value
 690 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v5, v1 dst_unused:UNUSED
 691 // CHECK-NEXT:{{^}}                                 ^
 692
 693 //==============================================================================
 694 // invalid exp target
 695
 696 exp invalid_target_10 v3, v2, v1, v0
 697 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid exp target
 698 // CHECK-NEXT:{{^}}exp invalid_target_10 v3, v2, v1, v0
 699 // CHECK-NEXT:{{^}}    ^
 700
 701 exp pos00 v3, v2, v1, v0
 702 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid exp target
 703 // CHECK-NEXT:{{^}}exp pos00 v3, v2, v1, v0
 704 // CHECK-NEXT:{{^}}    ^
 705
 706 //==============================================================================
 707 // invalid immediate: only 16-bit values are legal
 708
 709 s_setreg_b32  0x1f803, s2
 710 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid immediate: only 16-bit values are legal
 711 // CHECK-NEXT:{{^}}s_setreg_b32  0x1f803, s2
 712 // CHECK-NEXT:{{^}}              ^
 713
 714 //==============================================================================
 715 // invalid instruction
 716
 717 v_dot_f32_f16 v0, v1, v2
 718 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid instruction
 719 // CHECK-NEXT:{{^}}v_dot_f32_f16 v0, v1, v2
 720 // CHECK-NEXT:{{^}}^
 721
 722 //==============================================================================
 723 // invalid interpolation attribute
 724
 725 v_interp_p2_f32 v0, v1, att
 726 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid interpolation attribute
 727 // CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, att
 728 // CHECK-NEXT:{{^}}                        ^
 729
 730 //==============================================================================
 731 // invalid interpolation slot
 732
 733 v_interp_mov_f32 v8, p1, attr0.x
 734 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid interpolation slot
 735 // CHECK-NEXT:{{^}}v_interp_mov_f32 v8, p1, attr0.x
 736 // CHECK-NEXT:{{^}}                     ^
 737
 738 //==============================================================================
 739 // invalid mask
 740
 741 ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2")
 742 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid mask
 743 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BITMASK_PERM, "pppi2")
 744 // CHECK-NEXT:{{^}}                                                   ^
 745
 746 //==============================================================================
 747 // invalid message id
 748
 749 s_sendmsg sendmsg(-1)
 750 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message id
 751 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(-1)
 752 // CHECK-NEXT:{{^}}                  ^
 753
 754 //==============================================================================
 755 // invalid message stream id
 756
 757 s_sendmsg sendmsg(2, 2, 4)
 758 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message stream id
 759 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(2, 2, 4)
 760 // CHECK-NEXT:{{^}}                        ^
 761
 762 s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4)
 763 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid message stream id
 764 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 4)
 765 // CHECK-NEXT:{{^}}                                     ^
 766
 767 //==============================================================================
 768 // invalid mul value.
 769
 770 v_cvt_f64_i32 v[5:6], s1 mul:3
 771 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid mul value.
 772 // CHECK-NEXT:{{^}}v_cvt_f64_i32 v[5:6], s1 mul:3
 773 // CHECK-NEXT:{{^}}                         ^
 774
 775 //==============================================================================
 776 // invalid or missing interpolation attribute channel
 777
 778 v_interp_p2_f32 v0, v1, attr0.q
 779 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid or missing interpolation attribute channel
 780 // CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, attr0.q
 781 // CHECK-NEXT:{{^}}                        ^
 782
 783 //==============================================================================
 784 // invalid or missing interpolation attribute number
 785
 786 v_interp_p2_f32 v7, v1, attr.x
 787 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid or missing interpolation attribute number
 788 // CHECK-NEXT:{{^}}v_interp_p2_f32 v7, v1, attr.x
 789 // CHECK-NEXT:{{^}}                        ^
 790
 791 //==============================================================================
 792 // invalid op_sel operand
 793
 794 v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
 795 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
 796 // CHECK-NEXT:{{^}}v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
 797 // CHECK-NEXT:{{^}}                                ^
 798
 799 //==============================================================================
 800 // invalid op_sel value.
 801
 802 v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]
 803 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel value.
 804 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[-1,0]
 805 // CHECK-NEXT:{{^}}                                ^
 806
 807 //==============================================================================
 808 // invalid operand (violates constant bus restrictions)
 809
 810 v_ashrrev_i64 v[0:1], 0x100, s[0:1]
 811 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 812 // CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], 0x100, s[0:1]
 813 // CHECK-NEXT:{{^}}                             ^
 814
 815 v_ashrrev_i64 v[0:1], s3, s[0:1]
 816 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 817 // CHECK-NEXT:{{^}}v_ashrrev_i64 v[0:1], s3, s[0:1]
 818 // CHECK-NEXT:{{^}}                          ^
 819
 820 v_bfe_u32 v0, s1, 0x3039, s2
 821 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 822 // CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, 0x3039, s2
 823 // CHECK-NEXT:{{^}}                          ^
 824
 825 v_bfe_u32 v0, s1, s2, s3
 826 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 827 // CHECK-NEXT:{{^}}v_bfe_u32 v0, s1, s2, s3
 828 // CHECK-NEXT:{{^}}                      ^
 829
 830 v_div_fmas_f32 v5, s3, 0x123, v3
 831 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 832 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, 0x123, v3
 833 // CHECK-NEXT:{{^}}                       ^
 834
 835 v_div_fmas_f32 v5, s3, v3, 0x123
 836 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 837 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, v3, 0x123
 838 // CHECK-NEXT:{{^}}                           ^
 839
 840 v_div_fmas_f32 v5, 0x123, v3, s3
 841 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 842 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, 0x123, v3, s3
 843 // CHECK-NEXT:{{^}}                              ^
 844
 845 v_div_fmas_f32 v5, s3, s4, v3
 846 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand (violates constant bus restrictions)
 847 // CHECK-NEXT:{{^}}v_div_fmas_f32 v5, s3, s4, v3
 848 // CHECK-NEXT:{{^}}                       ^
 849
 850 //==============================================================================
 851 // invalid operand for instruction
 852
 853 buffer_load_dword v[5:6], off, s[8:11], s3 tfe lds
 854 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 855 // CHECK-NEXT:{{^}}buffer_load_dword v[5:6], off, s[8:11], s3 tfe lds
 856 // CHECK-NEXT:{{^}}                                               ^
 857
 858 exp mrt0 0x12345678, v0, v0, v0
 859 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 860 // CHECK-NEXT:{{^}}exp mrt0 0x12345678, v0, v0, v0
 861 // CHECK-NEXT:{{^}}         ^
 862
 863 v_cmp_eq_f32 s[0:1], private_base, s0
 864 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 865 // CHECK-NEXT:{{^}}v_cmp_eq_f32 s[0:1], private_base, s0
 866 // CHECK-NEXT:{{^}}             ^
 867
 868 //==============================================================================
 869 // invalid operation id
 870
 871 s_sendmsg sendmsg(15, -1)
 872 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operation id
 873 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(15, -1)
 874 // CHECK-NEXT:{{^}}                      ^
 875
 876 //==============================================================================
 877 // invalid or unsupported register size
 878
 879 s_mov_b64 s[0:17], -1
 880 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid or unsupported register size
 881 // CHECK-NEXT:{{^}}s_mov_b64 s[0:17], -1
 882 // CHECK-NEXT:{{^}}          ^
 883
 884 //==============================================================================
 885 // invalid register alignment
 886
 887 s_load_dwordx4 s[1:4], s[2:3], s4
 888 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register alignment
 889 // CHECK-NEXT:{{^}}s_load_dwordx4 s[1:4], s[2:3], s4
 890 // CHECK-NEXT:{{^}}               ^
 891
 892 //==============================================================================
 893 // invalid register index
 894
 895 s_mov_b32 s1, s[0:-1]
 896 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register index
 897 // CHECK-NEXT:{{^}}s_mov_b32 s1, s[0:-1]
 898 // CHECK-NEXT:{{^}}                  ^
 899
 900 v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2]
 901 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register index
 902 // CHECK-NEXT:{{^}}v_add_f64 v[0:1], v[0:1], v[0xF00000001:0x2]
 903 // CHECK-NEXT:{{^}}                            ^
 904
 905 //==============================================================================
 906 // invalid register name
 907
 908 s_mov_b64 s[10:11], [x0,s1]
 909 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid register name
 910 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [x0,s1]
 911 // CHECK-NEXT:{{^}}                     ^
 912
 913 //==============================================================================
 914 // invalid row_share value
 915
 916 v_mov_b32_dpp v5, v1 row_share:16 row_mask:0x0 bank_mask:0x0
 917 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid row_share value
 918 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:16 row_mask:0x0 bank_mask:0x0
 919 // CHECK-NEXT:{{^}}                               ^
 920
 921 v_mov_b32_dpp v5, v1 row_share:-1 row_mask:0x0 bank_mask:0x0
 922 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid row_share value
 923 // CHECK-NEXT:{{^}}v_mov_b32_dpp v5, v1 row_share:-1 row_mask:0x0 bank_mask:0x0
 924 // CHECK-NEXT:{{^}}                               ^
 925
 926 //==============================================================================
 927 // invalid syntax, expected 'neg' modifier
 928
 929 v_ceil_f32 v0, --1
 930 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid syntax, expected 'neg' modifier
 931 // CHECK-NEXT:{{^}}v_ceil_f32 v0, --1
 932 // CHECK-NEXT:{{^}}               ^
 933
 934 //==============================================================================
 935 // lane id must be in the interval [0,group size - 1]
 936
 937 ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)
 938 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lane id must be in the interval [0,group size - 1]
 939 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,2,-1)
 940 // CHECK-NEXT:{{^}}                                                 ^
 941
 942 //==============================================================================
 943 // lds_direct cannot be used with this instruction
 944
 945 v_ashrrev_i16 v0, lds_direct, v0
 946 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction
 947 // CHECK-NEXT:{{^}}v_ashrrev_i16 v0, lds_direct, v0
 948 // CHECK-NEXT:{{^}}                  ^
 949
 950 v_ashrrev_i16 v0, v1, lds_direct
 951 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction
 952 // CHECK-NEXT:{{^}}v_ashrrev_i16 v0, v1, lds_direct
 953 // CHECK-NEXT:{{^}}                      ^
 954
 955 v_mov_b32_sdwa v1, src_lds_direct dst_sel:DWORD
 956 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction
 957 // CHECK-NEXT:{{^}}v_mov_b32_sdwa v1, src_lds_direct dst_sel:DWORD
 958 // CHECK-NEXT:{{^}}                   ^
 959
 960 v_add_f32_sdwa v5, v1, lds_direct dst_sel:DWORD
 961 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct cannot be used with this instruction
 962 // CHECK-NEXT:{{^}}v_add_f32_sdwa v5, v1, lds_direct dst_sel:DWORD
 963 // CHECK-NEXT:{{^}}                       ^
 964
 965 //==============================================================================
 966 // lds_direct may be used as src0 only
 967
 968 v_add_f32 v5, v1, lds_direct
 969 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: lds_direct may be used as src0 only
 970 // CHECK-NEXT:{{^}}v_add_f32 v5, v1, lds_direct
 971 // CHECK-NEXT:{{^}}                  ^
 972
 973 //==============================================================================
 974 // message does not support operations
 975
 976 s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0)
 977 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: message does not support operations
 978 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_ALLOC_REQ, 0)
 979 // CHECK-NEXT:{{^}}                                    ^
 980
 981 //==============================================================================
 982 // message operation does not support streams
 983
 984 s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
 985 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: message operation does not support streams
 986 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP, 0)
 987 // CHECK-NEXT:{{^}}                                          ^
 988
 989 //==============================================================================
 990 // missing message operation
 991
 992 s_sendmsg sendmsg(MSG_SYSMSG)
 993 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing message operation
 994 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(MSG_SYSMSG)
 995 // CHECK-NEXT:{{^}}                  ^
 996
 997 //==============================================================================
 998 // missing register index
 999
1000 s_mov_b64 s[10:11], [s
1001 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing register index
1002 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s
1003 // CHECK-NEXT:{{^}}                      ^
1004
1005 s_mov_b64 s[10:11], [s,s1]
1006 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: missing register index
1007 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s,s1]
1008 // CHECK-NEXT:{{^}}                      ^
1009
1010 //==============================================================================
1011 // not a valid operand.
1012
1013 s_branch offset:1
1014 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
1015 // CHECK-NEXT:{{^}}s_branch offset:1
1016 // CHECK-NEXT:{{^}}         ^
1017
1018 v_mov_b32 v0, v0 row_bcast:0
1019 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
1020 // CHECK-NEXT:{{^}}v_mov_b32 v0, v0 row_bcast:0
1021 // CHECK-NEXT:{{^}}                 ^
1022
1023 //==============================================================================
1024 // only one unique literal operand is allowed
1025
1026 s_and_b32 s2, 0x12345678, 0x12345679
1027 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1028 // CHECK-NEXT:{{^}}s_and_b32 s2, 0x12345678, 0x12345679
1029 // CHECK-NEXT:{{^}}                          ^
1030
1031 v_add_f64 v[0:1], 1.23456, -abs(1.2345)
1032 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1033 // CHECK-NEXT:{{^}}v_add_f64 v[0:1], 1.23456, -abs(1.2345)
1034 // CHECK-NEXT:{{^}}                                ^
1035
1036 v_min3_i16 v5, 0x5678, 0x5678, 0x5679
1037 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1038 // CHECK-NEXT:{{^}}v_min3_i16 v5, 0x5678, 0x5678, 0x5679
1039 // CHECK-NEXT:{{^}}                               ^
1040
1041 v_pk_add_f16 v1, 25.0, 25.1
1042 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1043 // CHECK-NEXT:{{^}}v_pk_add_f16 v1, 25.0, 25.1
1044 // CHECK-NEXT:{{^}}                       ^
1045
1046 v_fma_mix_f32 v5, 0x7c, 0x7b, 1
1047 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1048 // CHECK-NEXT:{{^}}v_fma_mix_f32 v5, 0x7c, 0x7b, 1
1049 // CHECK-NEXT:{{^}}                        ^
1050
1051 v_pk_add_i16 v5, 0x7c, 0x4000
1052 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1053 // CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x7c, 0x4000
1054 // CHECK-NEXT:{{^}}                       ^
1055
1056 v_pk_add_i16 v5, 0x4400, 0x4000
1057 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1058 // CHECK-NEXT:{{^}}v_pk_add_i16 v5, 0x4400, 0x4000
1059 // CHECK-NEXT:{{^}}                         ^
1060
1061 v_bfe_u32 v0, v2, 123, undef
1062 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1063 // CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, 123, undef
1064 // CHECK-NEXT:{{^}}                       ^
1065
1066 v_bfe_u32 v0, v2, undef, 123
1067 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: only one unique literal operand is allowed
1068 // CHECK-NEXT:{{^}}v_bfe_u32 v0, v2, undef, 123
1069 // CHECK-NEXT:{{^}}                         ^
1070
1071 //==============================================================================
1072 // out of bounds interpolation attribute number
1073
1074 v_interp_p1_f32 v0, v1, attr64.w
1075 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: out of bounds interpolation attribute number
1076 // CHECK-NEXT:{{^}}v_interp_p1_f32 v0, v1, attr64.w
1077 // CHECK-NEXT:{{^}}                        ^
1078
1079 //==============================================================================
1080 // out of range format
1081
1082 tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 0
1083 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: out of range format
1084 // CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:-1, 0
1085 // CHECK-NEXT:{{^}}                                           ^
1086
1087 //==============================================================================
1088 // register does not fit in the list
1089
1090 s_mov_b64 s[10:11], [exec,exec_lo]
1091 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register does not fit in the list
1092 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec,exec_lo]
1093 // CHECK-NEXT:{{^}}                          ^
1094
1095 s_mov_b64 s[10:11], [exec_lo,exec]
1096 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register does not fit in the list
1097 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [exec_lo,exec]
1098 // CHECK-NEXT:{{^}}                             ^
1099
1100 //==============================================================================
1101 // register index is out of range
1102
1103 s_add_i32 s106, s0, s1
1104 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
1105 // CHECK-NEXT:{{^}}s_add_i32 s106, s0, s1
1106 // CHECK-NEXT:{{^}}          ^
1107
1108 s_load_dwordx16 s[100:115], s[2:3], s4
1109 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
1110 // CHECK-NEXT:{{^}}s_load_dwordx16 s[100:115], s[2:3], s4
1111 // CHECK-NEXT:{{^}}                ^
1112
1113 s_mov_b32 ttmp16, 0
1114 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
1115 // CHECK-NEXT:{{^}}s_mov_b32 ttmp16, 0
1116 // CHECK-NEXT:{{^}}          ^
1117
1118 v_add_nc_i32 v256, v0, v1
1119 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: register index is out of range
1120 // CHECK-NEXT:{{^}}v_add_nc_i32 v256, v0, v1
1121 // CHECK-NEXT:{{^}}             ^
1122
1123 //==============================================================================
1124 // register not available on this GPU
1125
1126 s_and_b32     ttmp9, tma_hi, 0x0000ffff
1127 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: tma_hi register not available on this GPU
1128 // CHECK-NEXT:{{^}}s_and_b32     ttmp9, tma_hi, 0x0000ffff
1129 // CHECK-NEXT:{{^}}                     ^
1130
1131 s_mov_b32 flat_scratch, -1
1132 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: flat_scratch register not available on this GPU
1133 // CHECK-NEXT:{{^}}s_mov_b32 flat_scratch, -1
1134 // CHECK-NEXT:{{^}}          ^
1135
1136 //==============================================================================
1137 // registers in a list must be of the same kind
1138
1139 s_mov_b64 s[10:11], [a0,v1]
1140 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must be of the same kind
1141 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,v1]
1142 // CHECK-NEXT:{{^}}                        ^
1143
1144 //==============================================================================
1145 // registers in a list must have consecutive indices
1146
1147 s_mov_b64 s[10:11], [a0,a2]
1148 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must have consecutive indices
1149 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [a0,a2]
1150 // CHECK-NEXT:{{^}}                        ^
1151
1152 s_mov_b64 s[10:11], [s0,s0]
1153 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must have consecutive indices
1154 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s0,s0]
1155 // CHECK-NEXT:{{^}}                        ^
1156
1157 s_mov_b64 s[10:11], [s2,s1]
1158 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: registers in a list must have consecutive indices
1159 // CHECK-NEXT:{{^}}s_mov_b64 s[10:11], [s2,s1]
1160 // CHECK-NEXT:{{^}}                        ^
1161
1162 //==============================================================================
1163 // source operand must be a VGPR
1164
1165 v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
1166 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
1167 // CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
1168 // CHECK-NEXT:{{^}}                       ^
1169
1170 v_movrels_b32_sdwa v0, s0
1171 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
1172 // CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, s0
1173 // CHECK-NEXT:{{^}}                       ^
1174
1175 v_movrels_b32_sdwa v0, shared_base
1176 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
1177 // CHECK-NEXT:{{^}}v_movrels_b32_sdwa v0, shared_base
1178 // CHECK-NEXT:{{^}}                       ^
1179
1180 //==============================================================================
1181 // invalid hardware register: not supported on this GPU
1182
1183 s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES)
1184 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU
1185 // CHECK-NEXT:{{^}}s_getreg_b32 s2, hwreg(HW_REG_SHADER_CYCLES)
1186 // CHECK-NEXT:{{^}}                       ^
1187
1188 //==============================================================================
1189 // too few operands for instruction
1190
1191 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]
1192 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
1193 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7]
1194 // CHECK-NEXT:{{^}}^
1195
1196 v_add_f32_e64 v0, v1
1197 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
1198 // CHECK-NEXT:{{^}}v_add_f32_e64 v0, v1
1199 // CHECK-NEXT:{{^}}^
1200
1201 buffer_load_dword off, s[8:11], s3
1202 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
1203 // CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3
1204 // CHECK-NEXT:{{^}}^
1205
1206 buffer_load_dword off, s[8:11], s3 offset:1
1207 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
1208 // CHECK-NEXT:{{^}}buffer_load_dword off, s[8:11], s3 offset:1
1209 // CHECK-NEXT:{{^}}^
1210
1211 //==============================================================================
1212 // too large value for expcnt
1213
1214 s_waitcnt expcnt(8)
1215 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too large value for expcnt
1216 // CHECK-NEXT:{{^}}s_waitcnt expcnt(8)
1217 // CHECK-NEXT:{{^}}                 ^
1218
1219 //==============================================================================
1220 // too large value for lgkmcnt
1221
1222 s_waitcnt lgkmcnt(64)
1223 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too large value for lgkmcnt
1224 // CHECK-NEXT:{{^}}s_waitcnt lgkmcnt(64)
1225 // CHECK-NEXT:{{^}}                  ^
1226
1227 //==============================================================================
1228 // too large value for vmcnt
1229
1230 s_waitcnt vmcnt(64)
1231 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: too large value for vmcnt
1232 // CHECK-NEXT:{{^}}s_waitcnt vmcnt(64)
1233 // CHECK-NEXT:{{^}}                ^
1234
1235 //==============================================================================
1236 // unknown token in expression
1237
1238 ds_swizzle_b32 v8, v2 offset:
1239 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1240 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:
1241 // CHECK-NEXT:{{^}}                             ^
1242
1243 s_sendmsg sendmsg(1 -)
1244 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1245 // CHECK-NEXT:{{^}}s_sendmsg sendmsg(1 -)
1246 // CHECK-NEXT:{{^}}                     ^
1247
1248 tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0
1249 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1250 // CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1,, s0
1251 // CHECK-NEXT:{{^}}                                                    ^
1252
1253 tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0
1254 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1255 // CHECK-NEXT:{{^}}tbuffer_load_format_d16_x v0, off, s[0:3], format:1:, s0
1256 // CHECK-NEXT:{{^}}                                                   ^
1257
1258 v_pk_add_u16 v1, v2, v3 op_sel:[
1259 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1260 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[
1261 // CHECK-NEXT:{{^}}                                ^
1262
1263 v_pk_add_u16 v1, v2, v3 op_sel:[,0]
1264 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1265 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,0]
1266 // CHECK-NEXT:{{^}}                                ^
1267
1268 v_pk_add_u16 v1, v2, v3 op_sel:[,]
1269 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1270 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[,]
1271 // CHECK-NEXT:{{^}}                                ^
1272
1273 v_pk_add_u16 v1, v2, v3 op_sel:[0,]
1274 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1275 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[0,]
1276 // CHECK-NEXT:{{^}}                                  ^
1277
1278 v_pk_add_u16 v1, v2, v3 op_sel:[]
1279 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unknown token in expression
1280 // CHECK-NEXT:{{^}}v_pk_add_u16 v1, v2, v3 op_sel:[]
1281 // CHECK-NEXT:{{^}}                                ^
1282
1283 //==============================================================================
1284 // unsupported format
1285
1286 tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT]
1287 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: unsupported format
1288 // CHECK-NEXT:{{^}}tbuffer_store_format_xyzw v[1:4], off, ttmp[4:7], s0 format:[BUF_DATA_FORMAT]
1289 // CHECK-NEXT:{{^}}                                                             ^
1290
1291 //==============================================================================
1292 // expected vertical bar
1293
1294 v_ceil_f32 v1, |1+1|
1295 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected vertical bar
1296 // CHECK-NEXT:{{^}}v_ceil_f32 v1, |1+1|
1297 // CHECK-NEXT:{{^}}                 ^
1298
1299 //==============================================================================
1300 // expected left paren after neg
1301
1302 v_ceil_f32 v1, neg-(v2)
1303 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected left paren after neg
1304 // CHECK-NEXT:{{^}}v_ceil_f32 v1, neg-(v2)
1305 // CHECK-NEXT:{{^}}                  ^
1306
1307 //==============================================================================
1308 // expected left paren after abs
1309
1310 v_ceil_f32 v1, abs-(v2)
1311 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected left paren after abs
1312 // CHECK-NEXT:{{^}}v_ceil_f32 v1, abs-(v2)
1313 // CHECK-NEXT:{{^}}                  ^
1314
1315 //==============================================================================
1316 // expected left paren after sext
1317
1318 v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD
1319 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected left paren after sext
1320 // CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext[v1], v2 src0_sel:DWORD src1_sel:DWORD
1321 // CHECK-NEXT:{{^}}                      ^
1322
1323 //==============================================================================
1324 // expected closing parentheses
1325
1326 v_ceil_f32 v1, abs(v2]
1327 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected closing parentheses
1328 // CHECK-NEXT:{{^}}v_ceil_f32 v1, abs(v2]
1329 // CHECK-NEXT:{{^}}                     ^
1330
1331 v_ceil_f32 v1, neg(v2]
1332 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected closing parentheses
1333 // CHECK-NEXT:{{^}}v_ceil_f32 v1, neg(v2]
1334 // CHECK-NEXT:{{^}}                     ^
1335
1336 v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD
1337 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected closing parentheses
1338 // CHECK-NEXT:{{^}}v_cmpx_f_i32_sdwa sext(v1], v2 src0_sel:DWORD src1_sel:DWORD
1339 // CHECK-NEXT:{{^}}                         ^
1340
1341 //==============================================================================
1342 // expected a left parentheses
1343
1344 ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3]
1345 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left parentheses
1346 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle[QUAD_PERM, 0, 1, 2, 3]
1347 // CHECK-NEXT:{{^}}                                    ^
1348
1349 //==============================================================================
1350 // expected an absolute expression or a label
1351
1352 s_branch 1+x
1353 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected an absolute expression or a label
1354 // CHECK-NEXT:{{^}}s_branch 1+x
1355 // CHECK-NEXT:{{^}}         ^
1356
1357 //==============================================================================
1358 // expected a 16-bit offset
1359
1360 ds_swizzle_b32 v8, v2 offset:0x10000
1361 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: expected a 16-bit offset
1362 // CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:0x10000
1363 // CHECK-NEXT:{{^}}                             ^
1364
1365 //==============================================================================
1366 // not a valid operand
1367
1368 v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
1369 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand.
1370 // CHECK-NEXT:{{^}}v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 src1_sel:WORD_0
1371 // CHECK-NEXT:{{^}}                           ^
1372
1373 //==============================================================================
1374 // TFE modifier has no meaning for store instructions
1375
1376 buffer_store_dword v[1:2], off, s[12:15], s4 tfe
1377 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: TFE modifier has no meaning for store instructions
1378 // CHECK-NEXT:{{^}}buffer_store_dword v[1:2], off, s[12:15], s4 tfe
1379 // CHECK-NEXT:{{^}}                                             ^