llvm/test/MC/AMDGPU/gfx10_unsupported_e32.s

   1 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck --implicit-check-not=error: %s
   2 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
   3 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1013 -mattr=+wavefrontsize32 %s 2>&1 | FileCheck --implicit-check-not=error: %s
   4
   5 v_add_co_u32_e32 v2, vcc, s0, v2
   6 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
   7
   8 v_ashrrev_i16_e32 v1, v2, v3
   9 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  10
  11 v_lshlrev_b16_e32 v1, v2, v3
  12 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  13
  14 v_lshrrev_b16_e32 v1, v2, v3
  15 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  16
  17 v_max_i16_e32 v1, v2, v3
  18 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  19
  20 v_max_u16_e32 v1, v2, v3
  21 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  22
  23 v_min_i16_e32 v1, v2, v3
  24 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  25
  26 v_min_u16_e32 v1, v2, v3
  27 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  28
  29 v_mul_lo_u16_e32 v1, v2, v3
  30 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  31
  32 v_sub_co_u32_e32 v2, vcc, s0, v2
  33 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  34
  35 v_subrev_co_u32_e32 v2, vcc, s0, v2
  36 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported