llvm/test/MC/AMDGPU/gfx11_asm_vop2_dpp16.s

   1 // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5
   2 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
   3 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
   4 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
   5 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
   6
   7 v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
   8 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
   9 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  10
  11 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
  12 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff]
  13 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  14
  15 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror
  16 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff]
  17 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  18
  19 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror
  20 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff]
  21 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  22
  23 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1
  24 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff]
  25 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  26
  27 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15
  28 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff]
  29 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  30
  31 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1
  32 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff]
  33 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  34
  35 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15
  36 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff]
  37 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  38
  39 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1
  40 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff]
  41 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  42
  43 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15
  44 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff]
  45 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  46
  47 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf
  48 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff]
  49 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  50
  51 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
  52 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01]
  53 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  54
  55 v_add_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
  56 // W32: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x09,0x13]
  57 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  58
  59 v_add_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
  60 // W32: v_add_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x05,0x30]
  61 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  62
  63 v_add_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0]
  64 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0xff]
  65 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  66
  67 v_add_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
  68 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xff]
  69 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  70
  71 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror
  72 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0xff]
  73 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  74
  75 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror
  76 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0xff]
  77 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  78
  79 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1
  80 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0xff]
  81 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  82
  83 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15
  84 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0xff]
  85 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  86
  87 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1
  88 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0xff]
  89 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  90
  91 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15
  92 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0xff]
  93 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  94
  95 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1
  96 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0xff]
  97 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
  98
  99 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15
 100 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0xff]
 101 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 102
 103 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf
 104 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x50,0x01,0xff]
 105 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 106
 107 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
 108 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x5f,0x01,0x01]
 109 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 110
 111 v_add_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 112 // W64: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x40,0x01,0x60,0x09,0x13]
 113 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 114
 115 v_add_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 116 // W64: v_add_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x41,0xff,0x6f,0x05,0x30]
 117 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 118
 119 v_add_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
 120 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0xff]
 121
 122 v_add_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
 123 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xff]
 124
 125 v_add_f16 v5.l, v1.l, v2.l row_mirror
 126 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0xff]
 127
 128 v_add_f16 v5.l, v1.l, v2.l row_half_mirror
 129 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0xff]
 130
 131 v_add_f16 v5.l, v1.l, v2.l row_shl:1
 132 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0xff]
 133
 134 v_add_f16 v5.l, v1.l, v2.l row_shl:15
 135 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0xff]
 136
 137 v_add_f16 v5.l, v1.l, v2.l row_shr:1
 138 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0xff]
 139
 140 v_add_f16 v5.l, v1.l, v2.l row_shr:15
 141 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0xff]
 142
 143 v_add_f16 v5.l, v1.l, v2.l row_ror:1
 144 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0xff]
 145
 146 v_add_f16 v5.l, v1.l, v2.l row_ror:15
 147 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0xff]
 148
 149 v_add_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
 150 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x50,0x01,0xff]
 151
 152 v_add_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
 153 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x01]
 154
 155 v_add_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
 156 // GFX11: v_add_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0x60,0x09,0x13]
 157
 158 v_add_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
 159 // GFX11: v_add_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x6f,0xf5,0x30]
 160
 161 v_add_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
 162 // GFX11: v_add_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x64,0x7f,0x5f,0x01,0x01]
 163
 164 v_add_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 165 // GFX11: v_add_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x65,0x81,0x60,0x09,0x13]
 166
 167 v_add_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 168 // GFX11: v_add_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x65,0xff,0x6f,0xf5,0x30]
 169
 170 v_add_f32 v5, v1, v2 quad_perm:[3,2,1,0]
 171 // GFX11: v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0xff]
 172
 173 v_add_f32 v5, v1, v2 quad_perm:[0,1,2,3]
 174 // GFX11: v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xff]
 175
 176 v_add_f32 v5, v1, v2 row_mirror
 177 // GFX11: v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0xff]
 178
 179 v_add_f32 v5, v1, v2 row_half_mirror
 180 // GFX11: v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0xff]
 181
 182 v_add_f32 v5, v1, v2 row_shl:1
 183 // GFX11: v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0xff]
 184
 185 v_add_f32 v5, v1, v2 row_shl:15
 186 // GFX11: v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0xff]
 187
 188 v_add_f32 v5, v1, v2 row_shr:1
 189 // GFX11: v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0xff]
 190
 191 v_add_f32 v5, v1, v2 row_shr:15
 192 // GFX11: v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0xff]
 193
 194 v_add_f32 v5, v1, v2 row_ror:1
 195 // GFX11: v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0xff]
 196
 197 v_add_f32 v5, v1, v2 row_ror:15
 198 // GFX11: v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0xff]
 199
 200 v_add_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 201 // GFX11: v_add_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x50,0x01,0xff]
 202
 203 v_add_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 204 // GFX11: v_add_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x01]
 205
 206 v_add_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 207 // GFX11: v_add_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x06,0x01,0x60,0x09,0x13]
 208
 209 v_add_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 210 // GFX11: v_add_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x07,0xff,0x6f,0xf5,0x30]
 211
 212 v_add_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0]
 213 // GFX11: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x00,0xff]
 214
 215 v_add_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3]
 216 // GFX11: v_add_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0xff]
 217
 218 v_add_nc_u32 v5, v1, v2 row_mirror
 219 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x40,0x01,0xff]
 220
 221 v_add_nc_u32 v5, v1, v2 row_half_mirror
 222 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x41,0x01,0xff]
 223
 224 v_add_nc_u32 v5, v1, v2 row_shl:1
 225 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x01,0x01,0xff]
 226
 227 v_add_nc_u32 v5, v1, v2 row_shl:15
 228 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x0f,0x01,0xff]
 229
 230 v_add_nc_u32 v5, v1, v2 row_shr:1
 231 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x11,0x01,0xff]
 232
 233 v_add_nc_u32 v5, v1, v2 row_shr:15
 234 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x1f,0x01,0xff]
 235
 236 v_add_nc_u32 v5, v1, v2 row_ror:1
 237 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x21,0x01,0xff]
 238
 239 v_add_nc_u32 v5, v1, v2 row_ror:15
 240 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x2f,0x01,0xff]
 241
 242 v_add_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 243 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x50,0x01,0xff]
 244
 245 v_add_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 246 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x5f,0x01,0x01]
 247
 248 v_add_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 249 // GFX11: v_add_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x4a,0x01,0x60,0x09,0x13]
 250
 251 v_add_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 252 // GFX11: v_add_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4b,0xff,0x6f,0x05,0x30]
 253
 254 v_and_b32 v5, v1, v2 quad_perm:[3,2,1,0]
 255 // GFX11: v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0xff]
 256
 257 v_and_b32 v5, v1, v2 quad_perm:[0,1,2,3]
 258 // GFX11: v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xff]
 259
 260 v_and_b32 v5, v1, v2 row_mirror
 261 // GFX11: v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0xff]
 262
 263 v_and_b32 v5, v1, v2 row_half_mirror
 264 // GFX11: v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0xff]
 265
 266 v_and_b32 v5, v1, v2 row_shl:1
 267 // GFX11: v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0xff]
 268
 269 v_and_b32 v5, v1, v2 row_shl:15
 270 // GFX11: v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0xff]
 271
 272 v_and_b32 v5, v1, v2 row_shr:1
 273 // GFX11: v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0xff]
 274
 275 v_and_b32 v5, v1, v2 row_shr:15
 276 // GFX11: v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0xff]
 277
 278 v_and_b32 v5, v1, v2 row_ror:1
 279 // GFX11: v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0xff]
 280
 281 v_and_b32 v5, v1, v2 row_ror:15
 282 // GFX11: v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0xff]
 283
 284 v_and_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 285 // GFX11: v_and_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x50,0x01,0xff]
 286
 287 v_and_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 288 // GFX11: v_and_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x01]
 289
 290 v_and_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 291 // GFX11: v_and_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x36,0x01,0x60,0x09,0x13]
 292
 293 v_and_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 294 // GFX11: v_and_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x37,0xff,0x6f,0x05,0x30]
 295
 296 v_ashrrev_i32 v5, v1, v2 quad_perm:[3,2,1,0]
 297 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0xff]
 298
 299 v_ashrrev_i32 v5, v1, v2 quad_perm:[0,1,2,3]
 300 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xff]
 301
 302 v_ashrrev_i32 v5, v1, v2 row_mirror
 303 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0xff]
 304
 305 v_ashrrev_i32 v5, v1, v2 row_half_mirror
 306 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0xff]
 307
 308 v_ashrrev_i32 v5, v1, v2 row_shl:1
 309 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0xff]
 310
 311 v_ashrrev_i32 v5, v1, v2 row_shl:15
 312 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0xff]
 313
 314 v_ashrrev_i32 v5, v1, v2 row_shr:1
 315 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0xff]
 316
 317 v_ashrrev_i32 v5, v1, v2 row_shr:15
 318 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0xff]
 319
 320 v_ashrrev_i32 v5, v1, v2 row_ror:1
 321 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0xff]
 322
 323 v_ashrrev_i32 v5, v1, v2 row_ror:15
 324 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0xff]
 325
 326 v_ashrrev_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 327 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x50,0x01,0xff]
 328
 329 v_ashrrev_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 330 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x01]
 331
 332 v_ashrrev_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 333 // GFX11: v_ashrrev_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0x60,0x09,0x13]
 334
 335 v_ashrrev_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 336 // GFX11: v_ashrrev_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x35,0xff,0x6f,0x05,0x30]
 337
 338 v_cndmask_b32 v5, v1, v2, vcc_lo quad_perm:[3,2,1,0]
 339 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff]
 340 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 341
 342 v_cndmask_b32 v5, v1, v2, vcc_lo quad_perm:[0,1,2,3]
 343 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff]
 344 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 345
 346 v_cndmask_b32 v5, v1, v2, vcc_lo row_mirror
 347 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff]
 348 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 349
 350 v_cndmask_b32 v5, v1, v2, vcc_lo row_half_mirror
 351 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff]
 352 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 353
 354 v_cndmask_b32 v5, v1, v2, vcc_lo row_shl:1
 355 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff]
 356 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 357
 358 v_cndmask_b32 v5, v1, v2, vcc_lo row_shl:15
 359 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff]
 360 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 361
 362 v_cndmask_b32 v5, v1, v2, vcc_lo row_shr:1
 363 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff]
 364 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 365
 366 v_cndmask_b32 v5, v1, v2, vcc_lo row_shr:15
 367 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff]
 368 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 369
 370 v_cndmask_b32 v5, v1, v2, vcc_lo row_ror:1
 371 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff]
 372 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 373
 374 v_cndmask_b32 v5, v1, v2, vcc_lo row_ror:15
 375 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff]
 376 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 377
 378 v_cndmask_b32 v5, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf
 379 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff]
 380 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 381
 382 v_cndmask_b32 v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
 383 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01]
 384 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 385
 386 v_cndmask_b32 v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 387 // W32: v_cndmask_b32_dpp v5, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13]
 388 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 389
 390 v_cndmask_b32 v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 391 // W32: v_cndmask_b32_dpp v5, -v1, |v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0x00]
 392 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 393
 394 v_cndmask_b32 v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 395 // W32: v_cndmask_b32_dpp v5, |v1|, -v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0x00]
 396 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 397
 398 v_cndmask_b32 v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 399 // W32: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0x00]
 400 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 401
 402 v_cndmask_b32 v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 403 // W32: v_cndmask_b32_dpp v255, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x05,0x30]
 404 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 405
 406 v_cndmask_b32 v5, v1, v2, vcc quad_perm:[3,2,1,0]
 407 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0xff]
 408 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 409
 410 v_cndmask_b32 v5, v1, v2, vcc quad_perm:[0,1,2,3]
 411 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xff]
 412 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 413
 414 v_cndmask_b32 v5, v1, v2, vcc row_mirror
 415 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0xff]
 416 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 417
 418 v_cndmask_b32 v5, v1, v2, vcc row_half_mirror
 419 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0xff]
 420 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 421
 422 v_cndmask_b32 v5, v1, v2, vcc row_shl:1
 423 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0xff]
 424 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 425
 426 v_cndmask_b32 v5, v1, v2, vcc row_shl:15
 427 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0xff]
 428 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 429
 430 v_cndmask_b32 v5, v1, v2, vcc row_shr:1
 431 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0xff]
 432 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 433
 434 v_cndmask_b32 v5, v1, v2, vcc row_shr:15
 435 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0xff]
 436 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 437
 438 v_cndmask_b32 v5, v1, v2, vcc row_ror:1
 439 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0xff]
 440 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 441
 442 v_cndmask_b32 v5, v1, v2, vcc row_ror:15
 443 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0xff]
 444 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 445
 446 v_cndmask_b32 v5, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf
 447 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x50,0x01,0xff]
 448 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 449
 450 v_cndmask_b32 v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
 451 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x5f,0x01,0x01]
 452 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 453
 454 v_cndmask_b32 v5, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 455 // W64: v_cndmask_b32_dpp v5, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0x60,0x09,0x13]
 456 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 457
 458 v_cndmask_b32 v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 459 // W64: v_cndmask_b32_dpp v255, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x03,0xff,0x6f,0x05,0x30]
 460 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 461
 462 v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 463 // W64: v_cndmask_b32_dpp v5, -v1, |v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x90,0x00]
 464 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 465
 466 v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 467 // W64: v_cndmask_b32_dpp v5, |v1|, -v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x60,0x00]
 468 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 469
 470 v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 471 // W64: v_cndmask_b32_dpp v5, -|v1|, -|v2|, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0xf0,0x00]
 472 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 473
 474 v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[3,2,1,0]
 475 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff]
 476
 477 v_cvt_pk_rtz_f16_f32 v5, v1, v2 quad_perm:[0,1,2,3]
 478 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff]
 479
 480 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_mirror
 481 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff]
 482
 483 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_half_mirror
 484 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff]
 485
 486 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shl:1
 487 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff]
 488
 489 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shl:15
 490 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff]
 491
 492 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shr:1
 493 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff]
 494
 495 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_shr:15
 496 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff]
 497
 498 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_ror:1
 499 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff]
 500
 501 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_ror:15
 502 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff]
 503
 504 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 505 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff]
 506
 507 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 508 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01]
 509
 510 v_cvt_pk_rtz_f16_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 511 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x09,0x13]
 512
 513 v_cvt_pk_rtz_f16_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 514 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xf5,0x30]
 515
 516 v_cvt_pkrtz_f16_f32 v5, v1, v2 quad_perm:[3,2,1,0]
 517 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0xff]
 518
 519 v_cvt_pkrtz_f16_f32 v5, v1, v2 quad_perm:[0,1,2,3]
 520 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xff]
 521
 522 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_mirror
 523 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0xff]
 524
 525 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_half_mirror
 526 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0xff]
 527
 528 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shl:1
 529 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0xff]
 530
 531 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shl:15
 532 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0xff]
 533
 534 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shr:1
 535 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0xff]
 536
 537 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_shr:15
 538 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0xff]
 539
 540 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_ror:1
 541 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0xff]
 542
 543 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_ror:15
 544 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0xff]
 545
 546 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 547 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x50,0x01,0xff]
 548
 549 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 550 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x5f,0x01,0x01]
 551
 552 v_cvt_pkrtz_f16_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 553 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x5e,0x01,0x60,0x09,0x13]
 554
 555 v_cvt_pkrtz_f16_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 556 // GFX11: v_cvt_pk_rtz_f16_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x5f,0xff,0x6f,0xf5,0x30]
 557
 558 v_dot2acc_f32_f16 v5, v1, v2 quad_perm:[3,2,1,0]
 559 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0xff]
 560
 561 v_dot2acc_f32_f16 v5, v1, v2 quad_perm:[0,1,2,3]
 562 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xff]
 563
 564 v_dot2acc_f32_f16 v5, v1, v2 row_mirror
 565 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0xff]
 566
 567 v_dot2acc_f32_f16 v5, v1, v2 row_half_mirror
 568 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0xff]
 569
 570 v_dot2acc_f32_f16 v5, v1, v2 row_shl:1
 571 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0xff]
 572
 573 v_dot2acc_f32_f16 v5, v1, v2 row_shl:15
 574 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0xff]
 575
 576 v_dot2acc_f32_f16 v5, v1, v2 row_shr:1
 577 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0xff]
 578
 579 v_dot2acc_f32_f16 v5, v1, v2 row_shr:15
 580 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0xff]
 581
 582 v_dot2acc_f32_f16 v5, v1, v2 row_ror:1
 583 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0xff]
 584
 585 v_dot2acc_f32_f16 v5, v1, v2 row_ror:15
 586 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0xff]
 587
 588 v_dot2acc_f32_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 589 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x50,0x01,0xff]
 590
 591 v_dot2acc_f32_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 592 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x5f,0x01,0x01]
 593
 594 v_dot2acc_f32_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 595 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x60,0x09,0x13]
 596
 597 v_dot2acc_f32_f16 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 598 // GFX11: v_dot2acc_f32_f16_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x05,0xff,0x6f,0xf5,0x30]
 599
 600 v_dot2c_f32_f16 v5, v1, v2 quad_perm:[3,2,1,0]
 601 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0xff]
 602
 603 v_dot2c_f32_f16 v5, v1, v2 quad_perm:[0,1,2,3]
 604 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xff]
 605
 606 v_dot2c_f32_f16 v5, v1, v2 row_mirror
 607 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0xff]
 608
 609 v_dot2c_f32_f16 v5, v1, v2 row_half_mirror
 610 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0xff]
 611
 612 v_dot2c_f32_f16 v5, v1, v2 row_shl:1
 613 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0xff]
 614
 615 v_dot2c_f32_f16 v5, v1, v2 row_shl:15
 616 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0xff]
 617
 618 v_dot2c_f32_f16 v5, v1, v2 row_shr:1
 619 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0xff]
 620
 621 v_dot2c_f32_f16 v5, v1, v2 row_shr:15
 622 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0xff]
 623
 624 v_dot2c_f32_f16 v5, v1, v2 row_ror:1
 625 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0xff]
 626
 627 v_dot2c_f32_f16 v5, v1, v2 row_ror:15
 628 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0xff]
 629
 630 v_dot2c_f32_f16 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 631 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x50,0x01,0xff]
 632
 633 v_dot2c_f32_f16 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 634 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x5f,0x01,0x01]
 635
 636 v_dot2c_f32_f16 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 637 // GFX11: v_dot2acc_f32_f16_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x04,0x01,0x60,0x09,0x13]
 638
 639 v_dot2c_f32_f16 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 640 // GFX11: v_dot2acc_f32_f16_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x05,0xff,0x6f,0xf5,0x30]
 641
 642 v_fmac_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
 643 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0xff]
 644
 645 v_fmac_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
 646 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xff]
 647
 648 v_fmac_f16 v5.l, v1.l, v2.l row_mirror
 649 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0xff]
 650
 651 v_fmac_f16 v5.l, v1.l, v2.l row_half_mirror
 652 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0xff]
 653
 654 v_fmac_f16 v5.l, v1.l, v2.l row_shl:1
 655 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0xff]
 656
 657 v_fmac_f16 v5.l, v1.l, v2.l row_shl:15
 658 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0xff]
 659
 660 v_fmac_f16 v5.l, v1.l, v2.l row_shr:1
 661 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0xff]
 662
 663 v_fmac_f16 v5.l, v1.l, v2.l row_shr:15
 664 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0xff]
 665
 666 v_fmac_f16 v5.l, v1.l, v2.l row_ror:1
 667 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0xff]
 668
 669 v_fmac_f16 v5.l, v1.l, v2.l row_ror:15
 670 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0xff]
 671
 672 v_fmac_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
 673 // GFX11: v_fmac_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6c,0x01,0x50,0x01,0xff]
 674
 675 v_fmac_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
 676 // GFX11: v_fmac_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x6c,0x7f,0x5f,0x01,0x01]
 677
 678 v_fmac_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 679 // GFX11: v_fmac_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x6d,0x81,0x60,0x09,0x13]
 680
 681 v_fmac_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 682 // GFX11: v_fmac_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6d,0xff,0x6f,0xf5,0x30]
 683
 684 v_fmac_f32 v5, v1, v2 quad_perm:[3,2,1,0]
 685 // GFX11: v_fmac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0xff]
 686
 687 v_fmac_f32 v5, v1, v2 quad_perm:[0,1,2,3]
 688 // GFX11: v_fmac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xff]
 689
 690 v_fmac_f32 v5, v1, v2 row_mirror
 691 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0xff]
 692
 693 v_fmac_f32 v5, v1, v2 row_half_mirror
 694 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0xff]
 695
 696 v_fmac_f32 v5, v1, v2 row_shl:1
 697 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0xff]
 698
 699 v_fmac_f32 v5, v1, v2 row_shl:15
 700 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0xff]
 701
 702 v_fmac_f32 v5, v1, v2 row_shr:1
 703 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0xff]
 704
 705 v_fmac_f32 v5, v1, v2 row_shr:15
 706 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0xff]
 707
 708 v_fmac_f32 v5, v1, v2 row_ror:1
 709 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0xff]
 710
 711 v_fmac_f32 v5, v1, v2 row_ror:15
 712 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0xff]
 713
 714 v_fmac_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 715 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x50,0x01,0xff]
 716
 717 v_fmac_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 718 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x5f,0x01,0x01]
 719
 720 v_fmac_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 721 // GFX11: v_fmac_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x56,0x01,0x60,0x09,0x13]
 722
 723 v_fmac_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 724 // GFX11: v_fmac_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x57,0xff,0x6f,0xf5,0x30]
 725
 726 v_ldexp_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
 727 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0xff]
 728
 729 v_ldexp_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
 730 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xff]
 731
 732 v_ldexp_f16 v5.l, v1.l, v2.l row_mirror
 733 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0xff]
 734
 735 v_ldexp_f16 v5.l, v1.l, v2.l row_half_mirror
 736 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0xff]
 737
 738 v_ldexp_f16 v5.l, v1.l, v2.l row_shl:1
 739 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0xff]
 740
 741 v_ldexp_f16 v5.l, v1.l, v2.l row_shl:15
 742 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0xff]
 743
 744 v_ldexp_f16 v5.l, v1.l, v2.l row_shr:1
 745 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0xff]
 746
 747 v_ldexp_f16 v5.l, v1.l, v2.l row_shr:15
 748 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0xff]
 749
 750 v_ldexp_f16 v5.l, v1.l, v2.l row_ror:1
 751 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0xff]
 752
 753 v_ldexp_f16 v5.l, v1.l, v2.l row_ror:15
 754 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0xff]
 755
 756 v_ldexp_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
 757 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x50,0x01,0xff]
 758
 759 v_ldexp_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
 760 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x01]
 761
 762 v_ldexp_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
 763 // GFX11: v_ldexp_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x76,0x01,0x60,0x09,0x13]
 764
 765 v_ldexp_f16 v127.l, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
 766 // GFX11: v_ldexp_f16_dpp v127.l, -|v127.l|, v127.l row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x6f,0x35,0x30]
 767
 768 v_ldexp_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
 769 // GFX11: v_ldexp_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x76,0x7f,0x5f,0x01,0x01]
 770
 771 v_ldexp_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 772 // GFX11: v_ldexp_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x77,0x81,0x60,0x09,0x13]
 773
 774 v_ldexp_f16 v127.h, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 775 // GFX11: v_ldexp_f16_dpp v127.h, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x77,0xff,0x6f,0x35,0x30]
 776
 777 v_lshlrev_b32 v5, v1, v2 quad_perm:[3,2,1,0]
 778 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0xff]
 779
 780 v_lshlrev_b32 v5, v1, v2 quad_perm:[0,1,2,3]
 781 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xff]
 782
 783 v_lshlrev_b32 v5, v1, v2 row_mirror
 784 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0xff]
 785
 786 v_lshlrev_b32 v5, v1, v2 row_half_mirror
 787 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0xff]
 788
 789 v_lshlrev_b32 v5, v1, v2 row_shl:1
 790 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0xff]
 791
 792 v_lshlrev_b32 v5, v1, v2 row_shl:15
 793 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0xff]
 794
 795 v_lshlrev_b32 v5, v1, v2 row_shr:1
 796 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0xff]
 797
 798 v_lshlrev_b32 v5, v1, v2 row_shr:15
 799 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0xff]
 800
 801 v_lshlrev_b32 v5, v1, v2 row_ror:1
 802 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0xff]
 803
 804 v_lshlrev_b32 v5, v1, v2 row_ror:15
 805 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0xff]
 806
 807 v_lshlrev_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 808 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x50,0x01,0xff]
 809
 810 v_lshlrev_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 811 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x01]
 812
 813 v_lshlrev_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 814 // GFX11: v_lshlrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0x60,0x09,0x13]
 815
 816 v_lshlrev_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 817 // GFX11: v_lshlrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x31,0xff,0x6f,0x05,0x30]
 818
 819 v_lshrrev_b32 v5, v1, v2 quad_perm:[3,2,1,0]
 820 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0xff]
 821
 822 v_lshrrev_b32 v5, v1, v2 quad_perm:[0,1,2,3]
 823 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xff]
 824
 825 v_lshrrev_b32 v5, v1, v2 row_mirror
 826 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0xff]
 827
 828 v_lshrrev_b32 v5, v1, v2 row_half_mirror
 829 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0xff]
 830
 831 v_lshrrev_b32 v5, v1, v2 row_shl:1
 832 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0xff]
 833
 834 v_lshrrev_b32 v5, v1, v2 row_shl:15
 835 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0xff]
 836
 837 v_lshrrev_b32 v5, v1, v2 row_shr:1
 838 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0xff]
 839
 840 v_lshrrev_b32 v5, v1, v2 row_shr:15
 841 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0xff]
 842
 843 v_lshrrev_b32 v5, v1, v2 row_ror:1
 844 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0xff]
 845
 846 v_lshrrev_b32 v5, v1, v2 row_ror:15
 847 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0xff]
 848
 849 v_lshrrev_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 850 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x50,0x01,0xff]
 851
 852 v_lshrrev_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 853 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x5f,0x01,0x01]
 854
 855 v_lshrrev_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 856 // GFX11: v_lshrrev_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x32,0x01,0x60,0x09,0x13]
 857
 858 v_lshrrev_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 859 // GFX11: v_lshrrev_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x33,0xff,0x6f,0x05,0x30]
 860
 861 v_max_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
 862 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0xff]
 863
 864 v_max_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
 865 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0xff]
 866
 867 v_max_f16 v5.l, v1.l, v2.l row_mirror
 868 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x40,0x01,0xff]
 869
 870 v_max_f16 v5.l, v1.l, v2.l row_half_mirror
 871 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x41,0x01,0xff]
 872
 873 v_max_f16 v5.l, v1.l, v2.l row_shl:1
 874 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x01,0x01,0xff]
 875
 876 v_max_f16 v5.l, v1.l, v2.l row_shl:15
 877 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x0f,0x01,0xff]
 878
 879 v_max_f16 v5.l, v1.l, v2.l row_shr:1
 880 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x11,0x01,0xff]
 881
 882 v_max_f16 v5.l, v1.l, v2.l row_shr:15
 883 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1f,0x01,0xff]
 884
 885 v_max_f16 v5.l, v1.l, v2.l row_ror:1
 886 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x21,0x01,0xff]
 887
 888 v_max_f16 v5.l, v1.l, v2.l row_ror:15
 889 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x2f,0x01,0xff]
 890
 891 v_max_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
 892 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x50,0x01,0xff]
 893
 894 v_max_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
 895 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x5f,0x01,0x01]
 896
 897 v_max_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
 898 // GFX11: v_max_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x72,0x01,0x60,0x09,0x13]
 899
 900 v_max_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
 901 // GFX11: v_max_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x72,0x7f,0x6f,0xf5,0x30]
 902
 903 v_max_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
 904 // GFX11: v_max_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x72,0x7f,0x5f,0x01,0x01]
 905
 906 v_max_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 907 // GFX11: v_max_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x73,0x81,0x60,0x09,0x13]
 908
 909 v_max_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 910 // GFX11: v_max_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x73,0xff,0x6f,0xf5,0x30]
 911
 912 v_max_f32 v5, v1, v2 quad_perm:[3,2,1,0]
 913 // GFX11: v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0xff]
 914
 915 v_max_f32 v5, v1, v2 quad_perm:[0,1,2,3]
 916 // GFX11: v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xff]
 917
 918 v_max_f32 v5, v1, v2 row_mirror
 919 // GFX11: v_max_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0xff]
 920
 921 v_max_f32 v5, v1, v2 row_half_mirror
 922 // GFX11: v_max_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0xff]
 923
 924 v_max_f32 v5, v1, v2 row_shl:1
 925 // GFX11: v_max_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0xff]
 926
 927 v_max_f32 v5, v1, v2 row_shl:15
 928 // GFX11: v_max_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0xff]
 929
 930 v_max_f32 v5, v1, v2 row_shr:1
 931 // GFX11: v_max_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0xff]
 932
 933 v_max_f32 v5, v1, v2 row_shr:15
 934 // GFX11: v_max_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0xff]
 935
 936 v_max_f32 v5, v1, v2 row_ror:1
 937 // GFX11: v_max_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0xff]
 938
 939 v_max_f32 v5, v1, v2 row_ror:15
 940 // GFX11: v_max_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0xff]
 941
 942 v_max_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 943 // GFX11: v_max_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x50,0x01,0xff]
 944
 945 v_max_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 946 // GFX11: v_max_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x5f,0x01,0x01]
 947
 948 v_max_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 949 // GFX11: v_max_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x20,0x01,0x60,0x09,0x13]
 950
 951 v_max_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 952 // GFX11: v_max_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x21,0xff,0x6f,0xf5,0x30]
 953
 954 v_max_i32 v5, v1, v2 quad_perm:[3,2,1,0]
 955 // GFX11: v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0xff]
 956
 957 v_max_i32 v5, v1, v2 quad_perm:[0,1,2,3]
 958 // GFX11: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xff]
 959
 960 v_max_i32 v5, v1, v2 row_mirror
 961 // GFX11: v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0xff]
 962
 963 v_max_i32 v5, v1, v2 row_half_mirror
 964 // GFX11: v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0xff]
 965
 966 v_max_i32 v5, v1, v2 row_shl:1
 967 // GFX11: v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0xff]
 968
 969 v_max_i32 v5, v1, v2 row_shl:15
 970 // GFX11: v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0xff]
 971
 972 v_max_i32 v5, v1, v2 row_shr:1
 973 // GFX11: v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0xff]
 974
 975 v_max_i32 v5, v1, v2 row_shr:15
 976 // GFX11: v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0xff]
 977
 978 v_max_i32 v5, v1, v2 row_ror:1
 979 // GFX11: v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0xff]
 980
 981 v_max_i32 v5, v1, v2 row_ror:15
 982 // GFX11: v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0xff]
 983
 984 v_max_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
 985 // GFX11: v_max_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x50,0x01,0xff]
 986
 987 v_max_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
 988 // GFX11: v_max_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x01]
 989
 990 v_max_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 991 // GFX11: v_max_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0x60,0x09,0x13]
 992
 993 v_max_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 994 // GFX11: v_max_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x25,0xff,0x6f,0x05,0x30]
 995
 996 v_max_u32 v5, v1, v2 quad_perm:[3,2,1,0]
 997 // GFX11: v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0xff]
 998
 999 v_max_u32 v5, v1, v2 quad_perm:[0,1,2,3]
1000 // GFX11: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xff]
1001
1002 v_max_u32 v5, v1, v2 row_mirror
1003 // GFX11: v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0xff]
1004
1005 v_max_u32 v5, v1, v2 row_half_mirror
1006 // GFX11: v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0xff]
1007
1008 v_max_u32 v5, v1, v2 row_shl:1
1009 // GFX11: v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0xff]
1010
1011 v_max_u32 v5, v1, v2 row_shl:15
1012 // GFX11: v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0xff]
1013
1014 v_max_u32 v5, v1, v2 row_shr:1
1015 // GFX11: v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0xff]
1016
1017 v_max_u32 v5, v1, v2 row_shr:15
1018 // GFX11: v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0xff]
1019
1020 v_max_u32 v5, v1, v2 row_ror:1
1021 // GFX11: v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0xff]
1022
1023 v_max_u32 v5, v1, v2 row_ror:15
1024 // GFX11: v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0xff]
1025
1026 v_max_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1027 // GFX11: v_max_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x50,0x01,0xff]
1028
1029 v_max_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1030 // GFX11: v_max_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x01]
1031
1032 v_max_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1033 // GFX11: v_max_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0x60,0x09,0x13]
1034
1035 v_max_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1036 // GFX11: v_max_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x29,0xff,0x6f,0x05,0x30]
1037
1038 v_min_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
1039 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0xff]
1040
1041 v_min_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
1042 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0xff]
1043
1044 v_min_f16 v5.l, v1.l, v2.l row_mirror
1045 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x40,0x01,0xff]
1046
1047 v_min_f16 v5.l, v1.l, v2.l row_half_mirror
1048 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x41,0x01,0xff]
1049
1050 v_min_f16 v5.l, v1.l, v2.l row_shl:1
1051 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x01,0x01,0xff]
1052
1053 v_min_f16 v5.l, v1.l, v2.l row_shl:15
1054 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x0f,0x01,0xff]
1055
1056 v_min_f16 v5.l, v1.l, v2.l row_shr:1
1057 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x11,0x01,0xff]
1058
1059 v_min_f16 v5.l, v1.l, v2.l row_shr:15
1060 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1f,0x01,0xff]
1061
1062 v_min_f16 v5.l, v1.l, v2.l row_ror:1
1063 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x21,0x01,0xff]
1064
1065 v_min_f16 v5.l, v1.l, v2.l row_ror:15
1066 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x2f,0x01,0xff]
1067
1068 v_min_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
1069 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x50,0x01,0xff]
1070
1071 v_min_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
1072 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x5f,0x01,0x01]
1073
1074 v_min_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
1075 // GFX11: v_min_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x74,0x01,0x60,0x09,0x13]
1076
1077 v_min_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
1078 // GFX11: v_min_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x74,0x7f,0x6f,0xf5,0x30]
1079
1080 v_min_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
1081 // GFX11: v_min_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x74,0x7f,0x5f,0x01,0x01]
1082
1083 v_min_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1084 // GFX11: v_min_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x75,0x81,0x60,0x09,0x13]
1085
1086 v_min_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1087 // GFX11: v_min_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x75,0xff,0x6f,0xf5,0x30]
1088
1089 v_min_f32 v5, v1, v2 quad_perm:[3,2,1,0]
1090 // GFX11: v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0xff]
1091
1092 v_min_f32 v5, v1, v2 quad_perm:[0,1,2,3]
1093 // GFX11: v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xff]
1094
1095 v_min_f32 v5, v1, v2 row_mirror
1096 // GFX11: v_min_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0xff]
1097
1098 v_min_f32 v5, v1, v2 row_half_mirror
1099 // GFX11: v_min_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0xff]
1100
1101 v_min_f32 v5, v1, v2 row_shl:1
1102 // GFX11: v_min_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0xff]
1103
1104 v_min_f32 v5, v1, v2 row_shl:15
1105 // GFX11: v_min_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0xff]
1106
1107 v_min_f32 v5, v1, v2 row_shr:1
1108 // GFX11: v_min_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0xff]
1109
1110 v_min_f32 v5, v1, v2 row_shr:15
1111 // GFX11: v_min_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0xff]
1112
1113 v_min_f32 v5, v1, v2 row_ror:1
1114 // GFX11: v_min_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0xff]
1115
1116 v_min_f32 v5, v1, v2 row_ror:15
1117 // GFX11: v_min_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0xff]
1118
1119 v_min_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1120 // GFX11: v_min_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x50,0x01,0xff]
1121
1122 v_min_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1123 // GFX11: v_min_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x5f,0x01,0x01]
1124
1125 v_min_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1126 // GFX11: v_min_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x60,0x09,0x13]
1127
1128 v_min_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1129 // GFX11: v_min_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x1f,0xff,0x6f,0xf5,0x30]
1130
1131 v_min_i32 v5, v1, v2 quad_perm:[3,2,1,0]
1132 // GFX11: v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0xff]
1133
1134 v_min_i32 v5, v1, v2 quad_perm:[0,1,2,3]
1135 // GFX11: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xff]
1136
1137 v_min_i32 v5, v1, v2 row_mirror
1138 // GFX11: v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0xff]
1139
1140 v_min_i32 v5, v1, v2 row_half_mirror
1141 // GFX11: v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0xff]
1142
1143 v_min_i32 v5, v1, v2 row_shl:1
1144 // GFX11: v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0xff]
1145
1146 v_min_i32 v5, v1, v2 row_shl:15
1147 // GFX11: v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0xff]
1148
1149 v_min_i32 v5, v1, v2 row_shr:1
1150 // GFX11: v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0xff]
1151
1152 v_min_i32 v5, v1, v2 row_shr:15
1153 // GFX11: v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0xff]
1154
1155 v_min_i32 v5, v1, v2 row_ror:1
1156 // GFX11: v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0xff]
1157
1158 v_min_i32 v5, v1, v2 row_ror:15
1159 // GFX11: v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0xff]
1160
1161 v_min_i32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1162 // GFX11: v_min_i32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x50,0x01,0xff]
1163
1164 v_min_i32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1165 // GFX11: v_min_i32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x01]
1166
1167 v_min_i32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1168 // GFX11: v_min_i32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0x60,0x09,0x13]
1169
1170 v_min_i32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1171 // GFX11: v_min_i32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x23,0xff,0x6f,0x05,0x30]
1172
1173 v_min_u32 v5, v1, v2 quad_perm:[3,2,1,0]
1174 // GFX11: v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0xff]
1175
1176 v_min_u32 v5, v1, v2 quad_perm:[0,1,2,3]
1177 // GFX11: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xff]
1178
1179 v_min_u32 v5, v1, v2 row_mirror
1180 // GFX11: v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0xff]
1181
1182 v_min_u32 v5, v1, v2 row_half_mirror
1183 // GFX11: v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0xff]
1184
1185 v_min_u32 v5, v1, v2 row_shl:1
1186 // GFX11: v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0xff]
1187
1188 v_min_u32 v5, v1, v2 row_shl:15
1189 // GFX11: v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0xff]
1190
1191 v_min_u32 v5, v1, v2 row_shr:1
1192 // GFX11: v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0xff]
1193
1194 v_min_u32 v5, v1, v2 row_shr:15
1195 // GFX11: v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0xff]
1196
1197 v_min_u32 v5, v1, v2 row_ror:1
1198 // GFX11: v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0xff]
1199
1200 v_min_u32 v5, v1, v2 row_ror:15
1201 // GFX11: v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0xff]
1202
1203 v_min_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1204 // GFX11: v_min_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x50,0x01,0xff]
1205
1206 v_min_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1207 // GFX11: v_min_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x01]
1208
1209 v_min_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1210 // GFX11: v_min_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0x60,0x09,0x13]
1211
1212 v_min_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1213 // GFX11: v_min_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x27,0xff,0x6f,0x05,0x30]
1214
1215 v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[3,2,1,0]
1216 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff]
1217
1218 v_mul_dx9_zero_f32 v5, v1, v2 quad_perm:[0,1,2,3]
1219 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff]
1220
1221 v_mul_dx9_zero_f32 v5, v1, v2 row_mirror
1222 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff]
1223
1224 v_mul_dx9_zero_f32 v5, v1, v2 row_half_mirror
1225 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff]
1226
1227 v_mul_dx9_zero_f32 v5, v1, v2 row_shl:1
1228 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff]
1229
1230 v_mul_dx9_zero_f32 v5, v1, v2 row_shl:15
1231 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff]
1232
1233 v_mul_dx9_zero_f32 v5, v1, v2 row_shr:1
1234 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff]
1235
1236 v_mul_dx9_zero_f32 v5, v1, v2 row_shr:15
1237 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff]
1238
1239 v_mul_dx9_zero_f32 v5, v1, v2 row_ror:1
1240 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff]
1241
1242 v_mul_dx9_zero_f32 v5, v1, v2 row_ror:15
1243 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff]
1244
1245 v_mul_dx9_zero_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1246 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff]
1247
1248 v_mul_dx9_zero_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1249 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01]
1250
1251 v_mul_dx9_zero_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1252 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x09,0x13]
1253
1254 v_mul_dx9_zero_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1255 // GFX11: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30]
1256
1257 v_mul_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
1258 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0xff]
1259
1260 v_mul_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
1261 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xff]
1262
1263 v_mul_f16 v5.l, v1.l, v2.l row_mirror
1264 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0xff]
1265
1266 v_mul_f16 v5.l, v1.l, v2.l row_half_mirror
1267 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0xff]
1268
1269 v_mul_f16 v5.l, v1.l, v2.l row_shl:1
1270 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0xff]
1271
1272 v_mul_f16 v5.l, v1.l, v2.l row_shl:15
1273 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0xff]
1274
1275 v_mul_f16 v5.l, v1.l, v2.l row_shr:1
1276 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0xff]
1277
1278 v_mul_f16 v5.l, v1.l, v2.l row_shr:15
1279 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0xff]
1280
1281 v_mul_f16 v5.l, v1.l, v2.l row_ror:1
1282 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0xff]
1283
1284 v_mul_f16 v5.l, v1.l, v2.l row_ror:15
1285 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0xff]
1286
1287 v_mul_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
1288 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x50,0x01,0xff]
1289
1290 v_mul_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
1291 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x01]
1292
1293 v_mul_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
1294 // GFX11: v_mul_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x60,0x09,0x13]
1295
1296 v_mul_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
1297 // GFX11: v_mul_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x6f,0xf5,0x30]
1298
1299 v_mul_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
1300 // GFX11: v_mul_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x6a,0x7f,0x5f,0x01,0x01]
1301
1302 v_mul_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1303 // GFX11: v_mul_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x6b,0x81,0x60,0x09,0x13]
1304
1305 v_mul_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1306 // GFX11: v_mul_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6b,0xff,0x6f,0xf5,0x30]
1307
1308 v_mul_f32 v5, v1, v2 quad_perm:[3,2,1,0]
1309 // GFX11: v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0xff]
1310
1311 v_mul_f32 v5, v1, v2 quad_perm:[0,1,2,3]
1312 // GFX11: v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xff]
1313
1314 v_mul_f32 v5, v1, v2 row_mirror
1315 // GFX11: v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0xff]
1316
1317 v_mul_f32 v5, v1, v2 row_half_mirror
1318 // GFX11: v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0xff]
1319
1320 v_mul_f32 v5, v1, v2 row_shl:1
1321 // GFX11: v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0xff]
1322
1323 v_mul_f32 v5, v1, v2 row_shl:15
1324 // GFX11: v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0xff]
1325
1326 v_mul_f32 v5, v1, v2 row_shr:1
1327 // GFX11: v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0xff]
1328
1329 v_mul_f32 v5, v1, v2 row_shr:15
1330 // GFX11: v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0xff]
1331
1332 v_mul_f32 v5, v1, v2 row_ror:1
1333 // GFX11: v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0xff]
1334
1335 v_mul_f32 v5, v1, v2 row_ror:15
1336 // GFX11: v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0xff]
1337
1338 v_mul_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1339 // GFX11: v_mul_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x50,0x01,0xff]
1340
1341 v_mul_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1342 // GFX11: v_mul_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x01]
1343
1344 v_mul_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1345 // GFX11: v_mul_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x10,0x01,0x60,0x09,0x13]
1346
1347 v_mul_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1348 // GFX11: v_mul_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x11,0xff,0x6f,0xf5,0x30]
1349
1350 v_mul_hi_i32_i24 v5, v1, v2 quad_perm:[3,2,1,0]
1351 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0xff]
1352
1353 v_mul_hi_i32_i24 v5, v1, v2 quad_perm:[0,1,2,3]
1354 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xff]
1355
1356 v_mul_hi_i32_i24 v5, v1, v2 row_mirror
1357 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0xff]
1358
1359 v_mul_hi_i32_i24 v5, v1, v2 row_half_mirror
1360 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0xff]
1361
1362 v_mul_hi_i32_i24 v5, v1, v2 row_shl:1
1363 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0xff]
1364
1365 v_mul_hi_i32_i24 v5, v1, v2 row_shl:15
1366 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0xff]
1367
1368 v_mul_hi_i32_i24 v5, v1, v2 row_shr:1
1369 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0xff]
1370
1371 v_mul_hi_i32_i24 v5, v1, v2 row_shr:15
1372 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0xff]
1373
1374 v_mul_hi_i32_i24 v5, v1, v2 row_ror:1
1375 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0xff]
1376
1377 v_mul_hi_i32_i24 v5, v1, v2 row_ror:15
1378 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0xff]
1379
1380 v_mul_hi_i32_i24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1381 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x50,0x01,0xff]
1382
1383 v_mul_hi_i32_i24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1384 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x01]
1385
1386 v_mul_hi_i32_i24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1387 // GFX11: v_mul_hi_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x14,0x01,0x60,0x09,0x13]
1388
1389 v_mul_hi_i32_i24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1390 // GFX11: v_mul_hi_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x15,0xff,0x6f,0x05,0x30]
1391
1392 v_mul_hi_u32_u24 v5, v1, v2 quad_perm:[3,2,1,0]
1393 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0xff]
1394
1395 v_mul_hi_u32_u24 v5, v1, v2 quad_perm:[0,1,2,3]
1396 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xff]
1397
1398 v_mul_hi_u32_u24 v5, v1, v2 row_mirror
1399 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0xff]
1400
1401 v_mul_hi_u32_u24 v5, v1, v2 row_half_mirror
1402 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0xff]
1403
1404 v_mul_hi_u32_u24 v5, v1, v2 row_shl:1
1405 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0xff]
1406
1407 v_mul_hi_u32_u24 v5, v1, v2 row_shl:15
1408 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0xff]
1409
1410 v_mul_hi_u32_u24 v5, v1, v2 row_shr:1
1411 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0xff]
1412
1413 v_mul_hi_u32_u24 v5, v1, v2 row_shr:15
1414 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0xff]
1415
1416 v_mul_hi_u32_u24 v5, v1, v2 row_ror:1
1417 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0xff]
1418
1419 v_mul_hi_u32_u24 v5, v1, v2 row_ror:15
1420 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0xff]
1421
1422 v_mul_hi_u32_u24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1423 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x50,0x01,0xff]
1424
1425 v_mul_hi_u32_u24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1426 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x01]
1427
1428 v_mul_hi_u32_u24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1429 // GFX11: v_mul_hi_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x18,0x01,0x60,0x09,0x13]
1430
1431 v_mul_hi_u32_u24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1432 // GFX11: v_mul_hi_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x19,0xff,0x6f,0x05,0x30]
1433
1434 v_mul_i32_i24 v5, v1, v2 quad_perm:[3,2,1,0]
1435 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0xff]
1436
1437 v_mul_i32_i24 v5, v1, v2 quad_perm:[0,1,2,3]
1438 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xff]
1439
1440 v_mul_i32_i24 v5, v1, v2 row_mirror
1441 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0xff]
1442
1443 v_mul_i32_i24 v5, v1, v2 row_half_mirror
1444 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0xff]
1445
1446 v_mul_i32_i24 v5, v1, v2 row_shl:1
1447 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0xff]
1448
1449 v_mul_i32_i24 v5, v1, v2 row_shl:15
1450 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0xff]
1451
1452 v_mul_i32_i24 v5, v1, v2 row_shr:1
1453 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0xff]
1454
1455 v_mul_i32_i24 v5, v1, v2 row_shr:15
1456 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0xff]
1457
1458 v_mul_i32_i24 v5, v1, v2 row_ror:1
1459 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0xff]
1460
1461 v_mul_i32_i24 v5, v1, v2 row_ror:15
1462 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0xff]
1463
1464 v_mul_i32_i24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1465 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x50,0x01,0xff]
1466
1467 v_mul_i32_i24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1468 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x01]
1469
1470 v_mul_i32_i24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1471 // GFX11: v_mul_i32_i24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x12,0x01,0x60,0x09,0x13]
1472
1473 v_mul_i32_i24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1474 // GFX11: v_mul_i32_i24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x13,0xff,0x6f,0x05,0x30]
1475
1476 v_mul_legacy_f32 v5, v1, v2 quad_perm:[3,2,1,0]
1477 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0xff]
1478
1479 v_mul_legacy_f32 v5, v1, v2 quad_perm:[0,1,2,3]
1480 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xff]
1481
1482 v_mul_legacy_f32 v5, v1, v2 row_mirror
1483 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0xff]
1484
1485 v_mul_legacy_f32 v5, v1, v2 row_half_mirror
1486 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0xff]
1487
1488 v_mul_legacy_f32 v5, v1, v2 row_shl:1
1489 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0xff]
1490
1491 v_mul_legacy_f32 v5, v1, v2 row_shl:15
1492 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0xff]
1493
1494 v_mul_legacy_f32 v5, v1, v2 row_shr:1
1495 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0xff]
1496
1497 v_mul_legacy_f32 v5, v1, v2 row_shr:15
1498 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0xff]
1499
1500 v_mul_legacy_f32 v5, v1, v2 row_ror:1
1501 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0xff]
1502
1503 v_mul_legacy_f32 v5, v1, v2 row_ror:15
1504 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0xff]
1505
1506 v_mul_legacy_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1507 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x50,0x01,0xff]
1508
1509 v_mul_legacy_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1510 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x01]
1511
1512 v_mul_legacy_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1513 // GFX11: v_mul_dx9_zero_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x60,0x09,0x13]
1514
1515 v_mul_legacy_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1516 // GFX11: v_mul_dx9_zero_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0f,0xff,0x6f,0xf5,0x30]
1517
1518 v_mul_u32_u24 v5, v1, v2 quad_perm:[3,2,1,0]
1519 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0xff]
1520
1521 v_mul_u32_u24 v5, v1, v2 quad_perm:[0,1,2,3]
1522 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xff]
1523
1524 v_mul_u32_u24 v5, v1, v2 row_mirror
1525 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0xff]
1526
1527 v_mul_u32_u24 v5, v1, v2 row_half_mirror
1528 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0xff]
1529
1530 v_mul_u32_u24 v5, v1, v2 row_shl:1
1531 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0xff]
1532
1533 v_mul_u32_u24 v5, v1, v2 row_shl:15
1534 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0xff]
1535
1536 v_mul_u32_u24 v5, v1, v2 row_shr:1
1537 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0xff]
1538
1539 v_mul_u32_u24 v5, v1, v2 row_shr:15
1540 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0xff]
1541
1542 v_mul_u32_u24 v5, v1, v2 row_ror:1
1543 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0xff]
1544
1545 v_mul_u32_u24 v5, v1, v2 row_ror:15
1546 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0xff]
1547
1548 v_mul_u32_u24 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1549 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x50,0x01,0xff]
1550
1551 v_mul_u32_u24 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1552 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x01]
1553
1554 v_mul_u32_u24 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1555 // GFX11: v_mul_u32_u24_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x16,0x01,0x60,0x09,0x13]
1556
1557 v_mul_u32_u24 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1558 // GFX11: v_mul_u32_u24_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x17,0xff,0x6f,0x05,0x30]
1559
1560 v_or_b32 v5, v1, v2 quad_perm:[3,2,1,0]
1561 // GFX11: v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0xff]
1562
1563 v_or_b32 v5, v1, v2 quad_perm:[0,1,2,3]
1564 // GFX11: v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xff]
1565
1566 v_or_b32 v5, v1, v2 row_mirror
1567 // GFX11: v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0xff]
1568
1569 v_or_b32 v5, v1, v2 row_half_mirror
1570 // GFX11: v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0xff]
1571
1572 v_or_b32 v5, v1, v2 row_shl:1
1573 // GFX11: v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0xff]
1574
1575 v_or_b32 v5, v1, v2 row_shl:15
1576 // GFX11: v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0xff]
1577
1578 v_or_b32 v5, v1, v2 row_shr:1
1579 // GFX11: v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0xff]
1580
1581 v_or_b32 v5, v1, v2 row_shr:15
1582 // GFX11: v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0xff]
1583
1584 v_or_b32 v5, v1, v2 row_ror:1
1585 // GFX11: v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0xff]
1586
1587 v_or_b32 v5, v1, v2 row_ror:15
1588 // GFX11: v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0xff]
1589
1590 v_or_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1591 // GFX11: v_or_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x50,0x01,0xff]
1592
1593 v_or_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1594 // GFX11: v_or_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x01]
1595
1596 v_or_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1597 // GFX11: v_or_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x38,0x01,0x60,0x09,0x13]
1598
1599 v_or_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1600 // GFX11: v_or_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x39,0xff,0x6f,0x05,0x30]
1601
1602 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
1603 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff]
1604 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1605
1606 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
1607 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff]
1608 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1609
1610 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror
1611 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff]
1612 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1613
1614 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror
1615 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff]
1616 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1617
1618 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1
1619 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff]
1620 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1621
1622 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15
1623 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff]
1624 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1625
1626 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1
1627 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff]
1628 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1629
1630 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15
1631 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff]
1632 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1633
1634 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1
1635 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff]
1636 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1637
1638 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15
1639 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff]
1640 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1641
1642 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf
1643 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff]
1644 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1645
1646 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
1647 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01]
1648 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1649
1650 v_sub_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1651 // W32: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x09,0x13]
1652 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1653
1654 v_sub_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1655 // W32: v_sub_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x05,0x30]
1656 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1657
1658 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0]
1659 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0xff]
1660 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1661
1662 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
1663 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xff]
1664 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1665
1666 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror
1667 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0xff]
1668 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1669
1670 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror
1671 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0xff]
1672 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1673
1674 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1
1675 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0xff]
1676 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1677
1678 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15
1679 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0xff]
1680 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1681
1682 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1
1683 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0xff]
1684 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1685
1686 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15
1687 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0xff]
1688 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1689
1690 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1
1691 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0xff]
1692 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1693
1694 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15
1695 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0xff]
1696 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1697
1698 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf
1699 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x50,0x01,0xff]
1700 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1701
1702 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
1703 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x5f,0x01,0x01]
1704 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1705
1706 v_sub_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1707 // W64: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x42,0x01,0x60,0x09,0x13]
1708 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1709
1710 v_sub_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1711 // W64: v_sub_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x43,0xff,0x6f,0x05,0x30]
1712 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1713
1714 v_sub_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
1715 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0xff]
1716
1717 v_sub_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
1718 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xff]
1719
1720 v_sub_f16 v5.l, v1.l, v2.l row_mirror
1721 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0xff]
1722
1723 v_sub_f16 v5.l, v1.l, v2.l row_half_mirror
1724 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0xff]
1725
1726 v_sub_f16 v5.l, v1.l, v2.l row_shl:1
1727 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0xff]
1728
1729 v_sub_f16 v5.l, v1.l, v2.l row_shl:15
1730 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0xff]
1731
1732 v_sub_f16 v5.l, v1.l, v2.l row_shr:1
1733 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0xff]
1734
1735 v_sub_f16 v5.l, v1.l, v2.l row_shr:15
1736 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0xff]
1737
1738 v_sub_f16 v5.l, v1.l, v2.l row_ror:1
1739 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0xff]
1740
1741 v_sub_f16 v5.l, v1.l, v2.l row_ror:15
1742 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0xff]
1743
1744 v_sub_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
1745 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x50,0x01,0xff]
1746
1747 v_sub_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
1748 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x01]
1749
1750 v_sub_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
1751 // GFX11: v_sub_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0x60,0x09,0x13]
1752
1753 v_sub_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
1754 // GFX11: v_sub_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x6f,0xf5,0x30]
1755
1756 v_sub_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
1757 // GFX11: v_sub_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x66,0x7f,0x5f,0x01,0x01]
1758
1759 v_sub_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1760 // GFX11: v_sub_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x67,0x81,0x60,0x09,0x13]
1761
1762 v_sub_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1763 // GFX11: v_sub_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x67,0xff,0x6f,0xf5,0x30]
1764
1765 v_sub_f32 v5, v1, v2 quad_perm:[3,2,1,0]
1766 // GFX11: v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0xff]
1767
1768 v_sub_f32 v5, v1, v2 quad_perm:[0,1,2,3]
1769 // GFX11: v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xff]
1770
1771 v_sub_f32 v5, v1, v2 row_mirror
1772 // GFX11: v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0xff]
1773
1774 v_sub_f32 v5, v1, v2 row_half_mirror
1775 // GFX11: v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0xff]
1776
1777 v_sub_f32 v5, v1, v2 row_shl:1
1778 // GFX11: v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0xff]
1779
1780 v_sub_f32 v5, v1, v2 row_shl:15
1781 // GFX11: v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0xff]
1782
1783 v_sub_f32 v5, v1, v2 row_shr:1
1784 // GFX11: v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0xff]
1785
1786 v_sub_f32 v5, v1, v2 row_shr:15
1787 // GFX11: v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0xff]
1788
1789 v_sub_f32 v5, v1, v2 row_ror:1
1790 // GFX11: v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0xff]
1791
1792 v_sub_f32 v5, v1, v2 row_ror:15
1793 // GFX11: v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0xff]
1794
1795 v_sub_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1796 // GFX11: v_sub_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x50,0x01,0xff]
1797
1798 v_sub_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1799 // GFX11: v_sub_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x01]
1800
1801 v_sub_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1802 // GFX11: v_sub_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x08,0x01,0x60,0x09,0x13]
1803
1804 v_sub_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1805 // GFX11: v_sub_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x09,0xff,0x6f,0xf5,0x30]
1806
1807 v_sub_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0]
1808 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0xff]
1809
1810 v_sub_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3]
1811 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xff]
1812
1813 v_sub_nc_u32 v5, v1, v2 row_mirror
1814 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0xff]
1815
1816 v_sub_nc_u32 v5, v1, v2 row_half_mirror
1817 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0xff]
1818
1819 v_sub_nc_u32 v5, v1, v2 row_shl:1
1820 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0xff]
1821
1822 v_sub_nc_u32 v5, v1, v2 row_shl:15
1823 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0xff]
1824
1825 v_sub_nc_u32 v5, v1, v2 row_shr:1
1826 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0xff]
1827
1828 v_sub_nc_u32 v5, v1, v2 row_shr:15
1829 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0xff]
1830
1831 v_sub_nc_u32 v5, v1, v2 row_ror:1
1832 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0xff]
1833
1834 v_sub_nc_u32 v5, v1, v2 row_ror:15
1835 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0xff]
1836
1837 v_sub_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
1838 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x50,0x01,0xff]
1839
1840 v_sub_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
1841 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x5f,0x01,0x01]
1842
1843 v_sub_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1844 // GFX11: v_sub_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x4c,0x01,0x60,0x09,0x13]
1845
1846 v_sub_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1847 // GFX11: v_sub_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4d,0xff,0x6f,0x05,0x30]
1848
1849 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0]
1850 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff]
1851 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1852
1853 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
1854 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff]
1855 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1856
1857 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_mirror
1858 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff]
1859 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1860
1861 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_half_mirror
1862 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff]
1863 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1864
1865 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:1
1866 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff]
1867 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1868
1869 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shl:15
1870 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff]
1871 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1872
1873 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:1
1874 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff]
1875 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1876
1877 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_shr:15
1878 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff]
1879 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1880
1881 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:1
1882 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff]
1883 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1884
1885 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_ror:15
1886 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff]
1887 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1888
1889 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf
1890 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff]
1891 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1892
1893 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1
1894 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01]
1895 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1896
1897 v_subrev_co_ci_u32 v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1898 // W32: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x09,0x13]
1899 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1900
1901 v_subrev_co_ci_u32 v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1902 // W32: v_subrev_co_ci_u32_dpp v255, vcc_lo, v255, v255, vcc_lo row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30]
1903 // W64-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1904
1905 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0]
1906 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0xff]
1907 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1908
1909 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
1910 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xff]
1911 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1912
1913 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_mirror
1914 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0xff]
1915 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1916
1917 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_half_mirror
1918 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0xff]
1919 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1920
1921 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:1
1922 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0xff]
1923 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1924
1925 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shl:15
1926 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0xff]
1927 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1928
1929 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:1
1930 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0xff]
1931 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1932
1933 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_shr:15
1934 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0xff]
1935 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1936
1937 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:1
1938 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0xff]
1939 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1940
1941 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_ror:15
1942 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0xff]
1943 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1944
1945 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf
1946 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x50,0x01,0xff]
1947 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1948
1949 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1
1950 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x5f,0x01,0x01]
1951 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1952
1953 v_subrev_co_ci_u32 v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
1954 // W64: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x44,0x01,0x60,0x09,0x13]
1955 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1956
1957 v_subrev_co_ci_u32 v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
1958 // W64: v_subrev_co_ci_u32_dpp v255, vcc, v255, v255, vcc row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x45,0xff,0x6f,0x05,0x30]
1959 // W32-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
1960
1961 v_subrev_f16 v5.l, v1.l, v2.l quad_perm:[3,2,1,0]
1962 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0xff]
1963
1964 v_subrev_f16 v5.l, v1.l, v2.l quad_perm:[0,1,2,3]
1965 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xff]
1966
1967 v_subrev_f16 v5.l, v1.l, v2.l row_mirror
1968 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0xff]
1969
1970 v_subrev_f16 v5.l, v1.l, v2.l row_half_mirror
1971 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0xff]
1972
1973 v_subrev_f16 v5.l, v1.l, v2.l row_shl:1
1974 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0xff]
1975
1976 v_subrev_f16 v5.l, v1.l, v2.l row_shl:15
1977 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0xff]
1978
1979 v_subrev_f16 v5.l, v1.l, v2.l row_shr:1
1980 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0xff]
1981
1982 v_subrev_f16 v5.l, v1.l, v2.l row_shr:15
1983 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0xff]
1984
1985 v_subrev_f16 v5.l, v1.l, v2.l row_ror:1
1986 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0xff]
1987
1988 v_subrev_f16 v5.l, v1.l, v2.l row_ror:15
1989 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0xff]
1990
1991 v_subrev_f16 v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf
1992 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x50,0x01,0xff]
1993
1994 v_subrev_f16 v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1
1995 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x01]
1996
1997 v_subrev_f16 v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1
1998 // GFX11: v_subrev_f16_dpp v5.l, v1.l, v2.l row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0x60,0x09,0x13]
1999
2000 v_subrev_f16 v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1
2001 // GFX11: v_subrev_f16_dpp v127.l, -|v127.l|, -|v127.l| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x6f,0xf5,0x30]
2002
2003 v_subrev_f16 v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1
2004 // GFX11: v_subrev_f16_dpp v127.l, v127.l, v127.l row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0xfe,0xfe,0x68,0x7f,0x5f,0x01,0x01]
2005
2006 v_subrev_f16 v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
2007 // GFX11: v_subrev_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0b,0x69,0x81,0x60,0x09,0x13]
2008
2009 v_subrev_f16 v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2010 // GFX11: v_subrev_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x69,0xff,0x6f,0xf5,0x30]
2011
2012 v_subrev_f32 v5, v1, v2 quad_perm:[3,2,1,0]
2013 // GFX11: v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0xff]
2014
2015 v_subrev_f32 v5, v1, v2 quad_perm:[0,1,2,3]
2016 // GFX11: v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xff]
2017
2018 v_subrev_f32 v5, v1, v2 row_mirror
2019 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0xff]
2020
2021 v_subrev_f32 v5, v1, v2 row_half_mirror
2022 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0xff]
2023
2024 v_subrev_f32 v5, v1, v2 row_shl:1
2025 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0xff]
2026
2027 v_subrev_f32 v5, v1, v2 row_shl:15
2028 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0xff]
2029
2030 v_subrev_f32 v5, v1, v2 row_shr:1
2031 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0xff]
2032
2033 v_subrev_f32 v5, v1, v2 row_shr:15
2034 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0xff]
2035
2036 v_subrev_f32 v5, v1, v2 row_ror:1
2037 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0xff]
2038
2039 v_subrev_f32 v5, v1, v2 row_ror:15
2040 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0xff]
2041
2042 v_subrev_f32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
2043 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x50,0x01,0xff]
2044
2045 v_subrev_f32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
2046 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x01]
2047
2048 v_subrev_f32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
2049 // GFX11: v_subrev_f32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x60,0x09,0x13]
2050
2051 v_subrev_f32 v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2052 // GFX11: v_subrev_f32_dpp v255, -|v255|, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x0b,0xff,0x6f,0xf5,0x30]
2053
2054 v_subrev_nc_u32 v5, v1, v2 quad_perm:[3,2,1,0]
2055 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0xff]
2056
2057 v_subrev_nc_u32 v5, v1, v2 quad_perm:[0,1,2,3]
2058 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xff]
2059
2060 v_subrev_nc_u32 v5, v1, v2 row_mirror
2061 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0xff]
2062
2063 v_subrev_nc_u32 v5, v1, v2 row_half_mirror
2064 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0xff]
2065
2066 v_subrev_nc_u32 v5, v1, v2 row_shl:1
2067 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0xff]
2068
2069 v_subrev_nc_u32 v5, v1, v2 row_shl:15
2070 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0xff]
2071
2072 v_subrev_nc_u32 v5, v1, v2 row_shr:1
2073 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0xff]
2074
2075 v_subrev_nc_u32 v5, v1, v2 row_shr:15
2076 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0xff]
2077
2078 v_subrev_nc_u32 v5, v1, v2 row_ror:1
2079 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0xff]
2080
2081 v_subrev_nc_u32 v5, v1, v2 row_ror:15
2082 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0xff]
2083
2084 v_subrev_nc_u32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
2085 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x50,0x01,0xff]
2086
2087 v_subrev_nc_u32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
2088 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x5f,0x01,0x01]
2089
2090 v_subrev_nc_u32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
2091 // GFX11: v_subrev_nc_u32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x60,0x09,0x13]
2092
2093 v_subrev_nc_u32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2094 // GFX11: v_subrev_nc_u32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x4f,0xff,0x6f,0x05,0x30]
2095
2096 v_xnor_b32 v5, v1, v2 quad_perm:[3,2,1,0]
2097 // GFX11: v_xnor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0xff]
2098
2099 v_xnor_b32 v5, v1, v2 quad_perm:[0,1,2,3]
2100 // GFX11: v_xnor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xff]
2101
2102 v_xnor_b32 v5, v1, v2 row_mirror
2103 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0xff]
2104
2105 v_xnor_b32 v5, v1, v2 row_half_mirror
2106 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0xff]
2107
2108 v_xnor_b32 v5, v1, v2 row_shl:1
2109 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0xff]
2110
2111 v_xnor_b32 v5, v1, v2 row_shl:15
2112 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0xff]
2113
2114 v_xnor_b32 v5, v1, v2 row_shr:1
2115 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0xff]
2116
2117 v_xnor_b32 v5, v1, v2 row_shr:15
2118 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0xff]
2119
2120 v_xnor_b32 v5, v1, v2 row_ror:1
2121 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0xff]
2122
2123 v_xnor_b32 v5, v1, v2 row_ror:15
2124 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0xff]
2125
2126 v_xnor_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
2127 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x50,0x01,0xff]
2128
2129 v_xnor_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
2130 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x01]
2131
2132 v_xnor_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
2133 // GFX11: v_xnor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x60,0x09,0x13]
2134
2135 v_xnor_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2136 // GFX11: v_xnor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3d,0xff,0x6f,0x05,0x30]
2137
2138 v_xor_b32 v5, v1, v2 quad_perm:[3,2,1,0]
2139 // GFX11: v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0xff]
2140
2141 v_xor_b32 v5, v1, v2 quad_perm:[0,1,2,3]
2142 // GFX11: v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xff]
2143
2144 v_xor_b32 v5, v1, v2 row_mirror
2145 // GFX11: v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0xff]
2146
2147 v_xor_b32 v5, v1, v2 row_half_mirror
2148 // GFX11: v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0xff]
2149
2150 v_xor_b32 v5, v1, v2 row_shl:1
2151 // GFX11: v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0xff]
2152
2153 v_xor_b32 v5, v1, v2 row_shl:15
2154 // GFX11: v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0xff]
2155
2156 v_xor_b32 v5, v1, v2 row_shr:1
2157 // GFX11: v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0xff]
2158
2159 v_xor_b32 v5, v1, v2 row_shr:15
2160 // GFX11: v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0xff]
2161
2162 v_xor_b32 v5, v1, v2 row_ror:1
2163 // GFX11: v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0xff]
2164
2165 v_xor_b32 v5, v1, v2 row_ror:15
2166 // GFX11: v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0xff]
2167
2168 v_xor_b32 v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf
2169 // GFX11: v_xor_b32_dpp v5, v1, v2 row_share:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x50,0x01,0xff]
2170
2171 v_xor_b32 v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1
2172 // GFX11: v_xor_b32_dpp v5, v1, v2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x01]
2173
2174 v_xor_b32 v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
2175 // GFX11: v_xor_b32_dpp v5, v1, v2 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 ; encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x60,0x09,0x13]
2176
2177 v_xor_b32 v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
2178 // GFX11: v_xor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x05,0x30]