llvm/test/MC/ARM/thumb2-diagnostics.s

   1 @ RUN: not llvm-mc -triple=thumbv7-apple-darwin < %s 2> %t
   2 @ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s
   3
   4 @ RUN: not llvm-mc -triple=thumbv8-apple-darwin < %s 2> %t
   5 @ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s
   6
   7 @ Ill-formed IT block instructions.
   8         itet eq
   9         addle r0, r1, r2
  10         nop
  11         it le
  12         iteeee gt
  13         ittfe le
  14         nopeq
  15
  16 @ CHECK-ERRORS: error: incorrect condition in IT block; got 'le', but expected 'eq'
  17 @ CHECK-ERRORS:         addle r0, r1, r2
  18 @ CHECK-ERRORS:            ^
  19 @ CHECK-ERRORS: error: incorrect condition in IT block; got 'al', but expected 'ne'
  20 @ CHECK-ERRORS:         nop
  21 @ CHECK-ERRORS:            ^
  22 @ CHECK-ERRORS: error: instructions in IT block must be predicable
  23 @ CHECK-ERRORS:         it le
  24 @ CHECK-ERRORS:         ^
  25 @ CHECK-ERRORS: error: too many conditions on IT instruction
  26 @ CHECK-ERRORS:         iteeee gt
  27 @ CHECK-ERRORS:           ^
  28 @ CHECK-ERRORS: error: illegal IT block condition mask 'tfe'
  29 @ CHECK-ERRORS:         ittfe le
  30 @ CHECK-ERRORS:           ^
  31 @ CHECK-ERRORS: error: predicated instructions must be in IT block
  32 @ CHECK-ERRORS:         nopeq
  33 @ CHECK-ERRORS:         ^
  34
  35         @ Out of range immediates for MRC/MRC2/MRRC/MRRC2
  36         mrc  p14, #8, r1, c1, c2, #4
  37         mrc  p14, #1, r1, c1, c2, #8
  38         mrc2  p14, #8, r1, c1, c2, #4
  39         mrc2  p14, #0, r1, c1, c2, #9
  40         mrrc  p14, #16, r5, r4, c1
  41         mrrc2  p14, #17, r5, r4, c1
  42 @ CHECK-ERRORS: operand must be an immediate in the range [0,7]
  43 @ CHECK-ERRORS: operand must be an immediate in the range [0,7]
  44 @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
  45 @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,7]
  46 @ CHECK-ERRORS-V8: invalid instruction
  47 @ CHECK-ERRORS-V8: too many operands for instruction
  48 @ CHECK-ERRORS: operand must be an immediate in the range [0,15]
  49 @ CHECK-ERRORS-V7: operand must be an immediate in the range [0,15]
  50 @ CHECK-ERRORS-V8: invalid instruction
  51
  52         @ Out of range immediate for ROR.
  53         @ (Assembling this instruction to "mov r1, r1" might also be OK.)
  54         ror r1, r1, #0
  55 @ CHECK-ERRORS: invalid instruction
  56 @ CHECK-ERRORS: operand must be an immediate in the range [1,31]
  57
  58         isb  #-1
  59         isb  #16
  60 @ CHECK-ERRORS: error: immediate value out of range
  61 @ CHECK-ERRORS: error: immediate value out of range
  62
  63         itt eq
  64         bkpteq #1
  65 @ CHECK-ERRORS: error: instruction 'bkpt' is not predicable, but condition code specified
  66
  67         nopeq
  68         nopeq
  69
  70 @ out of range operands for Thumb2 targets
  71
  72         beq.w  #-1048578
  73         bne.w  #1048576
  74         blt.w  #1013411
  75         b.w    #-16777218
  76         b.w    #16777216
  77         b.w    #1592313
  78
  79 @ CHECK-ERRORS: error: branch target out of range
  80 @ CHECK-ERRORS: error: branch target out of range
  81 @ CHECK-ERRORS: error: branch target out of range
  82 @ CHECK-ERRORS: error: branch target out of range
  83 @ CHECK-ERRORS: error: branch target out of range
  84 @ CHECK-ERRORS: error: branch target out of range
  85
  86 foo2:
  87         movw r0, foo2
  88         movt r0, foo2
  89         movt r0, #0x10000
  90         movt r0, #0x10000
  91 @ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16
  92 @ CHECK-ERRORS:                  ^
  93 @ CHECK-ERRORS: immediate expression for mov requires :lower16: or :upper16
  94 @ CHECK-ERRORS:                  ^
  95 @ CHECK-ERRORS: error: operand must be an immediate in the range [0,0xffff] or a relocatable expression
  96 @ CHECK-ERRORS: error: operand must be an immediate in the range [0,0xffff] or a relocatable expression
  97
  98         and sp, r1, #80008000
  99         and pc, r1, #80008000
 100 @ CHECK-ERRORS: error: invalid instruction
 101 @ CHECK-ERRORS: error: invalid instruction
 102
 103         ssat r0, #1, r0, asr #32
 104         usat r0, #1, r0, asr #32
 105 @ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
 106 @ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
 107
 108         @ PC is not valid as shifted-rGPR
 109         sbc.w r2, r7, pc, lsr #16
 110         and.w r2, r7, pc, lsr #16
 111 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 112 @ CHECK-ERRORS: note: invalid operand for instruction
 113 @ CHECK-ERRORS-V7: note: operand must be a register in range [r0, r12] or r14
 114 @ CHECK-ERRORS-V8: note: operand must be a register in range [r0, r14]
 115 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 116 @ CHECK-ERRORS: note: invalid operand for instruction
 117 @ CHECK-ERRORS-V7: note: operand must be a register in range [r0, r12] or r14
 118 @ CHECK-ERRORS-V8: note: operand must be a register in range [r0, r14]
 119
 120
 121         @ PC is not valid as base of load
 122         ldr r0, [pc, r0]
 123         ldrb r1, [pc, r2]
 124         ldrh r3, [pc, r3]
 125         pld r4, [pc, r5]
 126         str r6, [pc, r7]
 127         strb r7 [pc, r8]
 128         strh r9, [pc, r10]
 129 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 130 @ CHECK-ERRORS: note: invalid operand for instruction
 131 @ CHECK-ERRORS: note: instruction requires: arm-mode
 132 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 133 @ CHECK-ERRORS: note: invalid operand for instruction
 134 @ CHECK-ERRORS: note: instruction requires: arm-mode
 135 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 136 @ CHECK-ERRORS: note: instruction requires: arm-mode
 137 @ CHECK-ERRORS: note: invalid operand for instruction
 138 @ CHECK-ERRORS: error: invalid instruction
 139 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 140 @ CHECK-ERRORS: note: invalid operand for instruction
 141 @ CHECK-ERRORS: note: instruction requires: arm-mode
 142 @ CHECK-ERRORS: error: immediate value expected for vector index
 143 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 144 @ CHECK-ERRORS: note: instruction requires: arm-mode
 145 @ CHECK-ERRORS: note: invalid operand for instruction
 146
 147         @ SWP(B) is an ARM-only instruction
 148         swp  r0, r1, [r2]
 149         swpb r3, r4, [r5]
 150 @ CHECK-ERRORS-V7: error: instruction requires: arm-mode
 151 @ CHECK-ERRORS-V7: error: instruction requires: arm-mode
 152 @ CHECK-ERRORS-V8: error: invalid instruction
 153 @ CHECK-ERRORS-V8: error: invalid instruction
 154
 155         @ Generic error for too few operands
 156         adds
 157         adds r0
 158 @ CHECK-ERRORS: error: too few operands for instruction
 159 @ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this:
 160 @ CHECK-ERRORS: note: too few operands for instruction
 161 @ CHECK-ERRORS: note: operand must be a register in range [r0, r15]
 162
 163         tst sp, #3
 164         tst sp, r5
 165         tst sp, r5, lsl #3
 166 @ CHECK-ERRORS-V7: error: operand must be a register in range [r0, r12] or r14
 167 @ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
 168 @ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
 169
 170         teq sp, #5
 171         teq sp, r7
 172         teq sp, r9, lsl #2
 173 @ CHECK-ERRORS-V7: error: operand must be a register in range [r0, r12] or r14
 174 @ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
 175 @ CHECK-ERRORS-V7: operand must be a register in range [r0, r12] or r14
 176
 177         tbb [r0, sp]
 178         @ v8 allows rm = sp
 179 @ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
 180         tbb [r0, pc]
 181         @ rm = pc is always unpredictable
 182 @ CHECK-ERRORS: error: invalid operand for instruction
 183         tbb [sp, r0]
 184         @ v8 allows rn = sp
 185 @ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
 186         @ rn = pc is allowed so not included here
 187
 188         tbh [r0, sp, lsl #1]
 189         @ v8 allows rm = sp
 190 @ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
 191         tbh [r0, pc, lsl #1]
 192         @ rm = pc is always unpredictable
 193 @ CHECK-ERRORS: error: invalid operand for instruction
 194         tbh [sp, r0, lsl #1]
 195         @ v8 allows rn = sp
 196 @ CHECK-ERRORS-V7: error: instruction variant requires ARMv8 or later
 197         @ rn=pc is allowed so not included here