[AMDGPU][True16][CodeGen] true16 codegen pattern for v_med3_u/i16 (#121850)
[llvm-project.git] / llvm / test / MC / AVR / inst-in.s
blobe17f25b67d03de148d72c5a908503031ec47731a
1 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
2 ; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump --no-print-imm-hex -dr - | FileCheck -check-prefix=CHECK-INST %s
4 foo:
5 in r2, 4
6 in r9, 6
7 in r5, 32
8 in r0, 0
9 in r31, 0
10 in r0, 63
11 in r31, 63
13 in r20, foo+1
15 ; CHECK: in r2, 4 ; encoding: [0x24,0xb0]
16 ; CHECK: in r9, 6 ; encoding: [0x96,0xb0]
17 ; CHECK: in r5, 32 ; encoding: [0x50,0xb4]
18 ; CHECK: in r0, 0 ; encoding: [0x00,0xb0]
19 ; CHECK: in r31, 0 ; encoding: [0xf0,0xb1]
20 ; CHECK: in r0, 63 ; encoding: [0x0f,0xb6]
21 ; CHECK: in r31, 63 ; encoding: [0xff,0xb7]
23 ; CHECK: in r20, foo+1 ; encoding: [0x40'A',0xb1'A']
24 ; CHECK: ; fixup A - offset: 0, value: foo+1, kind: fixup_port6
26 ; CHECK-INST: in r2, 4
27 ; CHECK-INST: in r9, 6
28 ; CHECK-INST: in r5, 32
29 ; CHECK-INST: in r0, 0
30 ; CHECK-INST: in r31, 0
31 ; CHECK-INST: in r0, 63
32 ; CHECK-INST: in r31, 63
34 ; CHECK-INST: in r20, 0