[AMDGPU][True16][CodeGen] true16 codegen pattern for v_med3_u/i16 (#121850)
[llvm-project.git] / llvm / test / MC / AVR / inst-movw.s
blob12dc649f24497f8fa37d550378633bf2259f09b1
1 ; RUN: llvm-mc -triple avr -mattr=movw -show-encoding < %s | FileCheck %s
2 ; RUN: llvm-mc -filetype=obj -triple avr -mattr=movw < %s | llvm-objdump -dr --mattr=movw - | FileCheck -check-prefix=CHECK-INST %s
4 foo:
5 movw r10, r8
6 movw r12, r16
7 movw r20, r22
8 movw r8, r12
9 movw r0, r0
10 movw r0, r30
11 movw r30, r30
12 movw r30, r0
14 ; CHECK: movw r10, r8 ; encoding: [0x54,0x01]
15 ; CHECK: movw r12, r16 ; encoding: [0x68,0x01]
16 ; CHECK: movw r20, r22 ; encoding: [0xab,0x01]
17 ; CHECK: movw r8, r12 ; encoding: [0x46,0x01]
18 ; CHECK: movw r0, r0 ; encoding: [0x00,0x01]
19 ; CHECK: movw r0, r30 ; encoding: [0x0f,0x01]
20 ; CHECK: movw r30, r30 ; encoding: [0xff,0x01]
21 ; CHECK: movw r30, r0 ; encoding: [0xf0,0x01]
23 ; CHECK-INST: movw r10, r8
24 ; CHECK-INST: movw r12, r16
25 ; CHECK-INST: movw r20, r22
26 ; CHECK-INST: movw r8, r12
27 ; CHECK-INST: movw r0, r0
28 ; CHECK-INST: movw r0, r30
29 ; CHECK-INST: movw r30, r30
30 ; CHECK-INST: movw r30, r0