[AMDGPU][True16][CodeGen] true16 codegen pattern for v_med3_u/i16 (#121850)
[llvm-project.git] / llvm / test / MC / AVR / inst-sbic.s
blob1e8abdb29228d409ea6678fe8151dd6088b144b4
1 ; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
2 ; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump --no-print-imm-hex -dr - | FileCheck -check-prefix=CHECK-INST %s
4 foo:
5 sbic 4, 3
6 sbic 6, 2
7 sbic 16, 5
8 sbic 0, 0
9 sbic 31, 0
10 sbic 0, 7
11 sbic 31, 7
13 sbic foo+1, 1
15 ; CHECK: sbic 4, 3 ; encoding: [0x23,0x99]
16 ; CHECK: sbic 6, 2 ; encoding: [0x32,0x99]
17 ; CHECK: sbic 16, 5 ; encoding: [0x85,0x99]
18 ; CHECK: sbic 0, 0 ; encoding: [0x00,0x99]
19 ; CHECK: sbic 31, 0 ; encoding: [0xf8,0x99]
20 ; CHECK: sbic 0, 7 ; encoding: [0x07,0x99]
21 ; CHECK: sbic 31, 7 ; encoding: [0xff,0x99]
23 ; CHECK: sbic foo+1, 1 ; encoding: [0bAAAAA001,0x99]
24 ; CHECK: ; fixup A - offset: 0, value: foo+1, kind: fixup_port5
26 ; CHECK-INST: sbic 4, 3
27 ; CHECK-INST: sbic 6, 2
28 ; CHECK-INST: sbic 16, 5
29 ; CHECK-INST: sbic 0, 0
30 ; CHECK-INST: sbic 31, 0
31 ; CHECK-INST: sbic 0, 7
32 ; CHECK-INST: sbic 31, 7
34 ; CHECK-INST: sbic 0, 1