[AMDGPU][True16][CodeGen] true16 codegen pattern for v_med3_u/i16 (#121850)
[llvm-project.git] / llvm / test / MC / AVR / inst-sbiw.s
blob640f503c62aea352e266da269505f0ce4dae9181
1 ; RUN: llvm-mc -triple avr -mattr=addsubiw -show-encoding < %s | FileCheck %s
2 ; RUN: llvm-mc -filetype=obj -triple avr -mattr=addsubiw < %s | llvm-objdump --no-print-imm-hex -dr --mattr=addsubiw - | FileCheck --check-prefix=CHECK-INST %s
4 foo:
5 sbiw r26, 54
6 sbiw X, 63
8 sbiw 28, 52
9 sbiw r28, 0
11 sbiw r30, 63
12 sbiw Z, 47
14 sbiw r24, 1
15 sbiw r24, 2
17 sbiw r24, SYMBOL-1
18 sbiw r24, z+15
20 ; CHECK: sbiw r26, 54 ; encoding: [0xd6,0x97]
21 ; CHECK: sbiw r26, 63 ; encoding: [0xdf,0x97]
23 ; CHECK: sbiw r28, 52 ; encoding: [0xe4,0x97]
24 ; CHECK: sbiw r28, 0 ; encoding: [0x20,0x97]
26 ; CHECK: sbiw r30, 63 ; encoding: [0xff,0x97]
27 ; CHECK: sbiw r30, 47 ; encoding: [0xbf,0x97]
29 ; CHECK: sbiw r24, 1 ; encoding: [0x01,0x97]
30 ; CHECK: sbiw r24, 2 ; encoding: [0x02,0x97]
32 ; CHECK: sbiw r24, SYMBOL-1 ; encoding: [0b00AAAAAA,0x97]
33 ; fixup A - offset: 0, value: SYMBOL-1, kind: fixup_6_adiw
34 ; CHECK: sbiw r24, z+15 ; encoding: [0b00AAAAAA,0x97]
35 ; fixup A - offset: 0, value: z+15, kind: fixup_6_adiw
37 ; CHECK-INST: sbiw r26, 54
38 ; CHECK-INST: sbiw r26, 63
40 ; CHECK-INST: sbiw r28, 52
41 ; CHECK-INST: sbiw r28, 0
43 ; CHECK-INST: sbiw r30, 63
44 ; CHECK-INST: sbiw r30, 47
46 ; CHECK-INST: sbiw r24, 1
47 ; CHECK-INST: sbiw r24, 2
49 ; CHECK-INST: sbiw r24, 0
50 ; CHECK-INST: R_AVR_6_ADIW SYMBOL-0x1
51 ; CHECK-INST: sbiw r24, 0
52 ; CHECK-INST: R_AVR_6_ADIW z+0xf