[AMDGPU][True16][CodeGen] true16 codegen pattern for v_med3_u/i16 (#121850)
[llvm-project.git] / llvm / test / MC / AsmParser / macro-irp.s
blobd2ddd2a24a0bc32088156d3686b4f48f1ffa8819
1 # RUN: rm -rf %t && split-file %s %t && cd %t
2 # RUN: llvm-mc -triple=x86_64 a.s | FileCheck %s
4 #--- a.s
5 # CHECK: pushq %rax
6 # CHECK-NEXT: pushq %rbx
7 # CHECK-NEXT: pushq %rcx
8 .irp reg,%rax,%rbx
9 pushq \reg
10 .endr
11 pushq %rcx
13 # CHECK: addl %eax, 4
14 # CHECK-NEXT: addl %eax, 3
15 # CHECK-NEXT: addl %eax, 5
16 # CHECK-NEXT: addl %ebx, 4
17 # CHECK-NEXT: addl %ebx, 3
18 # CHECK-NEXT: addl %ebx, 5
19 # CHECK-EMPTY:
20 # CHECK-NEXT: nop
21 .irp reg,%eax,%ebx
22 .irp imm,4,3,5
23 addl \reg, \imm
24 .endr # comment after .endr
25 .endr ;
26 nop
28 # CHECK: xorl %eax, %eax
29 # CHECK-EMPTY:
30 # CHECK-NEXT: nop
31 .irp reg,%eax
32 xor \reg,\reg
33 .endr
34 # 99 "a.s"
35 nop
37 # RUN: not llvm-mc -triple=x86_64 err1.s 2>&1 | FileCheck %s --check-prefix=ERR1
38 # ERR1: .s:1:1: error: no matching '.endr' in definition
39 #--- err1.s
40 .irp reg,%eax