1 # RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble -print-imm-hex < %s | FileCheck %s
10 # CHECK: abs.8b v0, v0
11 # CHECK: abs.16b v0, v0
12 # CHECK: abs.4h v0, v0
13 # CHECK: abs.8h v0, v0
14 # CHECK: abs.2s v0, v0
15 # CHECK: abs.4s v0, v0
25 # CHECK: add.8b v0, v0, v0
26 # CHECK: add.16b v0, v0, v0
27 # CHECK: add.4h v0, v0, v0
28 # CHECK: add.8h v0, v0, v0
29 # CHECK: add.2s v0, v0, v0
30 # CHECK: add.4s v0, v0, v0
31 # CHECK: add.2d v0, v0, v0
35 # CHECK: add d1, d2, d3
44 # CHECK: addhn.8b v0, v0, v0
45 # CHECK: addhn2.16b v0, v0, v0
46 # CHECK: addhn.4h v0, v0, v0
47 # CHECK: addhn2.8h v0, v0, v0
48 # CHECK: addhn.2s v0, v0, v0
49 # CHECK: addhn2.4s v0, v0, v0
59 # CHECK: addp.8b v0, v0, v0
60 # CHECK: addp.16b v0, v0, v0
61 # CHECK: addp.4h v0, v0, v0
62 # CHECK: addp.8h v0, v0, v0
63 # CHECK: addp.2s v0, v0, v0
64 # CHECK: addp.4s v0, v0, v0
65 # CHECK: addp.2d v0, v0, v0
69 # CHECK: addp.2d d0, v0
77 # CHECK: addv.8b b0, v0
78 # CHECK: addv.16b b0, v0
79 # CHECK: addv.4h h0, v0
80 # CHECK: addv.8h h0, v0
81 # CHECK: addv.4s s0, v0
93 # CHECK: dup.2d v0, x3
94 # CHECK: dup.4s v0, w3
95 # CHECK: dup.2s v0, w3
96 # CHECK: dup.8h v0, w3
97 # CHECK: dup.4h v0, w3
98 # CHECK: dup.16b v0, w3
99 # CHECK: dup.8b v0, w3
109 # CHECK: dup.2d v0, v3[1]
110 # CHECK: dup.2s v0, v3[1]
111 # CHECK: dup.4s v0, v3[1]
112 # CHECK: dup.4h v0, v3[1]
113 # CHECK: dup.8h v0, v3[1]
114 # CHECK: dup.8b v0, v3[1]
115 # CHECK: dup.16b v0, v3[1]
125 # CHECK: smov.s x3, v2[2]
126 # CHECK: smov.s x3, v2[2]
127 # CHECK: mov.s w3, v2[2]
128 # CHECK: mov.s w3, v2[2]
129 # CHECK: mov.d x3, v2[1]
130 # CHECK: mov.d x3, v2[1]
142 # CHECK: mov.d v2[1], x5
143 # CHECK: mov.s v2[1], w5
144 # CHECK: mov.h v2[1], w5
145 # CHECK: mov.b v2[1], w5
147 # CHECK: mov.d v2[1], x5
148 # CHECK: mov.s v2[1], w5
149 # CHECK: mov.h v2[1], w5
150 # CHECK: mov.b v2[1], w5
162 # CHECK: mov.d v2[1], v15[1]
163 # CHECK: mov.s v2[1], v15[1]
164 # CHECK: mov.h v2[1], v15[1]
165 # CHECK: mov.b v2[1], v15[1]
167 # CHECK: mov.d v2[1], v15[0]
168 # CHECK: mov.s v2[3], v15[2]
169 # CHECK: mov.h v2[7], v15[3]
170 # CHECK: mov.b v2[10], v15[5]
172 # INS/DUP (non-standard)
181 # CHECK: dup.2d v0, x3
182 # CHECK: dup.4s v0, w3
183 # CHECK: dup.2s v0, w3
184 # CHECK: dup.8h v0, w3
185 # CHECK: dup.4h v0, w3
186 # CHECK: dup.16b v0, w3
187 # CHECK: dup.8b v0, w3
199 # CHECK: mov.d v2[1], v15[1]
200 # CHECK: mov.s v2[1], v15[1]
201 # CHECK: mov.h v2[1], v15[1]
202 # CHECK: mov.b v2[1], v15[1]
204 # CHECK: mov.d v2[1], v15[0]
205 # CHECK: mov.s v2[3], v15[2]
206 # CHECK: mov.h v2[7], v15[3]
207 # CHECK: mov.b v2[10], v15[5]
212 # CHECK: and.8b v0, v0, v0
213 # CHECK: and.16b v0, v0, v0
217 # CHECK: bic.8b v0, v0, v0
287 # CHECK: cmeq.8b v0, v0, v0
288 # CHECK: cmge.8b v0, v0, v0
289 # CHECK: cmgt.8b v0, v0, v0
290 # CHECK: cmhi.8b v0, v0, v0
291 # CHECK: cmhs.8b v0, v0, v0
292 # CHECK: cmtst.8b v0, v0, v0
293 # CHECK: fabd.2s v0, v0, v0
294 # CHECK: facge.2s v0, v0, v0
295 # CHECK: facgt.2s v0, v0, v0
296 # CHECK: faddp.2s v0, v0, v0
297 # CHECK: fadd.2s v0, v0, v0
298 # CHECK: fcmeq.2s v0, v0, v0
299 # CHECK: fcmge.2s v0, v0, v0
300 # CHECK: fcmgt.2s v0, v0, v0
301 # CHECK: fdiv.2s v0, v0, v0
302 # CHECK: fmaxnmp.2s v0, v0, v0
303 # CHECK: fmaxnm.2s v0, v0, v0
304 # CHECK: fmaxp.2s v0, v0, v0
305 # CHECK: fmax.2s v0, v0, v0
306 # CHECK: fminnmp.2s v0, v0, v0
307 # CHECK: fminnm.2s v0, v0, v0
308 # CHECK: fminp.2s v0, v0, v0
309 # CHECK: fmin.2s v0, v0, v0
310 # CHECK: fmla.2s v0, v0, v0
311 # CHECK: fmls.2s v0, v0, v0
312 # CHECK: fmulx.2s v0, v0, v0
313 # CHECK: fmul.2s v0, v0, v0
314 # CHECK: frecps.2s v0, v0, v0
315 # CHECK: frsqrts.2s v0, v0, v0
316 # CHECK: fsub.2s v0, v0, v0
317 # CHECK: mla.8b v0, v0, v0
318 # CHECK: mls.8b v0, v0, v0
319 # CHECK: mul.8b v0, v0, v0
320 # CHECK: pmul.8b v0, v0, v0
321 # CHECK: saba.8b v0, v0, v0
322 # CHECK: sabd.8b v0, v0, v0
323 # CHECK: shadd.8b v0, v0, v0
324 # CHECK: shsub.8b v0, v0, v0
325 # CHECK: smaxp.8b v0, v0, v0
326 # CHECK: smax.8b v0, v0, v0
327 # CHECK: sminp.8b v0, v0, v0
328 # CHECK: smin.8b v0, v0, v0
329 # CHECK: sqadd.8b v0, v0, v0
330 # CHECK: sqdmulh.4h v0, v0, v0
331 # CHECK: sqrdmulh.4h v0, v0, v0
332 # CHECK: sqrshl.8b v0, v0, v0
333 # CHECK: sqshl.8b v0, v0, v0
334 # CHECK: sqsub.8b v0, v0, v0
335 # CHECK: srhadd.8b v0, v0, v0
336 # CHECK: srshl.8b v0, v0, v0
337 # CHECK: sshl.8b v0, v0, v0
338 # CHECK: sub.8b v0, v0, v0
339 # CHECK: uaba.8b v0, v0, v0
340 # CHECK: uabd.8b v0, v0, v0
341 # CHECK: uhadd.8b v0, v0, v0
342 # CHECK: uhsub.8b v0, v0, v0
343 # CHECK: umaxp.8b v0, v0, v0
344 # CHECK: umax.8b v0, v0, v0
345 # CHECK: uminp.8b v0, v0, v0
346 # CHECK: umin.8b v0, v0, v0
347 # CHECK: uqadd.8b v0, v0, v0
348 # CHECK: uqrshl.8b v0, v0, v0
349 # CHECK: uqshl.8b v0, v0, v0
350 # CHECK: uqsub.8b v0, v0, v0
351 # CHECK: urhadd.8b v0, v0, v0
352 # CHECK: urshl.8b v0, v0, v0
353 # CHECK: ushl.8b v0, v0, v0
362 # CHECK: bif.8b v0, v0, v0
363 # CHECK: bit.8b v0, v0, v0
364 # CHECK: bsl.8b v0, v0, v0
365 # CHECK: eor.8b v0, v0, v0
366 # CHECK: orn.8b v0, v0, v0
367 # CHECK: orr.8b v0, v0, v1
376 # CHECK: sadalp.4h v0, v0
377 # CHECK: sadalp.8h v0, v0
378 # CHECK: sadalp.2s v0, v0
379 # CHECK: sadalp.4s v0, v0
380 # CHECK: sadalp.1d v0, v0
381 # CHECK: sadalp.2d v0, v0
466 # CHECK: cls.8b v0, v0
467 # CHECK: clz.8b v0, v0
468 # CHECK: cnt.8b v0, v0
469 # CHECK: fabs.2s v0, v0
470 # CHECK: fcvtas.2s v0, v0
471 # CHECK: fcvtau.2s v0, v0
472 # CHECK: fcvtms.2s v0, v0
473 # CHECK: fcvtmu.2s v0, v0
474 # CHECK: fcvtns.2s v0, v0
475 # CHECK: fcvtnu.2s v0, v0
476 # CHECK: fcvtps.2s v0, v0
477 # CHECK: fcvtpu.2s v0, v0
478 # CHECK: fcvtzs.2s v0, v0
479 # CHECK: fcvtzu.2s v0, v0
480 # CHECK: fneg.2s v0, v0
481 # CHECK: frecpe.2s v0, v0
482 # CHECK: frsqrte.2s v0, v0
483 # CHECK: fsqrt.2s v0, v0
484 # CHECK: neg.8b v0, v0
485 # CHECK: mvn.8b v0, v0
486 # CHECK: rbit.8b v0, v0
487 # CHECK: rev16.8b v0, v0
488 # CHECK: rev32.8b v0, v0
489 # CHECK: rev64.8b v0, v0
490 # CHECK: sadalp.4h v0, v0
491 # CHECK: saddlp.4h v0, v0
492 # CHECK: scvtf.2s v0, v0
493 # CHECK: shll.8h v0, v0, #8
494 # CHECK: sqabs.8b v0, v0
495 # CHECK: sqneg.8b v0, v0
496 # CHECK: sqxtn.8b v0, v0
497 # CHECK: sqxtun.8b v0, v0
498 # CHECK: suqadd.8b v0, v0
499 # CHECK: uadalp.4h v0, v0
500 # CHECK: uaddlp.4h v0, v0
501 # CHECK: ucvtf.2s v0, v0
502 # CHECK: uqxtn.8b v0, v0
503 # CHECK: urecpe.2s v0, v0
504 # CHECK: ursqrte.2s v0, v0
505 # CHECK: usqadd.8b v0, v0
506 # CHECK: xtn.8b v0, v0
516 # CHECK: cmeq.8b v0, v0, #0
517 # CHECK: cmeq.16b v0, v0, #0
518 # CHECK: cmeq.4h v0, v0, #0
519 # CHECK: cmeq.8h v0, v0, #0
520 # CHECK: cmeq.2s v0, v0, #0
521 # CHECK: cmeq.4s v0, v0, #0
522 # CHECK: cmeq.2d v0, v0, #0
534 # CHECK: cmge.8b v0, v0, #0
535 # CHECK: cmgt.8b v0, v0, #0
536 # CHECK: cmle.8b v0, v0, #0
537 # CHECK: cmlt.8b v0, v0, #0
538 # CHECK: fcmeq.2s v0, v0, #0
539 # CHECK: fcmge.2s v0, v0, #0
540 # CHECK: fcmgt.2s v0, v0, #0
541 # CHECK: fcmle.2s v0, v0, #0
542 # CHECK: fcmlt.2s v0, v0, #0
555 # CHECK: fcvtl v0.4s, v0.4h
556 # CHECK: fcvtl2 v0.4s, v0.8h
557 # CHECK: fcvtl v0.2d, v0.2s
558 # CHECK: fcvtl2 v0.2d, v0.4s
559 # CHECK: fcvtn v0.4h, v0.4s
560 # CHECK: fcvtn2 v0.8h, v0.4s
561 # CHECK: fcvtn v0.2s, v0.2d
562 # CHECK: fcvtn2 v0.4s, v0.2d
563 # CHECK: fcvtxn v0.2s, v0.2d
564 # CHECK: fcvtxn2 v0.4s, v0.2d
566 #===-------------------------------------------------------------------------===
567 # AdvSIMD modified immediate instructions
568 #===-------------------------------------------------------------------------===
575 # CHECK: bic.2s v0, #0x1
576 # CHECK: bic.2s v0, #0x1, lsl #8
577 # CHECK: bic.2s v0, #0x1, lsl #16
578 # CHECK: bic.2s v0, #0x1, lsl #24
584 # CHECK: bic.4h v0, #0x1
585 # CHECK: bic.4h v0, #0x1
586 # FIXME: bic.4h v0, #0x1, lsl #8
587 # 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0"
594 # CHECK: bic.4s v0, #0x1
595 # CHECK: bic.4s v0, #0x1, lsl #8
596 # CHECK: bic.4s v0, #0x1, lsl #16
597 # CHECK: bic.4s v0, #0x1, lsl #24
602 # CHECK: bic.8h v0, #0x1
603 # FIXME: bic.8h v0, #0x1, lsl #8
604 # "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0"
608 # CHECK: fmov.2d v0, #0.12500000
613 # CHECK: fmov.2s v0, #0.12500000
614 # CHECK: fmov.4s v0, #0.12500000
621 # CHECK: orr.2s v0, #0x1
622 # CHECK: orr.2s v0, #0x1, lsl #8
623 # CHECK: orr.2s v0, #0x1, lsl #16
624 # CHECK: orr.2s v0, #0x1, lsl #24
629 # CHECK: orr.4h v0, #0x1
630 # FIXME: orr.4h v0, #0x1, lsl #8
631 # 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0"
638 # CHECK: orr.4s v0, #0x1
639 # CHECK: orr.4s v0, #0x1, lsl #8
640 # CHECK: orr.4s v0, #0x1, lsl #16
641 # CHECK: orr.4s v0, #0x1, lsl #24
646 # CHECK: orr.8h v0, #0x1
647 # CHECK: orr.8h v0, #0x1, lsl #8
659 # CHECK: ld1.8b { v1 }, [x1]
660 # CHECK: ld1.16b { v2, v3 }, [x2]
661 # CHECK: ld1.4h { v4, v5, v6 }, [x3]
662 # CHECK: ld1.8h { v7, v8, v9, v10 }, [x4]
663 # CHECK: ld1.2s { v12, v13 }, [x0]
664 # CHECK: ld1.4s { v10, v11, v12 }, [x0]
665 # CHECK: ld1.1d { v13, v14 }, [x1]
666 # CHECK: ld1.2d { v15 }, [x2]
667 # CHECK: ld1.b { v0 }[0], [sp]
702 # CHECK: ld1.8b { v1 }, [x2], #8
703 # CHECK: ld1.8b { v1, v2 }, [x2], #16
704 # CHECK: ld1.8b { v1, v2, v3 }, [x2], #24
705 # CHECK: ld1.8b { v1, v2, v3, v4 }, [x2], #32
706 # CHECK: ld1.16b { v2 }, [x2], #16
707 # CHECK: ld1.16b { v2, v3 }, [x2], #32
708 # CHECK: ld1.16b { v2, v3, v4 }, [x2], #48
709 # CHECK: ld1.16b { v2, v3, v4, v5 }, [x2], #64
710 # CHECK: ld1.4h { v4 }, [x3], #8
711 # CHECK: ld1.4h { v4, v5 }, [x3], #16
712 # CHECK: ld1.4h { v4, v5, v6 }, [x3], #24
713 # CHECK: ld1.4h { v4, v5, v6, v7 }, [x3], #32
714 # CHECK: ld1.8h { v7 }, [x4], #16
715 # CHECK: ld1.8h { v7, v8 }, [x4], #32
716 # CHECK: ld1.8h { v7, v8, v9 }, [x4], #48
717 # CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], #64
718 # CHECK: ld1.2s { v12 }, [x0], #8
719 # CHECK: ld1.2s { v12, v13 }, [x0], #16
720 # CHECK: ld1.2s { v12, v13, v14 }, [x0], #24
721 # CHECK: ld1.2s { v12, v13, v14, v15 }, [x0], #32
722 # CHECK: ld1.4s { v10 }, [x0], #16
723 # CHECK: ld1.4s { v10, v11 }, [x0], #32
724 # CHECK: ld1.4s { v10, v11, v12 }, [x0], #48
725 # CHECK: ld1.4s { v10, v11, v12, v13 }, [x0], #64
726 # CHECK: ld1.1d { v13 }, [x1], #8
727 # CHECK: ld1.1d { v13, v14 }, [x1], #16
728 # CHECK: ld1.1d { v13, v14, v15 }, [x1], #24
729 # CHECK: ld1.1d { v13, v14, v15, v16 }, [x1], #32
730 # CHECK: ld1.2d { v15 }, [x2], #16
731 # CHECK: ld1.2d { v15, v16 }, [x2], #32
732 # CHECK: ld1.2d { v15, v16, v17 }, [x2], #48
733 # CHECK: ld1.2d { v15, v16, v17, v18 }, [x2], #64
744 # CHECK: st1.8b { v1 }, [x1]
745 # CHECK: st1.16b { v2, v3 }, [x2]
746 # CHECK: st1.4h { v4, v5, v6 }, [x3]
747 # CHECK: st1.8h { v7, v8, v9, v10 }, [x4]
748 # CHECK: st1.2s { v12, v13 }, [x0]
749 # CHECK: st1.4s { v10, v11, v12 }, [x0]
750 # CHECK: st1.1d { v13, v14 }, [x1]
751 # CHECK: st1.2d { v15 }, [x2]
758 # CHECK: ld1.b { v1 }[2], [x3]
759 # CHECK: ld1.d { v2 }[1], [x4]
760 # CHECK: ld1.h { v3 }[3], [x5]
761 # CHECK: ld1.s { v4 }[2], [x6]
768 # CHECK: ld1.b { v1 }[2], [x3], #1
769 # CHECK: ld1.d { v2 }[1], [x4], #8
770 # CHECK: ld1.h { v3 }[3], [x5], #2
771 # CHECK: ld1.s { v4 }[2], [x6], #4
778 # CHECK: st1.b { v1 }[2], [x3]
779 # CHECK: st1.d { v2 }[1], [x4]
780 # CHECK: st1.h { v3 }[3], [x5]
781 # CHECK: st1.s { v4 }[2], [x6]
788 # CHECK: st1.b { v1 }[2], [x3], #1
789 # CHECK: st1.d { v2 }[1], [x4], #8
790 # CHECK: st1.h { v3 }[3], [x5], #2
791 # CHECK: st1.s { v4 }[2], [x6], #4
798 # CHECK: ld1.b { v1 }[2], [x3], x4
799 # CHECK: ld1.d { v2 }[1], [x4], x5
800 # CHECK: ld1.h { v3 }[3], [x5], x6
801 # CHECK: ld1.s { v4 }[2], [x6], x7
808 # CHECK: st1.b { v1 }[2], [x3], x4
809 # CHECK: st1.d { v2 }[1], [x4], x5
810 # CHECK: st1.h { v3 }[3], [x5], x6
811 # CHECK: st1.s { v4 }[2], [x6], x7
822 # CHECK: ld1.8b { v1 }, [x2], x3
823 # CHECK: ld1.16b { v2, v3 }, [x2], x4
824 # CHECK: ld1.4h { v4, v5, v6 }, [x3], x5
825 # CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], x6
826 # CHECK: ld1.2s { v12, v13 }, [x0], x7
827 # CHECK: ld1.4s { v10, v11, v12 }, [x0], x8
828 # CHECK: ld1.1d { v13, v14 }, [x1], x9
829 # CHECK: ld1.2d { v15 }, [x2], x10
840 # CHECK: st1.8b { v1 }, [x2], x3
841 # CHECK: st1.16b { v2, v3 }, [x2], x4
842 # CHECK: st1.4h { v4, v5, v6 }, [x3], x5
843 # CHECK: st1.8h { v7, v8, v9, v10 }, [x4], x6
844 # CHECK: st1.2s { v12, v13 }, [x0], x7
845 # CHECK: st1.4s { v10, v11, v12 }, [x0], x8
846 # CHECK: st1.1d { v13, v14 }, [x1], x9
847 # CHECK: st1.2d { v15 }, [x2], x10
882 # CHECK: st1.8b { v1 }, [x2], #8
883 # CHECK: st1.8b { v1, v2 }, [x2], #16
884 # CHECK: st1.8b { v1, v2, v3 }, [x2], #24
885 # CHECK: st1.8b { v1, v2, v3, v4 }, [x2], #32
886 # CHECK: st1.16b { v2 }, [x2], #16
887 # CHECK: st1.16b { v2, v3 }, [x2], #32
888 # CHECK: st1.16b { v2, v3, v4 }, [x2], #48
889 # CHECK: st1.16b { v2, v3, v4, v5 }, [x2], #64
890 # CHECK: st1.4h { v4 }, [x3], #8
891 # CHECK: st1.4h { v4, v5 }, [x3], #16
892 # CHECK: st1.4h { v4, v5, v6 }, [x3], #24
893 # CHECK: st1.4h { v4, v5, v6, v7 }, [x3], #32
894 # CHECK: st1.8h { v7 }, [x4], #16
895 # CHECK: st1.8h { v7, v8 }, [x4], #32
896 # CHECK: st1.8h { v7, v8, v9 }, [x4], #48
897 # CHECK: st1.8h { v7, v8, v9, v10 }, [x4], #64
898 # CHECK: st1.2s { v12 }, [x0], #8
899 # CHECK: st1.2s { v12, v13 }, [x0], #16
900 # CHECK: st1.2s { v12, v13, v14 }, [x0], #24
901 # CHECK: st1.2s { v12, v13, v14, v15 }, [x0], #32
902 # CHECK: st1.4s { v10 }, [x0], #16
903 # CHECK: st1.4s { v10, v11 }, [x0], #32
904 # CHECK: st1.4s { v10, v11, v12 }, [x0], #48
905 # CHECK: st1.4s { v10, v11, v12, v13 }, [x0], #64
906 # CHECK: st1.1d { v13 }, [x1], #8
907 # CHECK: st1.1d { v13, v14 }, [x1], #16
908 # CHECK: st1.1d { v13, v14, v15 }, [x1], #24
909 # CHECK: st1.1d { v13, v14, v15, v16 }, [x1], #32
910 # CHECK: st1.2d { v15 }, [x2], #16
911 # CHECK: st1.2d { v15, v16 }, [x2], #32
912 # CHECK: st1.2d { v15, v16, v17 }, [x2], #48
913 # CHECK: st1.2d { v15, v16, v17, v18 }, [x2], #64
924 # CHECK: ld1r.8b { v1 }, [x1]
925 # CHECK: ld1r.8b { v1 }, [x1], x2
926 # CHECK: ld1r.4h { v4 }, [x3]
927 # CHECK: ld1r.4h { v4 }, [x3], x5
928 # CHECK: ld1r.2s { v9 }, [x5]
929 # CHECK: ld1r.2s { v9 }, [x5], x6
930 # CHECK: ld1r.1d { v12 }, [x7]
931 # CHECK: ld1r.1d { v12 }, [x7], x8
938 # CHECK: ld1r.8b { v1 }, [x1], #1
939 # CHECK: ld1r.4h { v1 }, [x1], #2
940 # CHECK: ld1r.2s { v1 }, [x1], #4
941 # CHECK: ld1r.1d { v1 }, [x1], #8
946 # CHECK: ld2.16b { v5, v6 }, [x2]
947 # CHECK: ld2.2s { v10, v11 }, [x0]
952 # CHECK: st2.16b { v5, v6 }, [x2]
953 # CHECK: st2.2s { v10, v11 }, [x0]
960 # CHECK: st2.b { v1, v2 }[2], [x3]
961 # CHECK: st2.d { v2, v3 }[1], [x4]
962 # CHECK: st2.h { v3, v4 }[2], [x6]
963 # CHECK: st2.s { v4, v5 }[3], [x7]
970 # CHECK: st2.b { v1, v2 }[2], [x3], #2
971 # CHECK: st2.d { v2, v3 }[1], [x4], #16
972 # CHECK: st2.h { v3, v4 }[3], [x5], #4
973 # CHECK: st2.s { v4, v5 }[2], [x6], #8
980 # CHECK: ld2.b { v1, v2 }[2], [x3]
981 # CHECK: ld2.d { v2, v3 }[1], [x4]
982 # CHECK: ld2.h { v3, v4 }[2], [x6]
983 # CHECK: ld2.s { v4, v5 }[3], [x7]
990 # CHECK: ld2.b { v1, v2 }[2], [x3], #2
991 # CHECK: ld2.d { v2, v3 }[1], [x4], #16
992 # CHECK: ld2.h { v3, v4 }[3], [x5], #4
993 # CHECK: ld2.s { v4, v5 }[2], [x6], #8
1000 # CHECK: ld2.b { v1, v2 }[2], [x3], x4
1001 # CHECK: ld2.d { v2, v3 }[1], [x4], x6
1002 # CHECK: ld2.h { v3, v4 }[3], [x5], x8
1003 # CHECK: ld2.s { v4, v5 }[2], [x6], x10
1010 # CHECK: st2.b { v1, v2 }[2], [x3], x4
1011 # CHECK: st2.d { v2, v3 }[1], [x4], x6
1012 # CHECK: st2.h { v3, v4 }[3], [x5], x8
1013 # CHECK: st2.s { v4, v5 }[2], [x6], x10
1018 # CHECK: ld2.4h { v4, v5 }, [x3], x5
1019 # CHECK: ld2.2s { v12, v13 }, [x0], x7
1029 # CHECK: ld2.8b { v0, v1 }, [x0], #16
1030 # CHECK: ld2.16b { v0, v1 }, [x0], #32
1031 # CHECK: ld2.4h { v0, v1 }, [x0], #16
1032 # CHECK: ld2.8h { v0, v1 }, [x0], #32
1033 # CHECK: ld2.2s { v0, v1 }, [x0], #16
1034 # CHECK: ld2.4s { v0, v1 }, [x0], #32
1035 # CHECK: ld2.2d { v0, v1 }, [x0], #32
1040 # CHECK: st2.4h { v4, v5 }, [x3], x5
1041 # CHECK: st2.2s { v12, v13 }, [x0], x7
1051 # CHECK: st2.8b { v0, v1 }, [x0], #16
1052 # CHECK: st2.16b { v0, v1 }, [x0], #32
1053 # CHECK: st2.4h { v0, v1 }, [x0], #16
1054 # CHECK: st2.8h { v0, v1 }, [x0], #32
1055 # CHECK: st2.2s { v0, v1 }, [x0], #16
1056 # CHECK: st2.4s { v0, v1 }, [x0], #32
1057 # CHECK: st2.2d { v0, v1 }, [x0], #32
1074 # CHECK: ld2r.8b { v1, v2 }, [x1]
1075 # CHECK: ld2r.8b { v1, v2 }, [x1], x2
1076 # CHECK: ld2r.16b { v1, v2 }, [x1]
1077 # CHECK: ld2r.16b { v1, v2 }, [x1], x2
1078 # CHECK: ld2r.4h { v1, v2 }, [x1]
1079 # CHECK: ld2r.4h { v1, v2 }, [x1], x2
1080 # CHECK: ld2r.8h { v1, v2 }, [x1]
1081 # CHECK: ld2r.8h { v1, v2 }, [x1], x2
1082 # CHECK: ld2r.2s { v1, v2 }, [x1]
1083 # CHECK: ld2r.2s { v1, v2 }, [x1], x2
1084 # CHECK: ld2r.2d { v1, v2 }, [x1]
1085 # CHECK: ld2r.2d { v1, v2 }, [x1], x2
1086 # CHECK: ld2r.1d { v1, v2 }, [x1]
1087 # CHECK: ld2r.1d { v1, v2 }, [x1], x2
1097 # CHECK: ld2r.8b { v1, v2 }, [x1], #2
1098 # CHECK: ld2r.16b { v1, v2 }, [x1], #2
1099 # CHECK: ld2r.4h { v1, v2 }, [x1], #4
1100 # CHECK: ld2r.8h { v1, v2 }, [x1], #4
1101 # CHECK: ld2r.2s { v1, v2 }, [x1], #8
1102 # CHECK: ld2r.2d { v1, v2 }, [x1], #16
1103 # CHECK: ld2r.1d { v1, v2 }, [x1], #16
1109 # CHECK: ld3.8b { v1, v2, v3 }, [x1]
1110 # CHECK: ld3.16b { v5, v6, v7 }, [x2]
1111 # CHECK: ld3.2s { v10, v11, v12 }, [x0]
1117 # CHECK: st3.8b { v1, v2, v3 }, [x1]
1118 # CHECK: st3.16b { v5, v6, v7 }, [x2]
1119 # CHECK: st3.2s { v10, v11, v12 }, [x0]
1126 # CHECK: ld3.b { v1, v2, v3 }[2], [x3], x4
1127 # CHECK: ld3.d { v2, v3, v4 }[1], [x4], x5
1128 # CHECK: ld3.h { v3, v4, v5 }[3], [x5], x6
1129 # CHECK: ld3.s { v4, v5, v6 }[2], [x6], x7
1136 # CHECK: st3.b { v1, v2, v3 }[2], [x3], x4
1137 # CHECK: st3.d { v2, v3, v4 }[1], [x4], x5
1138 # CHECK: st3.h { v3, v4, v5 }[3], [x5], x6
1139 # CHECK: st3.s { v4, v5, v6 }[2], [x6], x7
1146 # CHECK: st3.b { v1, v2, v3 }[2], [x3], #3
1147 # CHECK: st3.d { v2, v3, v4 }[1], [x4], #24
1148 # CHECK: st3.h { v3, v4, v5 }[3], [x5], #6
1149 # CHECK: st3.s { v4, v5, v6 }[2], [x6], #12
1159 # CHECK: ld3.8b { v1, v2, v3 }, [x2], x3
1160 # CHECK: ld3.16b { v2, v3, v4 }, [x2], x4
1161 # CHECK: ld3.4h { v4, v5, v6 }, [x3], x5
1162 # CHECK: ld3.8h { v7, v8, v9 }, [x4], x6
1163 # CHECK: ld3.2s { v12, v13, v14 }, [x0], x7
1164 # CHECK: ld3.4s { v10, v11, v12 }, [x0], x8
1165 # CHECK: ld3.2d { v15, v16, v17 }, [x2], x10
1175 # CHECK: ld3.8b { v0, v1, v2 }, [x0], #24
1176 # CHECK: ld3.16b { v0, v1, v2 }, [x0], #48
1177 # CHECK: ld3.4h { v0, v1, v2 }, [x0], #24
1178 # CHECK: ld3.8h { v0, v1, v2 }, [x0], #48
1179 # CHECK: ld3.2s { v0, v1, v2 }, [x0], #24
1180 # CHECK: ld3.4s { v0, v1, v2 }, [x0], #48
1181 # CHECK: ld3.2d { v0, v1, v2 }, [x0], #48
1191 # CHECK: st3.8b { v1, v2, v3 }, [x2], x3
1192 # CHECK: st3.16b { v2, v3, v4 }, [x2], x4
1193 # CHECK: st3.4h { v4, v5, v6 }, [x3], x5
1194 # CHECK: st3.8h { v7, v8, v9 }, [x4], x6
1195 # CHECK: st3.2s { v12, v13, v14 }, [x0], x7
1196 # CHECK: st3.4s { v10, v11, v12 }, [x0], x8
1197 # CHECK: st3.2d { v15, v16, v17 }, [x2], x10
1207 # CHECK: st3.8b { v0, v1, v2 }, [x0], #24
1208 # CHECK: st3.16b { v0, v1, v2 }, [x0], #48
1209 # CHECK: st3.4h { v0, v1, v2 }, [x0], #24
1210 # CHECK: st3.8h { v0, v1, v2 }, [x0], #48
1211 # CHECK: st3.2s { v0, v1, v2 }, [x0], #24
1212 # CHECK: st3.4s { v0, v1, v2 }, [x0], #48
1213 # CHECK: st3.2d { v0, v1, v2 }, [x0], #48
1220 # CHECK: ld3.b { v1, v2, v3 }[2], [x3]
1221 # CHECK: ld3.d { v2, v3, v4 }[1], [x4]
1222 # CHECK: ld3.h { v3, v4, v5 }[2], [x6]
1223 # CHECK: ld3.s { v4, v5, v6 }[3], [x7]
1230 # CHECK: ld3.b { v1, v2, v3 }[2], [x3], #3
1231 # CHECK: ld3.d { v2, v3, v4 }[1], [x4], #24
1232 # CHECK: ld3.h { v3, v4, v5 }[3], [x5], #6
1233 # CHECK: ld3.s { v4, v5, v6 }[2], [x6], #12
1240 # CHECK: st3.b { v1, v2, v3 }[2], [x3]
1241 # CHECK: st3.d { v2, v3, v4 }[1], [x4]
1242 # CHECK: st3.h { v3, v4, v5 }[2], [x6]
1243 # CHECK: st3.s { v4, v5, v6 }[3], [x7]
1260 # CHECK: ld3r.8b { v1, v2, v3 }, [x1]
1261 # CHECK: ld3r.8b { v1, v2, v3 }, [x1], x2
1262 # CHECK: ld3r.16b { v1, v2, v3 }, [x1]
1263 # CHECK: ld3r.16b { v1, v2, v3 }, [x1], x2
1264 # CHECK: ld3r.4h { v1, v2, v3 }, [x1]
1265 # CHECK: ld3r.4h { v1, v2, v3 }, [x1], x2
1266 # CHECK: ld3r.8h { v1, v2, v3 }, [x1]
1267 # CHECK: ld3r.8h { v1, v2, v3 }, [x1], x2
1268 # CHECK: ld3r.2s { v1, v2, v3 }, [x1]
1269 # CHECK: ld3r.2s { v1, v2, v3 }, [x1], x2
1270 # CHECK: ld3r.2d { v1, v2, v3 }, [x1]
1271 # CHECK: ld3r.2d { v1, v2, v3 }, [x1], x2
1272 # CHECK: ld3r.1d { v1, v2, v3 }, [x1]
1273 # CHECK: ld3r.1d { v1, v2, v3 }, [x1], x2
1283 # CHECK: ld3r.8b { v1, v2, v3 }, [x1], #3
1284 # CHECK: ld3r.16b { v1, v2, v3 }, [x1], #3
1285 # CHECK: ld3r.4h { v1, v2, v3 }, [x1], #6
1286 # CHECK: ld3r.8h { v1, v2, v3 }, [x1], #6
1287 # CHECK: ld3r.2s { v1, v2, v3 }, [x1], #12
1288 # CHECK: ld3r.2d { v1, v2, v3 }, [x1], #24
1289 # CHECK: ld3r.1d { v1, v2, v3 }, [x1], #24
1295 # CHECK: ld4.8b { v1, v2, v3, v4 }, [x1]
1296 # CHECK: ld4.16b { v5, v6, v7, v8 }, [x2]
1297 # CHECK: ld4.2s { v10, v11, v12, v13 }, [x0]
1303 # CHECK: st4.8b { v1, v2, v3, v4 }, [x1]
1304 # CHECK: st4.16b { v5, v6, v7, v8 }, [x2]
1305 # CHECK: st4.2s { v10, v11, v12, v13 }, [x0]
1312 # CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], x4
1313 # CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], x5
1314 # CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], x6
1315 # CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], x7
1322 # CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], #4
1323 # CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], #32
1324 # CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], #8
1325 # CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], #16
1332 # CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], x4
1333 # CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], x5
1334 # CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], x6
1335 # CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], x7
1342 # CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], #4
1343 # CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], #32
1344 # CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], #8
1345 # CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], #16
1355 # CHECK: ld4.8b { v1, v2, v3, v4 }, [x2], x3
1356 # CHECK: ld4.16b { v2, v3, v4, v5 }, [x2], x4
1357 # CHECK: ld4.4h { v4, v5, v6, v7 }, [x3], x5
1358 # CHECK: ld4.8h { v7, v8, v9, v10 }, [x4], x6
1359 # CHECK: ld4.2s { v12, v13, v14, v15 }, [x0], x7
1360 # CHECK: ld4.4s { v10, v11, v12, v13 }, [x0], x8
1361 # CHECK: ld4.2d { v15, v16, v17, v18 }, [x2], x10
1371 # CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], #32
1372 # CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], #64
1373 # CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], #32
1374 # CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], #64
1375 # CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32
1376 # CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64
1377 # CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64
1387 # CHECK: st4.8b { v0, v1, v2, v3 }, [x0], #32
1388 # CHECK: st4.16b { v0, v1, v2, v3 }, [x0], #64
1389 # CHECK: st4.4h { v0, v1, v2, v3 }, [x0], #32
1390 # CHECK: st4.8h { v0, v1, v2, v3 }, [x0], #64
1391 # CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32
1392 # CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64
1393 # CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64
1403 # CHECK: st4.8b { v1, v2, v3, v4 }, [x2], x3
1404 # CHECK: st4.16b { v2, v3, v4, v5 }, [x2], x4
1405 # CHECK: st4.4h { v4, v5, v6, v7 }, [x3], x5
1406 # CHECK: st4.8h { v7, v8, v9, v10 }, [x4], x6
1407 # CHECK: st4.2s { v12, v13, v14, v15 }, [x0], x7
1408 # CHECK: st4.4s { v10, v11, v12, v13 }, [x0], x8
1409 # CHECK: st4.2d { v15, v16, v17, v18 }, [x2], x10
1416 # CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3]
1417 # CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4]
1418 # CHECK: ld4.h { v3, v4, v5, v6 }[2], [x6]
1419 # CHECK: ld4.s { v4, v5, v6, v7 }[3], [x7]
1426 # CHECK: st4.b { v1, v2, v3, v4 }[2], [x3]
1427 # CHECK: st4.d { v2, v3, v4, v5 }[1], [x4]
1428 # CHECK: st4.h { v3, v4, v5, v6 }[2], [x6]
1429 # CHECK: st4.s { v4, v5, v6, v7 }[3], [x7]
1446 # CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1]
1447 # CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], x2
1448 # CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1]
1449 # CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], x2
1450 # CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1]
1451 # CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], x2
1452 # CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1]
1453 # CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], x2
1454 # CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1]
1455 # CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], x2
1456 # CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1]
1457 # CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], x2
1458 # CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1]
1459 # CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], x2
1469 # CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], #4
1470 # CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], #4
1471 # CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], #8
1472 # CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], #8
1473 # CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], #16
1474 # CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], #32
1475 # CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], #32
1482 # CHECK: movi d0, #0x000000000000ff
1483 # CHECK: movi.2d v0, #0x000000000000ff
1484 # CHECK: movi.8b v0, #0x1
1485 # CHECK: movi.16b v0, #0x1
1492 # CHECK: movi.2s v0, #0x1
1493 # CHECK: movi.2s v0, #0x1, lsl #8
1494 # CHECK: movi.2s v0, #0x1, lsl #16
1495 # CHECK: movi.2s v0, #0x1, lsl #24
1502 # CHECK: movi.4s v0, #0x1
1503 # CHECK: movi.4s v0, #0x1, lsl #8
1504 # CHECK: movi.4s v0, #0x1, lsl #16
1505 # CHECK: movi.4s v0, #0x1, lsl #24
1510 # CHECK: movi.4h v0, #0x1
1511 # CHECK: movi.4h v0, #0x1, lsl #8
1516 # CHECK: movi.8h v0, #0x1
1517 # CHECK: movi.8h v0, #0x1, lsl #8
1524 # CHECK: mvni.2s v0, #0x1
1525 # CHECK: mvni.2s v0, #0x1, lsl #8
1526 # CHECK: mvni.2s v0, #0x1, lsl #16
1527 # CHECK: mvni.2s v0, #0x1, lsl #24
1534 # CHECK: mvni.4s v0, #0x1
1535 # CHECK: mvni.4s v0, #0x1, lsl #8
1536 # CHECK: mvni.4s v0, #0x1, lsl #16
1537 # CHECK: mvni.4s v0, #0x1, lsl #24
1542 # CHECK: mvni.4h v0, #0x1
1543 # CHECK: mvni.4h v0, #0x1, lsl #8
1548 # CHECK: mvni.8h v0, #0x1
1549 # CHECK: mvni.8h v0, #0x1, lsl #8
1556 # CHECK: mvni.2s v0, #0x1, msl #8
1557 # CHECK: mvni.2s v0, #0x1, msl #16
1558 # CHECK: mvni.4s v0, #0x1, msl #8
1559 # CHECK: mvni.4s v0, #0x1, msl #16
1569 # CHECK: frinta.2s v0, v0
1570 # CHECK: frintx.2s v0, v0
1571 # CHECK: frinti.2s v0, v0
1572 # CHECK: frintm.2s v0, v0
1573 # CHECK: frintn.2s v0, v0
1574 # CHECK: frintp.2s v0, v0
1575 # CHECK: frintz.2s v0, v0
1577 #===-------------------------------------------------------------------------===
1578 # AdvSIMD scalar x index instructions
1579 #===-------------------------------------------------------------------------===
1599 # CHECK: fmla.s s0, s0, v0[3]
1600 # CHECK: fmla.d d0, d0, v0[1]
1601 # CHECK: fmls.s s0, s0, v0[3]
1602 # CHECK: fmls.d d0, d0, v0[1]
1603 # CHECK: fmulx.s s0, s0, v0[3]
1604 # CHECK: fmulx.d d0, d0, v0[1]
1605 # CHECK: fmul.s s0, s0, v0[3]
1606 # CHECK: fmul.d d0, d0, v0[1]
1607 # CHECK: sqdmlal.h s0, h0, v0[7]
1608 # CHECK: sqdmlal.s d0, s0, v0[3]
1609 # CHECK: sqdmlsl.h s0, h0, v0[7]
1610 # CHECK: sqdmulh.h h0, h0, v0[7]
1611 # CHECK: sqdmulh.s s0, s0, v0[3]
1612 # CHECK: sqdmull.h s0, h0, v0[7]
1613 # CHECK: sqdmull.s d0, s0, v0[3]
1614 # CHECK: sqrdmulh.h h0, h0, v0[7]
1615 # CHECK: sqrdmulh.s s0, s0, v0[3]
1617 #===-------------------------------------------------------------------------===
1618 # AdvSIMD vector x index instructions
1619 #===-------------------------------------------------------------------------===
1690 # CHECK: fmla.2s v0, v0, v0[0]
1691 # CHECK: fmla.4s v0, v0, v0[1]
1692 # CHECK: fmla.2d v0, v0, v0[1]
1693 # CHECK: fmls.2s v0, v0, v0[0]
1694 # CHECK: fmls.4s v0, v0, v0[1]
1695 # CHECK: fmls.2d v0, v0, v0[1]
1696 # CHECK: fmulx.2s v0, v0, v0[0]
1697 # CHECK: fmulx.4s v0, v0, v0[1]
1698 # CHECK: fmulx.2d v0, v0, v0[1]
1699 # CHECK: fmul.2s v0, v0, v0[0]
1700 # CHECK: fmul.4s v0, v0, v0[1]
1701 # CHECK: fmul.2d v0, v0, v0[1]
1702 # CHECK: mla.4h v0, v0, v0[0]
1703 # CHECK: mla.8h v0, v0, v0[1]
1704 # CHECK: mla.2s v0, v0, v0[2]
1705 # CHECK: mla.4s v0, v0, v0[3]
1706 # CHECK: mls.4h v0, v0, v0[0]
1707 # CHECK: mls.8h v0, v0, v0[1]
1708 # CHECK: mls.2s v0, v0, v0[2]
1709 # CHECK: mls.4s v0, v0, v0[3]
1710 # CHECK: mul.4h v0, v0, v0[0]
1711 # CHECK: mul.8h v0, v0, v0[1]
1712 # CHECK: mul.2s v0, v0, v0[2]
1713 # CHECK: mul.4s v0, v0, v0[3]
1714 # CHECK: smlal.4s v0, v0, v0[0]
1715 # CHECK: smlal2.4s v0, v0, v0[1]
1716 # CHECK: smlal.2d v0, v0, v0[2]
1717 # CHECK: smlal2.2d v0, v0, v0[3]
1718 # CHECK: smlsl.4s v0, v0, v0[0]
1719 # CHECK: smlsl2.4s v0, v0, v0[1]
1720 # CHECK: smlsl.2d v0, v0, v0[2]
1721 # CHECK: smlsl2.2d v0, v0, v0[3]
1722 # CHECK: smull.4s v0, v0, v0[0]
1723 # CHECK: smull2.4s v0, v0, v0[1]
1724 # CHECK: smull.2d v0, v0, v0[2]
1725 # CHECK: smull2.2d v0, v0, v0[3]
1726 # CHECK: sqdmlal.4s v0, v0, v0[0]
1727 # CHECK: sqdmlal2.4s v0, v0, v0[1]
1728 # CHECK: sqdmlal.2d v0, v0, v0[2]
1729 # CHECK: sqdmlal2.2d v0, v0, v0[3]
1730 # CHECK: sqdmlsl.4s v0, v0, v0[0]
1731 # CHECK: sqdmlsl2.4s v0, v0, v0[1]
1732 # CHECK: sqdmlsl.2d v0, v0, v0[2]
1733 # CHECK: sqdmlsl2.2d v0, v0, v0[3]
1734 # CHECK: sqdmulh.4h v0, v0, v0[0]
1735 # CHECK: sqdmulh.8h v0, v0, v0[1]
1736 # CHECK: sqdmulh.2s v0, v0, v0[2]
1737 # CHECK: sqdmulh.4s v0, v0, v0[3]
1738 # CHECK: sqdmull.4s v0, v0, v0[0]
1739 # CHECK: sqdmull2.4s v0, v0, v0[1]
1740 # CHECK: sqdmull.2d v0, v0, v0[2]
1741 # CHECK: sqdmull2.2d v0, v0, v0[3]
1742 # CHECK: sqrdmulh.4h v0, v0, v0[0]
1743 # CHECK: sqrdmulh.8h v0, v0, v0[1]
1744 # CHECK: sqrdmulh.2s v0, v0, v0[2]
1745 # CHECK: sqrdmulh.4s v0, v0, v0[3]
1746 # CHECK: umlal.4s v0, v0, v0[0]
1747 # CHECK: umlal2.4s v0, v0, v0[1]
1748 # CHECK: umlal.2d v0, v0, v0[2]
1749 # CHECK: umlal2.2d v0, v0, v0[3]
1750 # CHECK: umlsl.4s v0, v0, v0[0]
1751 # CHECK: umlsl2.4s v0, v0, v0[1]
1752 # CHECK: umlsl.2d v0, v0, v0[2]
1753 # CHECK: umlsl2.2d v0, v0, v0[3]
1754 # CHECK: umull.4s v0, v0, v0[0]
1755 # CHECK: umull2.4s v0, v0, v0[1]
1756 # CHECK: umull.2d v0, v0, v0[2]
1757 # CHECK: umull2.2d v0, v0, v0[3]
1760 #===-------------------------------------------------------------------------===
1761 # AdvSIMD scalar + shift instructions
1762 #===-------------------------------------------------------------------------===
1807 # CHECK: shl d0, d0, #0x1
1808 # CHECK: sli d0, d0, #0x1
1809 # CHECK: sqrshrn b0, h0, #0x7
1810 # CHECK: sqrshrn h0, s0, #0xe
1811 # CHECK: sqrshrn s0, d0, #0x1d
1812 # CHECK: sqrshrun b0, h0, #0x7
1813 # CHECK: sqrshrun h0, s0, #0xe
1814 # CHECK: sqrshrun s0, d0, #0x1d
1815 # CHECK: sqshlu b0, b0, #0x1
1816 # CHECK: sqshlu h0, h0, #0x2
1817 # CHECK: sqshlu s0, s0, #0x3
1818 # CHECK: sqshlu d0, d0, #0x4
1819 # CHECK: sqshl b0, b0, #0x1
1820 # CHECK: sqshl h0, h0, #0x2
1821 # CHECK: sqshl s0, s0, #0x3
1822 # CHECK: sqshl d0, d0, #0x4
1823 # CHECK: sqshrn b0, h0, #0x7
1824 # CHECK: sqshrn h0, s0, #0xe
1825 # CHECK: sqshrn s0, d0, #0x1d
1826 # CHECK: sqshrun b0, h0, #0x7
1827 # CHECK: sqshrun h0, s0, #0xe
1828 # CHECK: sqshrun s0, d0, #0x1d
1829 # CHECK: sri d0, d0, #0x3f
1830 # CHECK: srshr d0, d0, #0x3f
1831 # CHECK: srsra d0, d0, #0x3f
1832 # CHECK: sshr d0, d0, #0x3f
1833 # CHECK: ucvtf s0, s0, #0x1f
1834 # CHECK: ucvtf d0, d0, #0x3e
1835 # CHECK: uqrshrn b0, h0, #0x7
1836 # CHECK: uqrshrn h0, s0, #0xe
1837 # CHECK: uqrshrn s0, d0, #0x1d
1838 # CHECK: uqshl b0, b0, #0x1
1839 # CHECK: uqshl h0, h0, #0x2
1840 # CHECK: uqshl s0, s0, #0x3
1841 # CHECK: uqshl d0, d0, #0x4
1842 # CHECK: uqshrn b0, h0, #0x7
1843 # CHECK: uqshrn h0, s0, #0xe
1844 # CHECK: uqshrn s0, d0, #0x1d
1845 # CHECK: urshr d0, d0, #0x3f
1846 # CHECK: ursra d0, d0, #0x3f
1847 # CHECK: ushr d0, d0, #0x3f
1848 # CHECK: usra d0, d0, #0x3f
1850 #===-------------------------------------------------------------------------===
1851 # AdvSIMD vector + shift instructions
1852 #===-------------------------------------------------------------------------===
2026 # CHECK: fcvtzs.2s v0, v0, #0x1f
2027 # CHECK: fcvtzs.4s v0, v0, #0x1e
2028 # CHECK: fcvtzs.2d v0, v0, #0x3d
2029 # CHECK: fcvtzu.2s v0, v0, #0x1f
2030 # CHECK: fcvtzu.4s v0, v0, #0x1e
2031 # CHECK: fcvtzu.2d v0, v0, #0x3d
2032 # CHECK: rshrn.8b v0, v0, #0x7
2033 # CHECK: rshrn2.16b v0, v0, #0x6
2034 # CHECK: rshrn.4h v0, v0, #0xd
2035 # CHECK: rshrn2.8h v0, v0, #0xc
2036 # CHECK: rshrn.2s v0, v0, #0x1b
2037 # CHECK: rshrn2.4s v0, v0, #0x1a
2038 # CHECK: scvtf.2s v0, v0, #0x1f
2039 # CHECK: scvtf.4s v0, v0, #0x1e
2040 # CHECK: scvtf.2d v0, v0, #0x3d
2041 # CHECK: shl.8b v0, v0, #0x1
2042 # CHECK: shl.16b v0, v0, #0x2
2043 # CHECK: shl.4h v0, v0, #0x3
2044 # CHECK: shl.8h v0, v0, #0x4
2045 # CHECK: shl.2s v0, v0, #0x5
2046 # CHECK: shl.4s v0, v0, #0x6
2047 # CHECK: shl.2d v0, v0, #0x7
2048 # CHECK: shrn.8b v0, v0, #0x7
2049 # CHECK: shrn2.16b v0, v0, #0x6
2050 # CHECK: shrn.4h v0, v0, #0xd
2051 # CHECK: shrn2.8h v0, v0, #0xc
2052 # CHECK: shrn.2s v0, v0, #0x1b
2053 # CHECK: shrn2.4s v0, v0, #0x1a
2054 # CHECK: sli.8b v0, v0, #0x1
2055 # CHECK: sli.16b v0, v0, #0x2
2056 # CHECK: sli.4h v0, v0, #0x3
2057 # CHECK: sli.8h v0, v0, #0x4
2058 # CHECK: sli.2s v0, v0, #0x5
2059 # CHECK: sli.4s v0, v0, #0x6
2060 # CHECK: sli.2d v0, v0, #0x7
2061 # CHECK: sqrshrn.8b v0, v0, #0x7
2062 # CHECK: sqrshrn2.16b v0, v0, #0x6
2063 # CHECK: sqrshrn.4h v0, v0, #0xd
2064 # CHECK: sqrshrn2.8h v0, v0, #0xc
2065 # CHECK: sqrshrn.2s v0, v0, #0x1b
2066 # CHECK: sqrshrn2.4s v0, v0, #0x1a
2067 # CHECK: sqrshrun.8b v0, v0, #0x7
2068 # CHECK: sqrshrun2.16b v0, v0, #0x6
2069 # CHECK: sqrshrun.4h v0, v0, #0xd
2070 # CHECK: sqrshrun2.8h v0, v0, #0xc
2071 # CHECK: sqrshrun.2s v0, v0, #0x1b
2072 # CHECK: sqrshrun2.4s v0, v0, #0x1a
2073 # CHECK: sqshlu.8b v0, v0, #0x1
2074 # CHECK: sqshlu.16b v0, v0, #0x2
2075 # CHECK: sqshlu.4h v0, v0, #0x3
2076 # CHECK: sqshlu.8h v0, v0, #0x4
2077 # CHECK: sqshlu.2s v0, v0, #0x5
2078 # CHECK: sqshlu.4s v0, v0, #0x6
2079 # CHECK: sqshlu.2d v0, v0, #0x7
2080 # CHECK: sqshl.8b v0, v0, #0x1
2081 # CHECK: sqshl.16b v0, v0, #0x2
2082 # CHECK: sqshl.4h v0, v0, #0x3
2083 # CHECK: sqshl.8h v0, v0, #0x4
2084 # CHECK: sqshl.2s v0, v0, #0x5
2085 # CHECK: sqshl.4s v0, v0, #0x6
2086 # CHECK: sqshl.2d v0, v0, #0x7
2087 # CHECK: sqshrn.8b v0, v0, #0x7
2088 # CHECK: sqshrn2.16b v0, v0, #0x6
2089 # CHECK: sqshrn.4h v0, v0, #0xd
2090 # CHECK: sqshrn2.8h v0, v0, #0xc
2091 # CHECK: sqshrn.2s v0, v0, #0x1b
2092 # CHECK: sqshrn2.4s v0, v0, #0x1a
2093 # CHECK: sqshrun.8b v0, v0, #0x7
2094 # CHECK: sqshrun2.16b v0, v0, #0x6
2095 # CHECK: sqshrun.4h v0, v0, #0xd
2096 # CHECK: sqshrun2.8h v0, v0, #0xc
2097 # CHECK: sqshrun.2s v0, v0, #0x1b
2098 # CHECK: sqshrun2.4s v0, v0, #0x1a
2099 # CHECK: sri.8b v0, v0, #0x7
2100 # CHECK: sri.16b v0, v0, #0x6
2101 # CHECK: sri.4h v0, v0, #0xd
2102 # CHECK: sri.8h v0, v0, #0xc
2103 # CHECK: sri.2s v0, v0, #0x1b
2104 # CHECK: sri.4s v0, v0, #0x1a
2105 # CHECK: sri.2d v0, v0, #0x39
2106 # CHECK: srshr.8b v0, v0, #0x7
2107 # CHECK: srshr.16b v0, v0, #0x6
2108 # CHECK: srshr.4h v0, v0, #0xd
2109 # CHECK: srshr.8h v0, v0, #0xc
2110 # CHECK: srshr.2s v0, v0, #0x1b
2111 # CHECK: srshr.4s v0, v0, #0x1a
2112 # CHECK: srshr.2d v0, v0, #0x39
2113 # CHECK: srsra.8b v0, v0, #0x7
2114 # CHECK: srsra.16b v0, v0, #0x6
2115 # CHECK: srsra.4h v0, v0, #0xd
2116 # CHECK: srsra.8h v0, v0, #0xc
2117 # CHECK: srsra.2s v0, v0, #0x1b
2118 # CHECK: srsra.4s v0, v0, #0x1a
2119 # CHECK: srsra.2d v0, v0, #0x39
2120 # CHECK: sshll.8h v0, v0, #0x1
2121 # CHECK: sshll2.8h v0, v0, #0x2
2122 # CHECK: sshll.4s v0, v0, #0x3
2123 # CHECK: sshll2.4s v0, v0, #0x4
2124 # CHECK: sshll.2d v0, v0, #0x5
2125 # CHECK: sshll2.2d v0, v0, #0x6
2126 # CHECK: sshr.8b v0, v0, #0x7
2127 # CHECK: sshr.16b v0, v0, #0x6
2128 # CHECK: sshr.4h v0, v0, #0xd
2129 # CHECK: sshr.8h v0, v0, #0xc
2130 # CHECK: sshr.2s v0, v0, #0x1b
2131 # CHECK: sshr.4s v0, v0, #0x1a
2132 # CHECK: sshr.2d v0, v0, #0x39
2133 # CHECK: sshr.8b v0, v0, #0x7
2134 # CHECK: ssra.16b v0, v0, #0x6
2135 # CHECK: ssra.4h v0, v0, #0xd
2136 # CHECK: ssra.8h v0, v0, #0xc
2137 # CHECK: ssra.2s v0, v0, #0x1b
2138 # CHECK: ssra.4s v0, v0, #0x1a
2139 # CHECK: ssra.2d v0, v0, #0x39
2140 # CHECK: ssra d0, d0, #0x40
2141 # CHECK: ucvtf.2s v0, v0, #0x1f
2142 # CHECK: ucvtf.4s v0, v0, #0x1e
2143 # CHECK: ucvtf.2d v0, v0, #0x3d
2144 # CHECK: uqrshrn.8b v0, v0, #0x7
2145 # CHECK: uqrshrn2.16b v0, v0, #0x6
2146 # CHECK: uqrshrn.4h v0, v0, #0xd
2147 # CHECK: uqrshrn2.8h v0, v0, #0xc
2148 # CHECK: uqrshrn.2s v0, v0, #0x1b
2149 # CHECK: uqrshrn2.4s v0, v0, #0x1a
2150 # CHECK: uqshl.8b v0, v0, #0x1
2151 # CHECK: uqshl.16b v0, v0, #0x2
2152 # CHECK: uqshl.4h v0, v0, #0x3
2153 # CHECK: uqshl.8h v0, v0, #0x4
2154 # CHECK: uqshl.2s v0, v0, #0x5
2155 # CHECK: uqshl.4s v0, v0, #0x6
2156 # CHECK: uqshl.2d v0, v0, #0x7
2157 # CHECK: uqshrn.8b v0, v0, #0x7
2158 # CHECK: uqshrn2.16b v0, v0, #0x6
2159 # CHECK: uqshrn.4h v0, v0, #0xd
2160 # CHECK: uqshrn2.8h v0, v0, #0xc
2161 # CHECK: uqshrn.2s v0, v0, #0x1b
2162 # CHECK: uqshrn2.4s v0, v0, #0x1a
2163 # CHECK: urshr.8b v0, v0, #0x7
2164 # CHECK: urshr.16b v0, v0, #0x6
2165 # CHECK: urshr.4h v0, v0, #0xd
2166 # CHECK: urshr.8h v0, v0, #0xc
2167 # CHECK: urshr.2s v0, v0, #0x1b
2168 # CHECK: urshr.4s v0, v0, #0x1a
2169 # CHECK: urshr.2d v0, v0, #0x39
2170 # CHECK: ursra.8b v0, v0, #0x7
2171 # CHECK: ursra.16b v0, v0, #0x6
2172 # CHECK: ursra.4h v0, v0, #0xd
2173 # CHECK: ursra.8h v0, v0, #0xc
2174 # CHECK: ursra.2s v0, v0, #0x1b
2175 # CHECK: ursra.4s v0, v0, #0x1a
2176 # CHECK: ursra.2d v0, v0, #0x39
2177 # CHECK: ushll.8h v0, v0, #0x1
2178 # CHECK: ushll2.8h v0, v0, #0x2
2179 # CHECK: ushll.4s v0, v0, #0x3
2180 # CHECK: ushll2.4s v0, v0, #0x4
2181 # CHECK: ushll.2d v0, v0, #0x5
2182 # CHECK: ushll2.2d v0, v0, #0x6
2183 # CHECK: ushr.8b v0, v0, #0x7
2184 # CHECK: ushr.16b v0, v0, #0x6
2185 # CHECK: ushr.4h v0, v0, #0xd
2186 # CHECK: ushr.8h v0, v0, #0xc
2187 # CHECK: ushr.2s v0, v0, #0x1b
2188 # CHECK: ushr.4s v0, v0, #0x1a
2189 # CHECK: ushr.2d v0, v0, #0x39
2190 # CHECK: usra.8b v0, v0, #0x7
2191 # CHECK: usra.16b v0, v0, #0x6
2192 # CHECK: usra.4h v0, v0, #0xd
2193 # CHECK: usra.8h v0, v0, #0xc
2194 # CHECK: usra.2s v0, v0, #0x1b
2195 # CHECK: usra.4s v0, v0, #0x1a
2196 # CHECK: usra.2d v0, v0, #0x39
2204 # CHECK: pmull.8h v0, v0, v0
2205 # CHECK: pmull2.8h v0, v0, v0
2206 # CHECK: pmull.1q v0, v0, v0
2207 # CHECK: pmull2.1q v0, v0, v0
2211 # CHECK: faddp.2d d1, v2
2212 # CHECK: faddp.2s s3, v4
2223 # CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1
2224 # CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1
2225 # CHECK: tbl.16b v2, { v5 }, v1
2226 # CHECK: tbl.8b v0, { v5 }, v1
2227 # CHECK: tbl.16b v2, { v5, v6, v7 }, v1
2228 # CHECK: tbl.8b v0, { v5, v6, v7 }, v1
2229 # CHECK: tbl.16b v2, { v6, v7 }, v1
2230 # CHECK: tbl.8b v0, { v6, v7 }, v1
2241 # CHECK: tbx.16b v2, { v4, v5, v6, v7 }, v1
2242 # CHECK: tbx.8b v0, { v4, v5, v6, v7 }, v1
2243 # CHECK: tbx.16b v2, { v5 }, v1
2244 # CHECK: tbx.8b v0, { v5 }, v1
2245 # CHECK: tbx.16b v2, { v5, v6, v7 }, v1
2246 # CHECK: tbx.8b v0, { v5, v6, v7 }, v1
2247 # CHECK: tbx.16b v2, { v6, v7 }, v1
2248 # CHECK: tbx.8b v0, { v6, v7 }, v1
2256 # CHECK: smlal.8h v0, v0, v0
2257 # CHECK: smlal2.8h v0, v0, v0
2258 # CHECK: smlal.2d v0, v0, v0
2259 # CHECK: smlal2.2d v0, v0, v0
2266 # CHECK: umlal.8h v0, v0, v0
2267 # CHECK: umlal2.8h v0, v0, v0
2268 # CHECK: umlal.2d v0, v0, v0
2269 # CHECK: umlal2.2d v0, v0, v0
2276 # CHECK: sqdmlal s0, h0, h0
2277 # CHECK: sqdmlal d0, s0, s0
2278 # CHECK: sqdmlsl s0, h0, h0
2279 # CHECK: sqdmlsl d0, s0, s0
2285 # CHECK: ld1r.8h { v10 }, [x13], x7
2286 # CHECK: ld1r.4s { v10 }, [x13], x7
2287 # CHECK: ld1r.16b { v10 }, [x13], x7
2291 # CHECK: sqdmull s0, h0, h0
2292 # CHECK: sqdmull d0, s0, s0
2297 # CHECK: frsqrte s0, s0
2298 # CHECK: frsqrte d0, d0
2304 # CHECK: ld1r.2d { v10 }, [x14], x7
2305 # CHECK: ld2r.4s { v10, v11 }, [x15], x7
2306 # CHECK: ld3r.4s { v10, v11, v12 }, [x15], x7
2307 # CHECK: ld4r.4s { v10, v11, v12, v13 }, [x15], x7
2309 #===-------------------------------------------------------------------------===
2310 # AdvSIMD scalar three same
2311 #===-------------------------------------------------------------------------===
2313 # CHECK: fmulx s2, s3, s1
2315 # CHECK: fmulx d2, d3, d1
2320 # CHECK: ld1.4s { v8, v9, v10 }, [sp], #48