1 # RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s
3 #==---------------------------------------------------------------------------==
4 # 5.4.2 Logical (immediate)
5 #==---------------------------------------------------------------------------==
18 # CHECK: and w0, w0, #0x1
19 # CHECK: and x0, x0, #0x1
20 # CHECK: and w1, w2, #0xf
21 # CHECK: and x1, x2, #0xf
22 # CHECK: and sp, x5, #0xfffffffffffffff0
23 # CHECK: ands w0, w0, #0x1
24 # CHECK: ands x0, x0, #0x1
25 # CHECK: ands w1, w2, #0xf
26 # CHECK: ands x1, x2, #0xf
33 # CHECK: eor w1, w2, #0x4000
34 # CHECK: eor x1, x2, #0x8000
35 # CHECK: eor sp, x2, #0x8000
41 # CHECK: orr w1, w2, #0x4000
42 # CHECK: orr x1, x2, #0x8000
43 # CHECK: orr sp, x2, #0x8000
45 #==---------------------------------------------------------------------------==
46 # 5.5.3 Logical (shifted register)
47 #==---------------------------------------------------------------------------==
60 # CHECK: and w1, w2, w3
61 # CHECK: and x1, x2, x3
62 # CHECK: and w1, w2, w3, lsl #2
63 # CHECK: and x1, x2, x3, lsl #2
64 # CHECK: and w1, w2, w3, lsr #2
65 # CHECK: and x1, x2, x3, lsr #2
66 # CHECK: and w1, w2, w3, asr #2
67 # CHECK: and x1, x2, x3, asr #2
68 # CHECK: and w1, w2, w3, ror #2
69 # CHECK: and x1, x2, x3, ror #2
82 # CHECK: ands w1, w2, w3
83 # CHECK: ands x1, x2, x3
84 # CHECK: ands w1, w2, w3, lsl #2
85 # CHECK: ands x1, x2, x3, lsl #2
86 # CHECK: ands w1, w2, w3, lsr #2
87 # CHECK: ands x1, x2, x3, lsr #2
88 # CHECK: ands w1, w2, w3, asr #2
89 # CHECK: ands x1, x2, x3, asr #2
90 # CHECK: ands w1, w2, w3, ror #2
91 # CHECK: ands x1, x2, x3, ror #2
104 # CHECK: bic w1, w2, w3
105 # CHECK: bic x1, x2, x3
106 # CHECK: bic w1, w2, w3, lsl #3
107 # CHECK: bic x1, x2, x3, lsl #3
108 # CHECK: bic w1, w2, w3, lsr #3
109 # CHECK: bic x1, x2, x3, lsr #3
110 # CHECK: bic w1, w2, w3, asr #3
111 # CHECK: bic x1, x2, x3, asr #3
112 # CHECK: bic w1, w2, w3, ror #3
113 # CHECK: bic x1, x2, x3, ror #3
126 # CHECK: bics w1, w2, w3
127 # CHECK: bics x1, x2, x3
128 # CHECK: bics w1, w2, w3, lsl #3
129 # CHECK: bics x1, x2, x3, lsl #3
130 # CHECK: bics w1, w2, w3, lsr #3
131 # CHECK: bics x1, x2, x3, lsr #3
132 # CHECK: bics w1, w2, w3, asr #3
133 # CHECK: bics x1, x2, x3, asr #3
134 # CHECK: bics w1, w2, w3, ror #3
135 # CHECK: bics x1, x2, x3, ror #3
148 # CHECK: eon w1, w2, w3
149 # CHECK: eon x1, x2, x3
150 # CHECK: eon w1, w2, w3, lsl #4
151 # CHECK: eon x1, x2, x3, lsl #4
152 # CHECK: eon w1, w2, w3, lsr #4
153 # CHECK: eon x1, x2, x3, lsr #4
154 # CHECK: eon w1, w2, w3, asr #4
155 # CHECK: eon x1, x2, x3, asr #4
156 # CHECK: eon w1, w2, w3, ror #4
157 # CHECK: eon x1, x2, x3, ror #4
170 # CHECK: eor w1, w2, w3
171 # CHECK: eor x1, x2, x3
172 # CHECK: eor w1, w2, w3, lsl #5
173 # CHECK: eor x1, x2, x3, lsl #5
174 # CHECK: eor w1, w2, w3, lsr #5
175 # CHECK: eor x1, x2, x3, lsr #5
176 # CHECK: eor w1, w2, w3, asr #5
177 # CHECK: eor x1, x2, x3, asr #5
178 # CHECK: eor w1, w2, w3, ror #5
179 # CHECK: eor x1, x2, x3, ror #5
192 # CHECK: orr w1, w2, w3
193 # CHECK: orr x1, x2, x3
194 # CHECK: orr w1, w2, w3, lsl #6
195 # CHECK: orr x1, x2, x3, lsl #6
196 # CHECK: orr w1, w2, w3, lsr #6
197 # CHECK: orr x1, x2, x3, lsr #6
198 # CHECK: orr w1, w2, w3, asr #6
199 # CHECK: orr x1, x2, x3, asr #6
200 # CHECK: orr w1, w2, w3, ror #6
201 # CHECK: orr x1, x2, x3, ror #6
214 # CHECK: orn w1, w2, w3
215 # CHECK: orn x1, x2, x3
216 # CHECK: orn w1, w2, w3, lsl #7
217 # CHECK: orn x1, x2, x3, lsl #7
218 # CHECK: orn w1, w2, w3, lsr #7
219 # CHECK: orn x1, x2, x3, lsr #7
220 # CHECK: orn w1, w2, w3, asr #7
221 # CHECK: orn x1, x2, x3, asr #7
222 # CHECK: orn w1, w2, w3, ror #7
223 # CHECK: orn x1, x2, x3, ror #7