llvm/test/MC/Disassembler/AArch64/armv9-sysreg128.txt

   1 # RUN: llvm-mc -triple aarch64 -mattr=+d128                   --disassemble -show-encoding %s -o - | FileCheck %s --check-prefix=WITHOUT
   2 # RUN: llvm-mc -triple aarch64 -mattr=+d128,+the,+el2vmsa,+vh --disassemble -show-encoding %s -o - | FileCheck %s --check-prefix=W_FEATS
   3
   4 # RUN: llvm-mc -triple aarch64 --disassemble -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128
   5
   6 0x00,0x20,0x78,0xd5
   7 0x20,0x20,0x78,0xd5
   8 0x00,0x74,0x78,0xd5
   9 0x60,0xd0,0x78,0xd5
  10 0xc0,0xd0,0x78,0xd5
  11 0x00,0x20,0x7c,0xd5
  12 0x20,0x20,0x7c,0xd5
  13 0x00,0x21,0x7c,0xd5
  14 0x00,0x21,0x7c,0xd5
  15 0x02,0x21,0x7c,0xd5
  16 0x04,0x21,0x7c,0xd5
  17 0x06,0x21,0x7c,0xd5
  18 0x08,0x21,0x7c,0xd5
  19 0x0a,0x21,0x7c,0xd5
  20 0x0c,0x21,0x7c,0xd5
  21 0x0e,0x21,0x7c,0xd5
  22 0x10,0x21,0x7c,0xd5
  23 0x12,0x21,0x7c,0xd5
  24 0x14,0x21,0x7c,0xd5
  25 0x16,0x21,0x7c,0xd5
  26 0x18,0x21,0x7c,0xd5
  27 0x1a,0x21,0x7c,0xd5
  28
  29 # WITHOUT: mrrs x0, x1, TTBR0_EL1               // encoding: [0x00,0x20,0x78,0xd5]
  30 # WITHOUT: mrrs x0, x1, TTBR1_EL1               // encoding: [0x20,0x20,0x78,0xd5]
  31 # WITHOUT: mrrs x0, x1, PAR_EL1                 // encoding: [0x00,0x74,0x78,0xd5]
  32 # WITHOUT: mrrs x0, x1, S3_0_C13_C0_3           // encoding: [0x60,0xd0,0x78,0xd5]
  33 # WITHOUT: mrrs x0, x1, S3_0_C13_C0_6           // encoding: [0xc0,0xd0,0x78,0xd5]
  34 # WITHOUT: mrrs x0, x1, S3_4_C2_C0_0            // encoding: [0x00,0x20,0x7c,0xd5]
  35 # WITHOUT: mrrs x0, x1, S3_4_C2_C0_1            // encoding: [0x20,0x20,0x7c,0xd5]
  36 # WITHOUT: mrrs x0, x1, S3_4_C2_C1_0            // encoding: [0x00,0x21,0x7c,0xd5]
  37 # WITHOUT: mrrs x0, x1, S3_4_C2_C1_0            // encoding: [0x00,0x21,0x7c,0xd5]
  38 # WITHOUT: mrrs x2, x3, S3_4_C2_C1_0            // encoding: [0x02,0x21,0x7c,0xd5]
  39 # WITHOUT: mrrs x4, x5, S3_4_C2_C1_0            // encoding: [0x04,0x21,0x7c,0xd5]
  40 # WITHOUT: mrrs x6, x7, S3_4_C2_C1_0            // encoding: [0x06,0x21,0x7c,0xd5]
  41 # WITHOUT: mrrs x8, x9, S3_4_C2_C1_0            // encoding: [0x08,0x21,0x7c,0xd5]
  42 # WITHOUT: mrrs x10, x11, S3_4_C2_C1_0          // encoding: [0x0a,0x21,0x7c,0xd5]
  43 # WITHOUT: mrrs x12, x13, S3_4_C2_C1_0          // encoding: [0x0c,0x21,0x7c,0xd5]
  44 # WITHOUT: mrrs x14, x15, S3_4_C2_C1_0          // encoding: [0x0e,0x21,0x7c,0xd5]
  45 # WITHOUT: mrrs x16, x17, S3_4_C2_C1_0          // encoding: [0x10,0x21,0x7c,0xd5]
  46 # WITHOUT: mrrs x18, x19, S3_4_C2_C1_0          // encoding: [0x12,0x21,0x7c,0xd5]
  47 # WITHOUT: mrrs x20, x21, S3_4_C2_C1_0          // encoding: [0x14,0x21,0x7c,0xd5]
  48 # WITHOUT: mrrs x22, x23, S3_4_C2_C1_0          // encoding: [0x16,0x21,0x7c,0xd5]
  49 # WITHOUT: mrrs x24, x25, S3_4_C2_C1_0          // encoding: [0x18,0x21,0x7c,0xd5]
  50 # WITHOUT: mrrs x26, x27, S3_4_C2_C1_0          // encoding: [0x1a,0x21,0x7c,0xd5]
  51
  52 # W_FEATS: mrrs x0, x1, TTBR0_EL1               // encoding: [0x00,0x20,0x78,0xd5]
  53 # W_FEATS: mrrs x0, x1, TTBR1_EL1               // encoding: [0x20,0x20,0x78,0xd5]
  54 # W_FEATS: mrrs x0, x1, PAR_EL1                 // encoding: [0x00,0x74,0x78,0xd5]
  55 # W_FEATS: mrrs x0, x1, RCWSMASK_EL1            // encoding: [0x60,0xd0,0x78,0xd5]
  56 # W_FEATS: mrrs x0, x1, RCWMASK_EL1             // encoding: [0xc0,0xd0,0x78,0xd5]
  57 # W_FEATS: mrrs x0, x1, TTBR0_EL2               // encoding: [0x00,0x20,0x7c,0xd5]
  58 # W_FEATS: mrrs x0, x1, TTBR1_EL2               // encoding: [0x20,0x20,0x7c,0xd5]
  59 # W_FEATS: mrrs x0, x1, VTTBR_EL2               // encoding: [0x00,0x21,0x7c,0xd5]
  60 # W_FEATS: mrrs x0, x1, VTTBR_EL2               // encoding: [0x00,0x21,0x7c,0xd5]
  61 # W_FEATS: mrrs x2, x3, VTTBR_EL2               // encoding: [0x02,0x21,0x7c,0xd5]
  62 # W_FEATS: mrrs x4, x5, VTTBR_EL2               // encoding: [0x04,0x21,0x7c,0xd5]
  63 # W_FEATS: mrrs x6, x7, VTTBR_EL2               // encoding: [0x06,0x21,0x7c,0xd5]
  64 # W_FEATS: mrrs x8, x9, VTTBR_EL2               // encoding: [0x08,0x21,0x7c,0xd5]
  65 # W_FEATS: mrrs x10, x11, VTTBR_EL2             // encoding: [0x0a,0x21,0x7c,0xd5]
  66 # W_FEATS: mrrs x12, x13, VTTBR_EL2             // encoding: [0x0c,0x21,0x7c,0xd5]
  67 # W_FEATS: mrrs x14, x15, VTTBR_EL2             // encoding: [0x0e,0x21,0x7c,0xd5]
  68 # W_FEATS: mrrs x16, x17, VTTBR_EL2             // encoding: [0x10,0x21,0x7c,0xd5]
  69 # W_FEATS: mrrs x18, x19, VTTBR_EL2             // encoding: [0x12,0x21,0x7c,0xd5]
  70 # W_FEATS: mrrs x20, x21, VTTBR_EL2             // encoding: [0x14,0x21,0x7c,0xd5]
  71 # W_FEATS: mrrs x22, x23, VTTBR_EL2             // encoding: [0x16,0x21,0x7c,0xd5]
  72 # W_FEATS: mrrs x24, x25, VTTBR_EL2             // encoding: [0x18,0x21,0x7c,0xd5]
  73 # W_FEATS: mrrs x26, x27, VTTBR_EL2             // encoding: [0x1a,0x21,0x7c,0xd5]
  74
  75 # ERROR-NO-D128: warning: invalid instruction encoding
  76
  77
  78 0x00,0x20,0x58,0xd5
  79 0x20,0x20,0x58,0xd5
  80 0x00,0x74,0x58,0xd5
  81 0x60,0xd0,0x58,0xd5
  82 0xc0,0xd0,0x58,0xd5
  83 0x00,0x20,0x5c,0xd5
  84 0x20,0x20,0x5c,0xd5
  85 0x00,0x21,0x5c,0xd5
  86 0x00,0x21,0x5c,0xd5
  87 0x02,0x21,0x5c,0xd5
  88 0x04,0x21,0x5c,0xd5
  89 0x06,0x21,0x5c,0xd5
  90 0x08,0x21,0x5c,0xd5
  91 0x0a,0x21,0x5c,0xd5
  92 0x0c,0x21,0x5c,0xd5
  93 0x0e,0x21,0x5c,0xd5
  94 0x10,0x21,0x5c,0xd5
  95 0x12,0x21,0x5c,0xd5
  96 0x14,0x21,0x5c,0xd5
  97 0x16,0x21,0x5c,0xd5
  98 0x18,0x21,0x5c,0xd5
  99 0x1a,0x21,0x5c,0xd5
 100
 101 # WITHOUT: msrr TTBR0_EL1, x0, x1               // encoding: [0x00,0x20,0x58,0xd5]
 102 # WITHOUT: msrr TTBR1_EL1, x0, x1               // encoding: [0x20,0x20,0x58,0xd5]
 103 # WITHOUT: msrr PAR_EL1, x0, x1                 // encoding: [0x00,0x74,0x58,0xd5]
 104 # WITHOUT: msrr S3_0_C13_C0_3, x0, x1           // encoding: [0x60,0xd0,0x58,0xd5]
 105 # WITHOUT: msrr S3_0_C13_C0_6, x0, x1           // encoding: [0xc0,0xd0,0x58,0xd5]
 106 # WITHOUT: msrr S3_4_C2_C0_0, x0, x1            // encoding: [0x00,0x20,0x5c,0xd5]
 107 # WITHOUT: msrr S3_4_C2_C0_1, x0, x1            // encoding: [0x20,0x20,0x5c,0xd5]
 108 # WITHOUT: msrr S3_4_C2_C1_0, x0, x1            // encoding: [0x00,0x21,0x5c,0xd5]
 109 # WITHOUT: msrr S3_4_C2_C1_0, x0, x1            // encoding: [0x00,0x21,0x5c,0xd5]
 110 # WITHOUT: msrr S3_4_C2_C1_0, x2, x3            // encoding: [0x02,0x21,0x5c,0xd5]
 111 # WITHOUT: msrr S3_4_C2_C1_0, x4, x5            // encoding: [0x04,0x21,0x5c,0xd5]
 112 # WITHOUT: msrr S3_4_C2_C1_0, x6, x7            // encoding: [0x06,0x21,0x5c,0xd5]
 113 # WITHOUT: msrr S3_4_C2_C1_0, x8, x9            // encoding: [0x08,0x21,0x5c,0xd5]
 114 # WITHOUT: msrr S3_4_C2_C1_0, x10, x11          // encoding: [0x0a,0x21,0x5c,0xd5]
 115 # WITHOUT: msrr S3_4_C2_C1_0, x12, x13          // encoding: [0x0c,0x21,0x5c,0xd5]
 116 # WITHOUT: msrr S3_4_C2_C1_0, x14, x15          // encoding: [0x0e,0x21,0x5c,0xd5]
 117 # WITHOUT: msrr S3_4_C2_C1_0, x16, x17          // encoding: [0x10,0x21,0x5c,0xd5]
 118 # WITHOUT: msrr S3_4_C2_C1_0, x18, x19          // encoding: [0x12,0x21,0x5c,0xd5]
 119 # WITHOUT: msrr S3_4_C2_C1_0, x20, x21          // encoding: [0x14,0x21,0x5c,0xd5]
 120 # WITHOUT: msrr S3_4_C2_C1_0, x22, x23          // encoding: [0x16,0x21,0x5c,0xd5]
 121 # WITHOUT: msrr S3_4_C2_C1_0, x24, x25          // encoding: [0x18,0x21,0x5c,0xd5]
 122 # WITHOUT: msrr S3_4_C2_C1_0, x26, x27          // encoding: [0x1a,0x21,0x5c,0xd5]
 123
 124 # W_FEATS: msrr TTBR0_EL1, x0, x1               // encoding: [0x00,0x20,0x58,0xd5]
 125 # W_FEATS: msrr TTBR1_EL1, x0, x1               // encoding: [0x20,0x20,0x58,0xd5]
 126 # W_FEATS: msrr PAR_EL1, x0, x1                 // encoding: [0x00,0x74,0x58,0xd5]
 127 # W_FEATS: msrr RCWSMASK_EL1, x0, x1            // encoding: [0x60,0xd0,0x58,0xd5]
 128 # W_FEATS: msrr RCWMASK_EL1, x0, x1             // encoding: [0xc0,0xd0,0x58,0xd5]
 129 # W_FEATS: msrr TTBR0_EL2, x0, x1               // encoding: [0x00,0x20,0x5c,0xd5]
 130 # W_FEATS: msrr TTBR1_EL2, x0, x1               // encoding: [0x20,0x20,0x5c,0xd5]
 131 # W_FEATS: msrr VTTBR_EL2, x0, x1               // encoding: [0x00,0x21,0x5c,0xd5]
 132 # W_FEATS: msrr VTTBR_EL2, x0, x1               // encoding: [0x00,0x21,0x5c,0xd5]
 133 # W_FEATS: msrr VTTBR_EL2, x2, x3               // encoding: [0x02,0x21,0x5c,0xd5]
 134 # W_FEATS: msrr VTTBR_EL2, x4, x5               // encoding: [0x04,0x21,0x5c,0xd5]
 135 # W_FEATS: msrr VTTBR_EL2, x6, x7               // encoding: [0x06,0x21,0x5c,0xd5]
 136 # W_FEATS: msrr VTTBR_EL2, x8, x9               // encoding: [0x08,0x21,0x5c,0xd5]
 137 # W_FEATS: msrr VTTBR_EL2, x10, x11             // encoding: [0x0a,0x21,0x5c,0xd5]
 138 # W_FEATS: msrr VTTBR_EL2, x12, x13             // encoding: [0x0c,0x21,0x5c,0xd5]
 139 # W_FEATS: msrr VTTBR_EL2, x14, x15             // encoding: [0x0e,0x21,0x5c,0xd5]
 140 # W_FEATS: msrr VTTBR_EL2, x16, x17             // encoding: [0x10,0x21,0x5c,0xd5]
 141 # W_FEATS: msrr VTTBR_EL2, x18, x19             // encoding: [0x12,0x21,0x5c,0xd5]
 142 # W_FEATS: msrr VTTBR_EL2, x20, x21             // encoding: [0x14,0x21,0x5c,0xd5]
 143 # W_FEATS: msrr VTTBR_EL2, x22, x23             // encoding: [0x16,0x21,0x5c,0xd5]
 144 # W_FEATS: msrr VTTBR_EL2, x24, x25             // encoding: [0x18,0x21,0x5c,0xd5]
 145 # W_FEATS: msrr VTTBR_EL2, x26, x27             // encoding: [0x1a,0x21,0x5c,0xd5]
 146
 147 # ERROR-NO-D128: warning: invalid instruction encoding