llvm/test/MC/Disassembler/AArch64/armv9.6a-srmask.txt

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mc -triple aarch64 -disassemble < %s 2> %t | FileCheck %s
   3
   4 [0x03,0x14,0x38,0xd5]
   5 [0x03,0x14,0x3c,0xd5]
   6 [0x03,0x14,0x3d,0xd5]
   7 [0x43,0x14,0x38,0xd5]
   8 [0x43,0x14,0x3c,0xd5]
   9 [0x43,0x14,0x3d,0xd5]
  10 [0x63,0x14,0x38,0xd5]
  11 [0x63,0x14,0x3c,0xd5]
  12 [0x63,0x14,0x3d,0xd5]
  13 [0x83,0x14,0x38,0xd5]
  14 [0xc3,0x14,0x38,0xd5]
  15 [0xe3,0x14,0x38,0xd5]
  16 [0x43,0x27,0x38,0xd5]
  17 [0x43,0x27,0x3c,0xd5]
  18 [0x43,0x27,0x3d,0xd5]
  19 [0x63,0x27,0x38,0xd5]
  20 [0x63,0x27,0x3c,0xd5]
  21 [0x63,0x27,0x3d,0xd5]
  22 [0xc3,0x27,0x38,0xd5]
  23 [0xe3,0x27,0x38,0xd5]
  24 [0x23,0x14,0x38,0xd5]
  25 [0x23,0x14,0x3c,0xd5]
  26 [0x23,0x14,0x3d,0xd5]
  27 [0xa3,0x14,0x38,0xd5]
  28
  29 [0x03,0x14,0x18,0xd5]
  30 [0x03,0x14,0x1c,0xd5]
  31 [0x03,0x14,0x1d,0xd5]
  32 [0x43,0x14,0x18,0xd5]
  33 [0x43,0x14,0x1c,0xd5]
  34 [0x43,0x14,0x1d,0xd5]
  35 [0x63,0x14,0x18,0xd5]
  36 [0x63,0x14,0x1c,0xd5]
  37 [0x63,0x14,0x1d,0xd5]
  38 [0x83,0x14,0x18,0xd5]
  39 [0xc3,0x14,0x18,0xd5]
  40 [0xe3,0x14,0x18,0xd5]
  41 [0x43,0x27,0x18,0xd5]
  42 [0x43,0x27,0x1c,0xd5]
  43 [0x43,0x27,0x1d,0xd5]
  44 [0x63,0x27,0x18,0xd5]
  45 [0x63,0x27,0x1c,0xd5]
  46 [0x63,0x27,0x1d,0xd5]
  47 [0xc3,0x27,0x18,0xd5]
  48 [0xe3,0x27,0x18,0xd5]
  49 [0x23,0x14,0x18,0xd5]
  50 [0x23,0x14,0x1c,0xd5]
  51 [0x23,0x14,0x1d,0xd5]
  52 [0xa3,0x14,0x18,0xd5]
  53
  54 # CHECK:        mrs     x3, SCTLRMASK_EL1
  55 # CHECK-NEXT:   mrs     x3, SCTLRMASK_EL2
  56 # CHECK-NEXT:   mrs     x3, SCTLRMASK_EL12
  57 # CHECK-NEXT:   mrs     x3, CPACRMASK_EL1
  58 # CHECK-NEXT:   mrs     x3, CPTRMASK_EL2
  59 # CHECK-NEXT:   mrs     x3, CPACRMASK_EL12
  60 # CHECK-NEXT:   mrs     x3, SCTLR2MASK_EL1
  61 # CHECK-NEXT:   mrs     x3, SCTLR2MASK_EL2
  62 # CHECK-NEXT:   mrs     x3, SCTLR2MASK_EL12
  63 # CHECK-NEXT:   mrs     x3, CPACRALIAS_EL1
  64 # CHECK-NEXT:   mrs     x3, SCTLRALIAS_EL1
  65 # CHECK-NEXT:   mrs     x3, SCTLR2ALIAS_EL1
  66 # CHECK-NEXT:   mrs     x3, TCRMASK_EL1
  67 # CHECK-NEXT:   mrs     x3, TCRMASK_EL2
  68 # CHECK-NEXT:   mrs     x3, TCRMASK_EL12
  69 # CHECK-NEXT:   mrs     x3, TCR2MASK_EL1
  70 # CHECK-NEXT:   mrs     x3, TCR2MASK_EL2
  71 # CHECK-NEXT:   mrs     x3, TCR2MASK_EL12
  72 # CHECK-NEXT:   mrs     x3, TCRALIAS_EL1
  73 # CHECK-NEXT:   mrs     x3, TCR2ALIAS_EL1
  74 # CHECK-NEXT:   mrs     x3, ACTLRMASK_EL1
  75 # CHECK-NEXT:   mrs     x3, ACTLRMASK_EL2
  76 # CHECK-NEXT:   mrs     x3, ACTLRMASK_EL12
  77 # CHECK-NEXT:   mrs     x3, ACTLRALIAS_EL1
  78 # CHECK-NEXT:   msr     SCTLRMASK_EL1, x3
  79 # CHECK-NEXT:   msr     SCTLRMASK_EL2, x3
  80 # CHECK-NEXT:   msr     SCTLRMASK_EL12, x3
  81 # CHECK-NEXT:   msr     CPACRMASK_EL1, x3
  82 # CHECK-NEXT:   msr     CPTRMASK_EL2, x3
  83 # CHECK-NEXT:   msr     CPACRMASK_EL12, x3
  84 # CHECK-NEXT:   msr     SCTLR2MASK_EL1, x3
  85 # CHECK-NEXT:   msr     SCTLR2MASK_EL2, x3
  86 # CHECK-NEXT:   msr     SCTLR2MASK_EL12, x3
  87 # CHECK-NEXT:   msr     CPACRALIAS_EL1, x3
  88 # CHECK-NEXT:   msr     SCTLRALIAS_EL1, x3
  89 # CHECK-NEXT:   msr     SCTLR2ALIAS_EL1, x3
  90 # CHECK-NEXT:   msr     TCRMASK_EL1, x3
  91 # CHECK-NEXT:   msr     TCRMASK_EL2, x3
  92 # CHECK-NEXT:   msr     TCRMASK_EL12, x3
  93 # CHECK-NEXT:   msr     TCR2MASK_EL1, x3
  94 # CHECK-NEXT:   msr     TCR2MASK_EL2, x3
  95 # CHECK-NEXT:   msr     TCR2MASK_EL12, x3
  96 # CHECK-NEXT:   msr     TCRALIAS_EL1, x3
  97 # CHECK-NEXT:   msr     TCR2ALIAS_EL1, x3
  98 # CHECK-NEXT:   msr     ACTLRMASK_EL1, x3
  99 # CHECK-NEXT:   msr     ACTLRMASK_EL2, x3
 100 # CHECK-NEXT:   msr     ACTLRMASK_EL12, x3
 101 # CHECK-NEXT:   msr     ACTLRALIAS_EL1, x3