[RISCV] Add ESWIN EIC770X (SiFive P550) to getHostCPUNameForRISCV. (#125277)
[llvm-project.git] / llvm / test / MC / Mips / mips2 / invalid-mips4-wrong-error.s
blob5fdc7174f59c80708d3ba78944179c53f3d72152
1 # Instructions that are invalid and are correctly rejected but used to emit
2 # the wrong error message.
4 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \
5 # RUN: 2>%t1
6 # RUN: FileCheck %s < %t1
8 .set noat
9 bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
10 bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level
11 scd $15,-8243($sp) # CHECK: :[[#@LINE]]:[[#]]: error: instruction requires a CPU feature not currently enabled
12 sdl $a3,-20961($s8) # CHECK: :[[#@LINE]]:[[#]]: error: instruction requires a CPU feature not currently enabled
13 sdr $11,-20423($12) # CHECK: :[[#@LINE]]:[[#]]: error: instruction requires a CPU feature not currently enabled