llvm/test/MC/RISCV/rv32zhinx-invalid.s

   1 # RUN: not llvm-mc -triple riscv32 -mattr=+zhinx %s 2>&1 | FileCheck %s
   2
   3 # Not support float registers
   4 flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}}
   5 fadd.h fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}}
   6
   7 # Invalid instructions
   8 fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
   9 fmv.x.h s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
  10
  11 # Invalid register names
  12 fadd.h a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
  13 fsgnjn.h a100, a2, a3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
  14
  15 # Rounding mode when a register is expected
  16 fmadd.h x10, x11, x12, ree # CHECK: :[[@LINE]]:24: error: invalid operand for instruction
  17
  18 # Invalid rounding modes
  19 fmadd.h x10, x11, x12, x13, ree # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
  20 fmsub.h x14, x15, x16, x17, 0 # CHECK: :[[@LINE]]:29: error: operand must be a valid floating point rounding mode mnemonic
  21 fnmsub.h x18, x19, x20, x21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic
  22
  23 # FP registers where integer regs are expected
  24 fcvt.wu.h ft2, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction