llvm/test/MC/RISCV/xqcicsr-valid.s

   1 # Xqcicsr - Qualcomm uC CSR Extension
   2 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -M no-aliases -show-encoding \
   3 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
   4 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \
   5 # RUN:     | llvm-objdump --mattr=+experimental-xqcicsr -M no-aliases --no-print-imm-hex -d - \
   6 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
   7 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -show-encoding \
   8 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
   9 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \
  10 # RUN:     | llvm-objdump --mattr=+experimental-xqcicsr --no-print-imm-hex -d - \
  11 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
  12
  13 # CHECK-INST: qc.csrrwr  a0, t0, s4
  14 # CHECK-ENC: encoding: [0x73,0x85,0x42,0x8d]
  15 qc.csrrwr  x10, x5, x20
  16
  17 # CHECK-INST: qc.csrrwri s4, 31, a2
  18 # CHECK-ENC: encoding: [0x73,0x8a,0xcf,0x8e]
  19 qc.csrrwri x20, 31, x12