[RISCV] Match vcompress during shuffle lowering (#117748)
[llvm-project.git] / llvm / test / TableGen / FixedLenDecoderEmitter / InitValue.td
blob03847439ffc2e690cfb9fec6dd7b3eeb6b753e78
1 // RUN: llvm-tblgen -gen-disassembler -I %p/../../../include %s | FileCheck %s
3 include "llvm/Target/Target.td"
5 def archInstrInfo : InstrInfo { }
7 def arch : Target {
8     let InstructionSet = archInstrInfo;
11 let OutOperandList = (outs), Size = 2 in {
13 def foo : Instruction {
14     let InOperandList = (ins i32imm:$factor);
15     field bits<16> Inst;
16     field bits<16> SoftFail = 0;
17     bits<8> factor;
18     let factor{0} = 0; // zero initial value
19     let Inst{15...8} = factor{7...0};
20     }
22 def bar : Instruction {
23     let InOperandList = (ins i32imm:$factor);
24     field bits<16> Inst;
25     field bits<16> SoftFail = 0;
26     bits<8> factor;
27     let factor{0} = 1; // non-zero initial value
28     let Inst{15...8} = factor{7...0};
29     }
31 def bax : Instruction {
32     let InOperandList = (ins i32imm:$factor);
33     field bits<16> Inst;
34     field bits<16> SoftFail = 0;
35     bits<33> factor;
36     let factor{32} = 1; // non-zero initial value
37     let Inst{15...8} = factor{32...25};
38     }
42 // CHECK: tmp = fieldFromInstruction(insn, 9, 7) << 1;
43 // CHECK: tmp = 0x1;
44 // CHECK: insertBits(tmp, fieldFromInstruction(insn, 9, 7), 1, 7);
45 // CHECK: tmp = 0x100000000;
46 // CHECK: insertBits(tmp, fieldFromInstruction(insn, 8, 7), 25, 7);